Re: [Qemu-devel] [PATCH] Allow PIR read in privileged mode

> According to PowerISA, the PIR register should be readable in privileged mode > also, not only in hypervisor privileged mode. The code makes sense but it doesn't seem created by git format-patch. If so, could you please follow the instructions from https://wiki.qemu.org/Contribute/SubmitAPatch

Re: [Qemu-devel] [PATCH v2] dump: Show custom message for ENOSPC

On Fri, Feb 09, 2018 at 02:57:33PM -0600, Eric Blake wrote: > On 02/09/2018 02:26 PM, Yasmin Beatriz wrote: > > This patch intends to make a more specific message for when > > the system has not enough space to save guest memory. > > > > Reported-by: yilzh...@redhat.com > > Cc: Jose Ricardo

Re: [Qemu-devel] [PATCH] Revert "virtio: postpone the execution of event_notifier_cleanup function"

On Tue, Jan 23, 2018 at 05:22:12PM +0200, Michael S. Tsirkin wrote: > On Tue, Jan 23, 2018 at 11:20:21AM -0200, Jose Ricardo Ziviani wrote: > > This reverts commit 4fe6d78b2e241f41208dfb07605aace4becfc747. > > > > As reported > >

Re: [Qemu-devel] [PATCH] Revert "virtio: postpone the execution of event_notifier_cleanup function"

On Tue, Jan 23, 2018 at 05:22:12PM +0200, Michael S. Tsirkin wrote: > On Tue, Jan 23, 2018 at 11:20:21AM -0200, Jose Ricardo Ziviani wrote: > > This reverts commit 4fe6d78b2e241f41208dfb07605aace4becfc747. > > > > As reported > >

Re: [Qemu-devel] virtio block device is not working

On Tue, Jan 23, 2018 at 01:05:28AM -0200, jos...@linux.vnet.ibm.com wrote: > Hello people! > > I'm not able to boot any guest that sets a virtio block device like: > (branch master) > > [PPC64] > qemu-system-ppc64 -cpu POWER8 -nographic -vga none -m 4G -M > pseries,accel=kvm,kvm-type=PR -drive

[Qemu-devel] virtio block device is not working

Hello people! I'm not able to boot any guest that sets a virtio block device like: (branch master) [PPC64] qemu-system-ppc64 -cpu POWER8 -nographic -vga none -m 4G -M pseries,accel=kvm,kvm-type=PR -drive file=disk.qcow2,if=virtio QEMU Starting Build Date = Dec 18 2017 13:08:00 FW Version =

Re: [Qemu-devel] [PATCH 1/2] target/ppc: Clarify compat mode max_threads value

On Mon, Jan 15, 2018 at 06:27:14PM +1100, David Gibson wrote: > We recently had some discussions that were sidetracked for a while, because > nearly everyone misapprehended the purpose of the 'max_threads' field in > the compatiblity modes table. It's all about guest expectations, not host >

Re: [Qemu-devel] [PATCH 2/2] spapr: Adjust default VSMT value for better migration compatibility

On Mon, Jan 15, 2018 at 06:27:15PM +1100, David Gibson wrote: > fa98fbfc "PC: KVM: Support machine option to set VSMT mode" introduced the > "vsmt" parameter for the pseries machine type, which controls the spacing > of the vcpu ids of thread 0 for each virtual core. This was done to bring > some

Re: [Qemu-devel] [Qemu-ppc] [PATCH 1/1] spapr: Check SMT based on KVM_CAP_PPC_SMT_POSSIBLE

On Fri, Jan 12, 2018 at 02:46:19PM +1100, David Gibson wrote: > On Fri, Jan 12, 2018 at 01:16:22AM +1100, David Gibson wrote: > > On Fri, Jan 05, 2018 at 10:47:22PM -0200, Jose Ricardo Ziviani wrote: > > > Power9 supports 4 HW threads/core but it's possible to emulate > > > doorbells to implement

Re: [Qemu-devel] [Qemu-ppc] [PATCH 1/1] spapr: Check SMT based on KVM_CAP_PPC_SMT_POSSIBLE

On Tue, Jan 09, 2018 at 01:48:13PM +0100, Greg Kurz wrote: > On Fri, 5 Jan 2018 22:47:22 -0200 > Jose Ricardo Ziviani wrote: > > > Power9 supports 4 HW threads/core but it's possible to emulate > > doorbells to implement virtual SMT. KVM has the

Re: [Qemu-devel] [QEMU-PPC] [RFC 2/3] hw/spapr/spapr_caps: Add new caps safe_[cache/bounds_check/indirect_branch]

On Tue, Jan 09, 2018 at 08:21:02PM +1100, Suraj Jitindar Singh wrote: > This patch adds three new capabilities: > cap-cfpc -> safe_cache > cap-sbbc -> safe_bounds_check > cap-ibs -> safe_indirect_branch > > Each capability is tristate with the possible values "broken", > "workaround" or "fixed".

Re: [Qemu-devel] [Qemu-ppc] [PATCH] target/ppc/cpu-models: set POWER9_v1.0 as POWER9 DD1

On Fri, Jun 23, 2017 at 04:10:55PM +0200, Laurent Vivier wrote: > On 23/06/2017 11:21, David Gibson wrote: > > On Thu, Jun 22, 2017 at 01:31:24PM +0200, Thomas Huth wrote: > >> On 22.06.2017 13:26, Laurent Vivier wrote: > >>> CPU_POWERPC_POWER9_DD1 is 0x004E0100, so this is the POWER9 v1.0. > >>>

Re: [Qemu-devel] [PATCH Risu v3 4/4] build: Add support to PowerPC BE and remove ARCH

On Tue, May 30, 2017 at 03:27:33PM +0100, Peter Maydell wrote: > On 25 May 2017 at 20:10, Jose Ricardo Ziviani > wrote: > > Essentialy the code for PowerPC BE and LE are the same, so this patch > > renames all *ppc64le.* files to *ppc64.* and reflects such in the > >

Re: [Qemu-devel] [PATCH risu] ppc64: Fix patterns for rotate doubleword instructions

On Tue, May 23, 2017 at 11:33:03PM -0300, jos...@linux.vnet.ibm.com wrote: > On Tue, May 23, 2017 at 11:47:30AM +0530, Nikunj A Dadhania wrote: > > G 3 writes: > > > > > On May 22, 2017, at 4:32 AM, qemu-devel-requ...@nongnu.org wrote: > > > > > > Hello I have also

Re: [Qemu-devel] [PATCH risu] ppc64: Fix patterns for rotate doubleword instructions

On Tue, May 23, 2017 at 11:47:30AM +0530, Nikunj A Dadhania wrote: > G 3 writes: > > > On May 22, 2017, at 4:32 AM, qemu-devel-requ...@nongnu.org wrote: > > > > Hello I have also done some work risu. My patches add ppc32 support. > > Well my patches were made to work

Re: [Qemu-devel] [Qemu-ppc] [PATCH] Revert "target-ppc/kvm: Enable in-kernel TCE acceleration for multi-tce"

On Tue, May 09, 2017 at 07:14:19PM +1000, Alexey Kardashevskiy wrote: > On 09/05/17 15:22, David Gibson wrote: > > On Tue, May 09, 2017 at 07:25:51AM +1000, Alexey Kardashevskiy wrote: > >> On 09/05/17 06:17, Jose Ricardo Ziviani wrote: > >>> This reverts commit

Re: [Qemu-devel] [Qemu-ppc] [PATCH] Revert "target-ppc/kvm: Enable in-kernel TCE acceleration for multi-tce"

On Tue, May 09, 2017 at 03:22:44PM +1000, David Gibson wrote: > On Tue, May 09, 2017 at 07:25:51AM +1000, Alexey Kardashevskiy wrote: > > On 09/05/17 06:17, Jose Ricardo Ziviani wrote: > > > This reverts commit 3dc410ae83e6cb76c81ea30a05d62596092b3165. > > > > > > Booting a radix guest in Power9

Re: [Qemu-devel] [Qemu-ppc] ppc/spapr: Radix guest causing host kernel oops

On Mon, May 08, 2017 at 02:48:58PM +0530, Bharata B Rao wrote: > Hi, > > With ppc-for-2.10 branch of dwg's tree, starting a radix guest is currently > causing a host kernel oops like this: > > Unable to handle kernel paging request for data at address 0xe64bb17da64ab078 > Faulting instruction

Re: [Qemu-devel] [PATCH 0/2] VFIO: Make 8-byte accesses atomic

On Fri, Apr 21, 2017 at 12:06:15PM +0200, Paolo Bonzini wrote: > > > On 20/04/2017 18:03, Alex Williamson wrote: > > On Thu, 20 Apr 2017 00:19:23 -0700 > > Richard Henderson wrote: > > > >> On 04/19/2017 12:44 PM, Jose Ricardo Ziviani wrote: > >>> This patchset has two

Re: [Qemu-devel] [PATCH v2] trace: add qemu mutex lock and unlock trace events

On Thu, Apr 27, 2017 at 11:59:26AM -0300, jos...@linux.vnet.ibm.com wrote: > On Thu, Apr 27, 2017 at 10:55:04AM +0200, Paolo Bonzini wrote: > > > > > > On 24/04/2017 19:19, Jose Ricardo Ziviani wrote: > > > These trace events were very useful to help me to understand and find a > > > reordering

Re: [Qemu-devel] [PATCH v2] trace: add qemu mutex lock and unlock trace events

On Thu, Apr 27, 2017 at 10:55:04AM +0200, Paolo Bonzini wrote: > > > On 24/04/2017 19:19, Jose Ricardo Ziviani wrote: > > These trace events were very useful to help me to understand and find a > > reordering issue in vfio, for example: > > > > qemu_mutex_lock locked mutex 0x10905ad8 > >

Re: [Qemu-devel] [PATCH] trace: add qemu mutex lock and unlock trace events

On Mon, Apr 24, 2017 at 10:45:52PM +0800, Fam Zheng wrote: > On Mon, 04/24 11:28, Jose Ricardo Ziviani wrote: > > These trace events were very useful to help me to understand and find a > > reordering issue in vfio, for example: > > > > qemu_mutex_lock locked mutex 0x10905ad8 > >

Re: [Qemu-devel] [PATCH Risu v2 2/3] configure: Add initial support to PPC64 (big endian)

On Mon, Mar 13, 2017 at 12:10:10PM +0100, Peter Maydell wrote: > On 9 March 2017 at 19:38, Jose Ricardo Ziviani > wrote: > > This commit set Makefile to point to ppc64le source for both archs > > (ppc64 and ppc64le) because they do the exact same thing. The > >

Re: [Qemu-devel] [PATCH Risu 2/5] risu_reginfo_ppc64le: Remove unused code from PPC64 register comparison

On Tue, Feb 28, 2017 at 01:43:22PM +, Peter Maydell wrote: > On 27 February 2017 at 19:41, Jose Ricardo Ziviani > wrote: > > Signed-off-by: Jose Ricardo Ziviani > > --- > > risu_reginfo_ppc64le.c | 8 > > 1 file changed, 8

Re: [Qemu-devel] [PATCH Risu v2 7/9] Add PPC64 in risu build system

On Sat, Feb 18, 2017 at 10:41:41PM +, Peter Maydell wrote: > On 6 November 2016 at 17:15, Jose Ricardo Ziviani > wrote: > > Recognizes PPC64 as a valid architecture and setup the environment > > variables to compile code for that. > > > > Signed-off-by: Jose Ricardo

Re: [Qemu-devel] [PATCH] linux-user: fill target sigcontext struct accordingly

Up On Wed, Feb 01, 2017 at 09:43:57PM +0100, Laurent Vivier wrote: > Le 31/01/2017 à 23:05, Jose Ricardo Ziviani a écrit : > > A segfault is noticed when an emulated program uses any of ucontext > > regs fields. Risu detected this issue in the following operation when > > handling a signal: > >

Re: [Qemu-devel] [Qemu-ppc] [PATCH 0/4] POWER9 TCG enablements - part 13

On Fri, Feb 03, 2017 at 02:11:31PM -0800, no-re...@patchew.org wrote: > Hi, > > Your series seems to have some coding style problems. See output below for > more information: > > Type: series > Subject: [Qemu-devel] [PATCH 0/4] POWER9 TCG enablements - part 13 > Message-id:

Re: [Qemu-devel] [PATCH Risu 1/2] risu_ppc64: Fix Risu to run under qemu linux user

On Mon, Jan 30, 2017 at 11:49:34AM +, Peter Maydell wrote: > On 30 January 2017 at 02:47, Jose Ricardo Ziviani > wrote: > > Qemu linux-user doesn't fill uc_mcontext completely like full emul. does. > > For instance, uc->uc_mcontext.regs->nip is an invalid so this >

Re: [Qemu-devel] [Bug 1655708] [NEW] target/ppc/int_helper.c:2806: strange expression ?

On Wed, Jan 11, 2017 at 05:12:38PM -, Eric Blake wrote: > On 01/11/2017 10:41 AM, dcb wrote: > > Public bug reported: > > > > target/ppc/int_helper.c:2806:25: warning: ‘*’ in boolean context, > > suggest ‘&&’ instead [-Wint-in-bool-context] > > > > Source code is > > > >zone_digit =

Re: [Qemu-devel] [Qemu-ppc] [PATCH v4 1/6] target-ppc: Implement unsigned quadword left/right shift and unit tests

Hello Eric, Thank you very much for your review. Please, read my responses and questions below. Happy 2017. On Tue, Jan 03, 2017 at 09:20:37AM -0600, Eric Blake wrote: > On 12/19/2016 10:47 AM, Jose Ricardo Ziviani wrote: > > This commit implements functions to right and left shifts and the > >

Re: [Qemu-devel] [Qemu-ppc] [PATCH v4 1/6] target-ppc: Implement unsigned quadword left/right shift and unit tests

On Tue, Jan 03, 2017 at 10:53:33AM +1100, David Gibson wrote: > On Mon, Dec 19, 2016 at 02:47:39PM -0200, Jose Ricardo Ziviani wrote: > > This commit implements functions to right and left shifts and the > > unittest for them. Such functions is needed due to instructions > > that requires them. >

Re: [Qemu-devel] [RISU PATCH v3 00/10] Record/payback patches

On Fri, Dec 09, 2016 at 11:48:20AM +, Alex Bennée wrote: > Hi, > > I did a bunch of tweaking to see if I could abstract the hackage for > record/replay a bit more. With a little bit of light re-factoring of > the send and recv functions I can move all the specific send/recv > logic into the

Re: [Qemu-devel] [Qemu-ppc] [PATCH v3 5/6] target-ppc: Implement bcdtrunc. instruction

On Fri, Dec 09, 2016 at 08:06:14AM +1100, David Gibson wrote: > On Thu, Dec 08, 2016 at 12:07:07AM -0200, Jose Ricardo Ziviani wrote: > > bcdtrunc.: Decimal integer truncate. Given a BCD number in vrb and the > > number of bytes to truncate in vra, the return register will have vrb > > with such

Re: [Qemu-devel] [Qemu-ppc] [PATCH v2 2/7] target-ppc: Implement unsigned quadword left/right shift and unit tests

On Wed, Dec 07, 2016 at 04:41:53PM +1100, David Gibson wrote: > On Tue, Dec 06, 2016 at 05:40:05PM -0200, Jose Ricardo Ziviani wrote: > > This commit implements functions to right and left shifts and the > > unittest for them. Such functions is needed due to instructions > > that requires them. >

Re: [Qemu-devel] [Qemu-ppc] [PATCH 5/7] target-ppc: Implement bcdsr. instruction

On Mon, Dec 05, 2016 at 02:19:26PM +1100, David Gibson wrote: > On Sat, Dec 03, 2016 at 03:00:04AM -0200, Jose Ricardo Ziviani wrote: > > bcdsr.: Decimal shift and round. This instruction works like bcds. > > however, when performing right shift, 1 will be added to the > > result if the last digit

Re: [Qemu-devel] [RISU PATCH 0/9] Record/playback patches

On Fri, Dec 02, 2016 at 03:59:26PM +, Alex Bennée wrote: > Hi Peter, > > I've been cleaning things up so I thought I should re-post my current > state. These all apply to the current master. > > I had to regenerate all the risu binaries as I'd used --no-fp for a > bunch of them originally

Re: [Qemu-devel] [Qemu-ppc] [PATCH 2/7] target-ppc: Implement unsigned quadword left/right shift and unit tests

On Mon, Dec 05, 2016 at 12:56:39PM +1100, David Gibson wrote: > On Sat, Dec 03, 2016 at 05:37:27PM -0800, Richard Henderson wrote: > > On 12/02/2016 09:00 PM, Jose Ricardo Ziviani wrote: > > > +++ b/include/qemu/host-utils.h > > > @@ -29,6 +29,33 @@ > > > #include "qemu/bswap.h" > > > > > >

Re: [Qemu-devel] [Qemu-ppc] [PATCH v2 0/4] POWER9 TCG enablements - BCD functions part II

David, Thank you again for reviewing my code, I'm making the changes. I only have a question about patch 1/4 which I didn't find the issue so I'm waiting for Richard's answer. Thanks! On Thu, Nov 24, 2016 at 12:28:32PM +1100, David Gibson wrote: > On Wed, Nov 23, 2016 at 02:21:41PM -0200,

Re: [Qemu-devel] [Qemu-ppc] [PATCH v2 1/4] target-ppc: Implement bcdcfsq. instruction

Hello Richard, Thank you for your review, please read my answer below. On Thu, Nov 24, 2016 at 01:43:18AM +0100, Richard Henderson wrote: > On 11/23/2016 05:21 PM, Jose Ricardo Ziviani wrote: > >bcdcfsq.: Decimal convert from signed quadword. It is not possible > >to convert values less than

Re: [Qemu-devel] [Bug 1643537] [NEW] target-ppc/int_helper.c: 2 * bad array index

On Mon, Nov 21, 2016 at 02:23:25PM +0100, Thomas Huth wrote: > On 21.11.2016 13:16, dcb wrote: > > Public bug reported: > > > > 1. > > > > [qemu/target-ppc/int_helper.c:2575]: (error) Array 'reg.u16[8]' accessed > > at index 8, which is out of bounds. > > > > Source code is > > > >return

Re: [Qemu-devel] [Qemu-ppc] Testing PowerPC floating point instructions

On Thu, Nov 17, 2016 at 10:57:41AM -0500, G 3 wrote: > Is there an official way to test any of the PowerPC floating point > instructions in QEMU? > Hello! it's not an "official way" but I've been working on Risu tool for PPC64le (https://wiki.linaro.org/PeterMaydell/Risu). I think the hardest

Re: [Qemu-devel] [PATCH 1/4] target-ppc: Implement bcdcfsq. instruction

Hello David, Thank you for your review. I have just one question below, could you help me to address it please? Thank you! Ziviani On Thu, Nov 17, 2016 at 02:42:43PM +1100, David Gibson wrote: > On Wed, Nov 16, 2016 at 06:07:27PM -0200, Jose Ricardo Ziviani wrote: > > bcdcfsq.: Decimal convert

Re: [Qemu-devel] [PATCH Risu v2 0/9] Risu support for PPC64LE

On Mon, Nov 07, 2016 at 04:43:38PM +, Peter Maydell wrote: > On 6 November 2016 at 17:15, Jose Ricardo Ziviani > wrote: > > v2: > > - smaller commits > > - improved registers comparison > > - improved code style > > - fixed copyright lines > > > > TODOs: > > -

Re: [Qemu-devel] [PATCH Risu 0/3] Risu support for PPC64LE

On Mon, Oct 31, 2016 at 02:45:24PM +, Peter Maydell wrote: > On 28 October 2016 at 18:46, Jose Ricardo Ziviani > wrote: > > From: Jose Ricardo Ziviani > > > > This is an initial effort to have RISU working for PPC64LE. > > > > I also made some

Re: [Qemu-devel] [PATCH v2 0/4] POWER9 TCG enablements - BCD functions part I

On Mon, Oct 31, 2016 at 01:37:35PM +1100, David Gibson wrote: > On Fri, Oct 28, 2016 at 03:18:00PM -0200, Jose Ricardo Ziviani wrote: > > v2: > > - implements all fixes and suggestions > > Ok, I think the implementations are correct now, but there is still > some polish necessary - comments on

Re: [Qemu-devel] [Qemu-ppc] [PATCH] 4/4] target-ppc: Implement bcdctz. instruction

On Thu, Oct 27, 2016 at 12:47:34PM +1100, David Gibson wrote: > On Wed, Oct 26, 2016 at 11:18:58AM -0200, Jose Ricardo Ziviani wrote: > > bcdctz. converts from BCD to Zoned numeric format. Zoned format uses > > a byte to represent a digit where the most significant nibble is 0x3 > > or 0xf,

Re: [Qemu-devel] [PATCH] 4/4] target-ppc: Implement bcdctz. instruction

Everything will be fixed in v2. Thanks for reviewing it! On Thu, Oct 27, 2016 at 12:47:34PM +1100, David Gibson wrote: > On Wed, Oct 26, 2016 at 11:18:58AM -0200, Jose Ricardo Ziviani wrote: > > bcdctz. converts from BCD to Zoned numeric format. Zoned format uses > > a byte to represent a digit

Re: [Qemu-devel] [PATCH] 3/4] target-ppc: Implement bcdcfz. instruction

I'll send an improved version in v2. Thank you for reviewing it. On Thu, Oct 27, 2016 at 12:35:19PM +1100, David Gibson wrote: > On Wed, Oct 26, 2016 at 11:18:57AM -0200, Jose Ricardo Ziviani wrote: > > bcdcfz. converts from Zoned numeric format to BCD. Zoned format uses > > a byte to represent

Re: [Qemu-devel] [PATCH] 2/4] target-ppc: Implement bcdctn. instruction

On Thu, Oct 27, 2016 at 12:20:17PM +1100, David Gibson wrote: > On Wed, Oct 26, 2016 at 11:18:56AM -0200, Jose Ricardo Ziviani wrote: > > bcdctn. converts from BCD to National numeric format. National format > > uses a byte to represent a digit where the most significant nibble is > > always 0x3

Re: [Qemu-devel] [PATCH] 1/4] target-ppc: Implement bcdcfn. instruction

Hello David, Thank you very much for your review. As you might have noticed this is my first patch so I hope you don't mind about my newbie questions/explanations below. On Thu, Oct 27, 2016 at 12:05:30PM +1100, David Gibson wrote: > On Wed, Oct 26, 2016 at 11:18:55AM -0200, Jose Ricardo