Re: [PULL 00/47] tcg patch queue

2023-10-04 Thread Richard Henderson 

On 10/4/23 09:46, Stefan Hajnoczi wrote:

On Wed, 4 Oct 2023 at 12:28, Richard Henderson
 wrote:


On 10/4/23 07:57, Stefan Hajnoczi wrote:

This commit breaks the build:

../bsd-user/signal.c:479:19: error: unused variable 'env'
[-Werror,-Wunused-variable]
CPUArchState *env = cpu_env(cpu);
^

https://gitlab.com/qemu-project/qemu/-/jobs/5222693462

Please resend the pull request with a fix.


The line number quoted above does not correspond to my source.
Did you attempt to merge multiple pulls simultaneously?
There must be a conflict between them.

My guess is Warner's bsd-user PR.
Please just apply that first and I'll re-roll mine afterward.


Okay. Note that host_signal_handler()'s env local variable looks
unused in your tag:
https://gitlab.com/rth7680/qemu/-/blob/pull-tcg-20231003/bsd-user/signal.c?ref_type=tags#L473


You're right, it does appear to be unused.
And yet "make vm-build-freebsd" succeeds, as does a native build on a freebsd 
install.


r~

Re: [PULL 00/47] tcg patch queue

2023-10-04 Thread Stefan Hajnoczi 
On Wed, 4 Oct 2023 at 12:28, Richard Henderson
 wrote:
>
> On 10/4/23 07:57, Stefan Hajnoczi wrote:
> > This commit breaks the build:
> >
> > ../bsd-user/signal.c:479:19: error: unused variable 'env'
> > [-Werror,-Wunused-variable]
> > CPUArchState *env = cpu_env(cpu);
> > ^
> >
> > https://gitlab.com/qemu-project/qemu/-/jobs/5222693462
> >
> > Please resend the pull request with a fix.
>
> The line number quoted above does not correspond to my source.
> Did you attempt to merge multiple pulls simultaneously?
> There must be a conflict between them.
>
> My guess is Warner's bsd-user PR.
> Please just apply that first and I'll re-roll mine afterward.

Okay. Note that host_signal_handler()'s env local variable looks
unused in your tag:
https://gitlab.com/rth7680/qemu/-/blob/pull-tcg-20231003/bsd-user/signal.c?ref_type=tags#L473

Re: [PULL 00/47] tcg patch queue

2023-10-04 Thread Richard Henderson 

On 10/4/23 07:57, Stefan Hajnoczi wrote:

This commit breaks the build:

../bsd-user/signal.c:479:19: error: unused variable 'env'
[-Werror,-Wunused-variable]
CPUArchState *env = cpu_env(cpu);
^

https://gitlab.com/qemu-project/qemu/-/jobs/5222693462

Please resend the pull request with a fix.


The line number quoted above does not correspond to my source.
Did you attempt to merge multiple pulls simultaneously?
There must be a conflict between them.

My guess is Warner's bsd-user PR.
Please just apply that first and I'll re-roll mine afterward.


r~

Re: [PULL 00/47] tcg patch queue

2023-10-04 Thread Stefan Hajnoczi 
On Tue, 3 Oct 2023 at 13:31, Richard Henderson
 wrote:
>
> The following changes since commit da1034094d375afe9e3d8ec8980550ea0f06f7e0:
>
>   Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging 
> (2023-10-03 07:43:44 -0400)
>
> are available in the Git repository at:
>
>   https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20231003
>
> for you to fetch changes up to 971537eca2e6c7aaf185bbf10d4cbd84cf9d8a38:
>
>   tcg/loongarch64: Fix buid error (2023-10-03 08:53:17 -0700)
>
> 
> accel: Introduce AccelClass::cpu_common_[un]realize
> accel: Target agnostic code movement
> accel/tcg: Cleanups to use CPUState instead of CPUArchState
> accel/tcg: Move CPUNegativeOffsetState into CPUState
> tcg: Split out tcg init functions to tcg/startup.h
> linux-user/hppa: Fix struct target_sigcontext layout
> build: Remove --enable-gprof
>
> 
> Anton Johansson (9):
>   target/arm: Replace TARGET_PAGE_ENTRY_EXTRA
>   accel/tcg: Modify tlb_*() to use CPUState
>   accel/tcg: Modify probe_access_internal() to use CPUState
>   accel/tcg: Modify memory access functions to use CPUState
>   accel/tcg: Modify atomic_mmu_lookup() to use CPUState
>   accel/tcg: Use CPUState in atomicity helpers
>   accel/tcg: Remove env_tlb()
>   accel/tcg: Unify user and softmmu do_[st|ld]*_mmu()
>   accel/tcg: move ld/st helpers to ldst_common.c.inc
>
> Philippe Mathieu-Daudé (19):
>   accel: Rename accel_cpu_realizefn() -> accel_cpu_realize()
>   accel: Rename AccelCPUClass::cpu_realizefn() -> cpu_target_realize()
>   accel: Rename accel_cpu_realize() -> accel_cpu_common_realize()
>   accel: Introduce accel_cpu_common_unrealize() stub
>   accel: Declare AccelClass::cpu_common_[un]realize() handlers
>   accel/tcg: Have tcg_exec_realizefn() return a boolean
>   accel/tcg: Restrict tcg_exec_[un]realizefn() to TCG
>   exec: Make EXCP_FOO definitions target agnostic
>   exec: Move cpu_loop_foo() target agnostic functions to 'cpu-common.h'
>   accel/tcg: Restrict dump_exec_info() declaration
>   accel: Make accel-blocker.o target agnostic
>   accel: Rename accel-common.c -> accel-target.c
>   exec: Rename cpu.c -> cpu-target.c
>   exec: Rename target specific page-vary.c -> page-vary-target.c
>   accel/tcg: Rename target-specific 'internal.h' -> 'internal-target.h'
>   accel/tcg: Make monitor.c a target-agnostic unit
>   accel/tcg: Make icount.o a target agnostic unit
>   accel/tcg: Make cpu-exec-common.c a target agnostic unit
>   tests/avocado: Re-enable MIPS Malta tests (GitLab issue #1884 fixed)
>
> Richard Henderson (18):
>   accel/tcg: Move CPUTLB definitions from cpu-defs.h
>   qom: Propagate alignment through type system
>   target/arm: Remove size and alignment for cpu subclasses
>   target/*: Add instance_align to all cpu base classes
>   accel/tcg: Validate placement of CPUNegativeOffsetState
>   accel/tcg: Move CPUNegativeOffsetState into CPUState
>   accel/tcg: Remove CPUState.icount_decr_ptr
>   accel/tcg: Move can_do_io to CPUNegativeOffsetState
>   accel/tcg: Remove cpu_neg()
>   tcg: Rename cpu_env to tcg_env
>   accel/tcg: Replace CPUState.env_ptr with cpu_env()

This commit breaks the build:

../bsd-user/signal.c:479:19: error: unused variable 'env'
[-Werror,-Wunused-variable]
CPUArchState *env = cpu_env(cpu);
^

https://gitlab.com/qemu-project/qemu/-/jobs/5222693462

Please resend the pull request with a fix.

Thanks,
Stefan

>   accel/tcg: Remove cpu_set_cpustate_pointers
>   accel/tcg: Remove env_neg()
>   tcg: Remove TCGContext.tlb_fast_offset
>   tcg: Remove argument to tcg_prologue_init
>   tcg: Split out tcg init functions to tcg/startup.h
>   linux-user/hppa: Fix struct target_sigcontext layout
>   build: Remove --enable-gprof
>
> gaosong (1):
>   tcg/loongarch64: Fix buid error
>
>  MAINTAINERS|7 +-
>  docs/about/deprecated.rst  |   14 -
>  meson.build|   18 +-
>  accel/tcg/atomic_template.h|   20 +-
>  accel/tcg/internal-common.h|   28 +
>  accel/tcg/{internal.h => internal-target.h}|   21 +-
>  bsd-user/bsd-proc.h|3 -
>  include/exec/cpu-all.h |   67 +-
>  include/exec/cpu-common.h  |   39 +
>  include/exec/cpu-defs.h|  138 ---
>  include/exec/cpu_ldst.h|8 +-
>  include/exec/exec-all.h|   32 +-
>  include/hw/core/accel-cpu.h|2 +-
>  include/hw/core/cpu.h  |  171 ++-
>  include/qemu/accel.h

[PULL 00/47] tcg patch queue

2023-10-03 Thread Richard Henderson 
The following changes since commit da1034094d375afe9e3d8ec8980550ea0f06f7e0:

  Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging 
(2023-10-03 07:43:44 -0400)

are available in the Git repository at:

  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20231003

for you to fetch changes up to 971537eca2e6c7aaf185bbf10d4cbd84cf9d8a38:

  tcg/loongarch64: Fix buid error (2023-10-03 08:53:17 -0700)


accel: Introduce AccelClass::cpu_common_[un]realize
accel: Target agnostic code movement
accel/tcg: Cleanups to use CPUState instead of CPUArchState
accel/tcg: Move CPUNegativeOffsetState into CPUState
tcg: Split out tcg init functions to tcg/startup.h
linux-user/hppa: Fix struct target_sigcontext layout
build: Remove --enable-gprof


Anton Johansson (9):
  target/arm: Replace TARGET_PAGE_ENTRY_EXTRA
  accel/tcg: Modify tlb_*() to use CPUState
  accel/tcg: Modify probe_access_internal() to use CPUState
  accel/tcg: Modify memory access functions to use CPUState
  accel/tcg: Modify atomic_mmu_lookup() to use CPUState
  accel/tcg: Use CPUState in atomicity helpers
  accel/tcg: Remove env_tlb()
  accel/tcg: Unify user and softmmu do_[st|ld]*_mmu()
  accel/tcg: move ld/st helpers to ldst_common.c.inc

Philippe Mathieu-Daudé (19):
  accel: Rename accel_cpu_realizefn() -> accel_cpu_realize()
  accel: Rename AccelCPUClass::cpu_realizefn() -> cpu_target_realize()
  accel: Rename accel_cpu_realize() -> accel_cpu_common_realize()
  accel: Introduce accel_cpu_common_unrealize() stub
  accel: Declare AccelClass::cpu_common_[un]realize() handlers
  accel/tcg: Have tcg_exec_realizefn() return a boolean
  accel/tcg: Restrict tcg_exec_[un]realizefn() to TCG
  exec: Make EXCP_FOO definitions target agnostic
  exec: Move cpu_loop_foo() target agnostic functions to 'cpu-common.h'
  accel/tcg: Restrict dump_exec_info() declaration
  accel: Make accel-blocker.o target agnostic
  accel: Rename accel-common.c -> accel-target.c
  exec: Rename cpu.c -> cpu-target.c
  exec: Rename target specific page-vary.c -> page-vary-target.c
  accel/tcg: Rename target-specific 'internal.h' -> 'internal-target.h'
  accel/tcg: Make monitor.c a target-agnostic unit
  accel/tcg: Make icount.o a target agnostic unit
  accel/tcg: Make cpu-exec-common.c a target agnostic unit
  tests/avocado: Re-enable MIPS Malta tests (GitLab issue #1884 fixed)

Richard Henderson (18):
  accel/tcg: Move CPUTLB definitions from cpu-defs.h
  qom: Propagate alignment through type system
  target/arm: Remove size and alignment for cpu subclasses
  target/*: Add instance_align to all cpu base classes
  accel/tcg: Validate placement of CPUNegativeOffsetState
  accel/tcg: Move CPUNegativeOffsetState into CPUState
  accel/tcg: Remove CPUState.icount_decr_ptr
  accel/tcg: Move can_do_io to CPUNegativeOffsetState
  accel/tcg: Remove cpu_neg()
  tcg: Rename cpu_env to tcg_env
  accel/tcg: Replace CPUState.env_ptr with cpu_env()
  accel/tcg: Remove cpu_set_cpustate_pointers
  accel/tcg: Remove env_neg()
  tcg: Remove TCGContext.tlb_fast_offset
  tcg: Remove argument to tcg_prologue_init
  tcg: Split out tcg init functions to tcg/startup.h
  linux-user/hppa: Fix struct target_sigcontext layout
  build: Remove --enable-gprof

gaosong (1):
  tcg/loongarch64: Fix buid error

 MAINTAINERS|7 +-
 docs/about/deprecated.rst  |   14 -
 meson.build|   18 +-
 accel/tcg/atomic_template.h|   20 +-
 accel/tcg/internal-common.h|   28 +
 accel/tcg/{internal.h => internal-target.h}|   21 +-
 bsd-user/bsd-proc.h|3 -
 include/exec/cpu-all.h |   67 +-
 include/exec/cpu-common.h  |   39 +
 include/exec/cpu-defs.h|  138 ---
 include/exec/cpu_ldst.h|8 +-
 include/exec/exec-all.h|   32 +-
 include/hw/core/accel-cpu.h|2 +-
 include/hw/core/cpu.h  |  171 ++-
 include/qemu/accel.h   |   12 +-
 include/tcg/startup.h  |   58 +
 include/tcg/tcg.h  |6 +-
 target/alpha/cpu.h |1 -
 target/arm/common-semi-target.h|2 +-
 target/arm/cpu-param.h |   12 -
 target/arm/cpu.h   |1 -
 target/arm/tcg/translate-a32.h |2 +-
 target/arm/tcg/translate-a64.h

Re: [PULL 00/47] tcg patch queue

2023-01-05 Thread Peter Maydell 
On Fri, 30 Dec 2022 at 00:21, Richard Henderson
 wrote:
>
> The following changes since commit 222059a0fccf4af3be776fe35a5ea2d6a68f9a0b:
>
>   Merge tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu into 
> staging (2022-12-21 18:08:09 +)
>
> are available in the Git repository at:
>
>   https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20221229
>
> for you to fetch changes up to b05e35533782a71a9fda472afd08442f50622a3e:
>
>   tests/tcg/multiarch: add vma-pthread.c (2022-12-29 12:39:45 -0800)
>
> 
> Fix race conditions in new user-only vma tracking.
> Add tcg backend paired register allocation.
> Cleanup tcg backend function call abi.
>
> 

This seems to consistently fail on the sparc64 boot-serial-test and
prom-env-test qtests on the cross-i386-system job:
https://gitlab.com/qemu-project/qemu/-/jobs/3556359194
https://gitlab.com/qemu-project/qemu/-/jobs/3558798430

A couple of the sparc avocado tests also now timeout and fail
with the INTERRUPTED state:
https://gitlab.com/qemu-project/qemu/-/jobs/3556359335
https://gitlab.com/qemu-project/qemu/-/jobs/3558798558

So it looks like there's a problem for sparc guests here somewhere.

thanks
-- PMM

[PULL 00/47] tcg patch queue

2022-12-29 Thread Richard Henderson 
The following changes since commit 222059a0fccf4af3be776fe35a5ea2d6a68f9a0b:

  Merge tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu into 
staging (2022-12-21 18:08:09 +)

are available in the Git repository at:

  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20221229

for you to fetch changes up to b05e35533782a71a9fda472afd08442f50622a3e:

  tests/tcg/multiarch: add vma-pthread.c (2022-12-29 12:39:45 -0800)


Fix race conditions in new user-only vma tracking.
Add tcg backend paired register allocation.
Cleanup tcg backend function call abi.


Ilya Leoshkevich (1):
  tests/tcg/multiarch: add vma-pthread.c

Mark Cave-Ayland (1):
  tcg: convert tcg/README to rst

Philippe Mathieu-Daudé (5):
  tcg/s390x: Fix coding style
  tcg: Massage process_op_defs()
  tcg: Pass number of arguments to tcg_emit_op() / tcg_op_insert_*()
  tcg: Convert typecode_to_ffi from array to function
  tcg: Factor init_ffi_layouts() out of tcg_context_init()

Richard Henderson (40):
  meson: Move CONFIG_TCG_INTERPRETER to config_host
  tcg: Cleanup trailing whitespace
  qemu/main-loop: Introduce QEMU_IOTHREAD_LOCK_GUARD
  hw/mips: Use QEMU_IOTHREAD_LOCK_GUARD in cpu_mips_irq_request
  target/ppc: Use QEMU_IOTHREAD_LOCK_GUARD in ppc_maybe_interrupt
  target/ppc: Use QEMU_IOTHREAD_LOCK_GUARD in cpu_interrupt_exittb
  target/riscv: Use QEMU_IOTHREAD_LOCK_GUARD in riscv_cpu_update_mip
  hw/ppc: Use QEMU_IOTHREAD_LOCK_GUARD in ppc_set_irq
  accel/tcg: Use QEMU_IOTHREAD_LOCK_GUARD in io_readx/io_writex
  tcg: Tidy tcg_reg_alloc_op
  tcg: Remove TCG_TARGET_STACK_GROWSUP
  tci: MAX_OPC_PARAM_IARGS is no longer used
  tcg: Fix tcg_reg_alloc_dup*
  tcg: Centralize updates to reg_to_temp
  tcg: Remove check_regs
  tcg: Introduce paired register allocation
  accel/tcg: Set cflags_next_tb in cpu_common_initfn
  target/sparc: Avoid TCGV_{LOW,HIGH}
  tcg: Move TCG_{LOW,HIGH} to tcg-internal.h
  tcg: Add temp_subindex to TCGTemp
  tcg: Simplify calls to temp_sync vs mem_coherent
  tcg: Allocate TCGTemp pairs in host memory order
  tcg: Move TCG_TYPE_COUNT outside enum
  tcg: Introduce tcg_type_size
  tcg: Introduce TCGCallReturnKind and TCGCallArgumentKind
  tcg: Replace TCG_TARGET_CALL_ALIGN_ARGS with TCG_TARGET_CALL_ARG_I64
  tcg: Replace TCG_TARGET_EXTEND_ARGS with TCG_TARGET_CALL_ARG_I32
  tcg: Use TCG_CALL_ARG_EVEN for TCI special case
  accel/tcg/plugin: Don't search for the function pointer index
  accel/tcg/plugin: Avoid duplicate copy in copy_call
  accel/tcg/plugin: Use copy_op in append_{udata,mem}_cb
  tcg: Vary the allocation size for TCGOp
  tcg: Use output_pref wrapper function
  tcg: Reorg function calls
  tcg: Move ffi_cif pointer into TCGHelperInfo
  tcg/aarch64: Merge tcg_out_callr into tcg_out_call
  tcg: Add TCGHelperInfo argument to tcg_out_call
  accel/tcg: Fix tb_invalidate_phys_page_unwind
  accel/tcg: Use g_free_rcu for user-exec interval trees
  accel/tcg: Handle false negative lookup in page_check_range

 docs/devel/atomics.rst   |2 +
 docs/devel/index-tcg.rst |1 +
 docs/devel/tcg-ops.rst   |  941 +++
 docs/devel/tcg.rst   |2 +-
 meson.build  |4 +-
 include/exec/helper-head.h   |2 +-
 include/qemu/main-loop.h |   29 +
 include/tcg/tcg-op.h |   35 +-
 include/tcg/tcg.h|   96 +-
 tcg/aarch64/tcg-target.h |4 +-
 tcg/arm/tcg-target.h |4 +-
 tcg/i386/tcg-target.h|2 +
 tcg/loongarch64/tcg-target.h |3 +-
 tcg/mips/tcg-target.h|4 +-
 tcg/riscv/tcg-target.h   |7 +-
 tcg/s390x/tcg-target.h   |3 +-
 tcg/sparc64/tcg-target.h |3 +-
 tcg/tcg-internal.h   |   58 +-
 tcg/tci/tcg-target.h |7 +
 tests/tcg/multiarch/nop_func.h   |   25 +
 accel/tcg/cputlb.c   |   25 +-
 accel/tcg/plugin-gen.c   |   54 +-
 accel/tcg/tb-maint.c |   78 +-
 accel/tcg/user-exec.c|   59 +-
 hw/core/cpu-common.c |1 +
 hw/mips/mips_int.c   |   11 +-
 hw/ppc/ppc.c |   10 +-
 target/ppc/excp_helper.c |   11 +-
 target/ppc/helper_regs.c |   14 +-
 target/riscv/cpu_helper.c|   10 +-
 target/sparc/translate.c |   21 +-
 tcg/optimize.c   |   10 +-
 tcg/tcg-op-vec.c |   10 +-
 tcg/tcg-op.c |   49 +-
 tcg/tcg.c| 1658

Re: [PULL 00/47] tcg patch queue

2022-10-26 Thread Stefan Hajnoczi 
Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any 
user-visible changes.


signature.asc
Description: PGP signature

[PULL 00/47] tcg patch queue

2022-10-25 Thread Richard Henderson 
The following changes since commit e750a7ace492f0b450653d4ad368a77d6f660fb8:

  Merge tag 'pull-9p-20221024' of https://github.com/cschoenebeck/qemu into 
staging (2022-10-24 14:27:12 -0400)

are available in the Git repository at:

  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20221026

for you to fetch changes up to 04f105758b0089f73ee47260671580cde35f96cc:

  accel/tcg: Remove restore_state_to_opc function (2022-10-26 11:11:28 +1000)


Revert incorrect cflags initialization.
Add direct jumps for tcg/loongarch64.
Speed up breakpoint check.
Improve assertions for atomic.h.
Move restore_state_to_opc to TCGCPUOps.
Cleanups to TranslationBlock maintenance.


Leandro Lupori (1):
  accel/tcg: Add a quicker check for breakpoints

Peter Maydell (1):
  Revert "accel/tcg: Init TCG cflags in vCPU thread handler"

Qi Hu (2):
  tcg/loongarch64: Add direct jump support
  tcg/aarch64: Remove unused code in tcg_out_op

Richard Henderson (43):
  include/qemu/osdep: Add qemu_build_assert
  include/qemu/atomic: Use qemu_build_assert
  include/qemu/thread: Use qatomic_* functions
  accel/tcg: Make page_alloc_target_data allocation constant
  accel/tcg: Remove disabled debug in translate-all.c
  accel/tcg: Split out PageDesc to internal.h
  accel/tcg: Split out tb-maint.c
  accel/tcg: Move assert_no_pages_locked to internal.h
  accel/tcg: Drop cpu_get_tb_cpu_state from TARGET_HAS_PRECISE_SMC
  accel/tcg: Remove duplicate store to tb->page_addr[]
  accel/tcg: Introduce tb_{set_}page_addr{0,1}
  accel/tcg: Rename tb_invalidate_phys_page
  accel/tcg: Rename tb_invalidate_phys_page_range and drop end parameter
  accel/tcg: Unify declarations of tb_invalidate_phys_range
  accel/tcg: Use tb_invalidate_phys_page in page_set_flags
  accel/tcg: Call tb_invalidate_phys_page for PAGE_RESET
  accel/tcg: Use page_reset_target_data in page_set_flags
  accel/tcg: Use tb_invalidate_phys_range in page_set_flags
  accel/tcg: Move TARGET_PAGE_DATA_SIZE impl to user-exec.c
  accel/tcg: Simplify page_get/alloc_target_data
  accel/tcg: Add restore_state_to_opc to TCGCPUOps
  target/alpha: Convert to tcg_ops restore_state_to_opc
  target/arm: Convert to tcg_ops restore_state_to_opc
  target/avr: Convert to tcg_ops restore_state_to_opc
  target/cris: Convert to tcg_ops restore_state_to_opc
  target/hexagon: Convert to tcg_ops restore_state_to_opc
  target/hppa: Convert to tcg_ops restore_state_to_opc
  target/i386: Convert to tcg_ops restore_state_to_opc
  target/loongarch: Convert to tcg_ops restore_state_to_opc
  target/m68k: Convert to tcg_ops restore_state_to_opc
  target/microblaze: Convert to tcg_ops restore_state_to_opc
  target/mips: Convert to tcg_ops restore_state_to_opc
  target/nios2: Convert to tcg_ops restore_state_to_opc
  target/openrisc: Convert to tcg_ops restore_state_to_opc
  target/ppc: Convert to tcg_ops restore_state_to_opc
  target/riscv: Convert to tcg_ops restore_state_to_opc
  target/rx: Convert to tcg_ops restore_state_to_opc
  target/s390x: Convert to tcg_ops restore_state_to_opc
  target/sh4: Convert to tcg_ops restore_state_to_opc
  target/sparc: Convert to tcg_ops restore_state_to_opc
  target/tricore: Convert to tcg_ops restore_state_to_opc
  target/xtensa: Convert to tcg_ops restore_state_to_opc
  accel/tcg: Remove restore_state_to_opc function

 accel/tcg/internal.h |   91 
 include/exec/cpu-all.h   |   22 +-
 include/exec/exec-all.h  |   35 +-
 include/exec/ram_addr.h  |2 -
 include/exec/translate-all.h |2 +-
 include/hw/core/tcg-cpu-ops.h|   11 +
 include/qemu/atomic.h|   16 +-
 include/qemu/osdep.h |8 +
 include/qemu/thread.h|8 +-
 target/arm/cpu.h |8 +
 target/arm/internals.h   |4 -
 target/mips/tcg/tcg-internal.h   |3 +
 target/s390x/s390x-internal.h|4 +-
 target/sparc/cpu.h   |3 +
 tcg/loongarch64/tcg-target.h |9 +-
 accel/tcg/cpu-exec.c |   24 +-
 accel/tcg/tb-maint.c |  704 ++
 accel/tcg/tcg-accel-ops-mttcg.c  |5 +-
 accel/tcg/tcg-accel-ops-rr.c |7 +-
 accel/tcg/translate-all.c| 1017 ++
 accel/tcg/translator.c   |9 +-
 accel/tcg/user-exec.c|   42 ++
 bsd-user/mmap.c  |2 -
 cpu.c|4 +-
 linux-user/mmap.c|4 -
 target/alpha/cpu.c   |9 +
 target/alpha/translate.c |6 -
 target/arm/cpu.c |   26 +
 target/arm/mte_helper.c  |5 -
 target/arm/translate.c   |   22 -

Re: [PULL 00/47] tcg patch queue

2021-01-08 Thread Peter Maydell 
On Thu, 7 Jan 2021 at 20:14, Richard Henderson
 wrote:
>
> The following changes since commit 470dd6bd360782f5137f7e3376af6a44658eb1d3:
>
>   Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-060121-4' 
> into staging (2021-01-06 22:18:36 +)
>
> are available in the Git repository at:
>
>   https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210107
>
> for you to fetch changes up to e5e2e4c73926f6f3c1f5da24a350e4345d5ad232:
>
>   tcg: Constify TCGLabelQemuLdst.raddr (2021-01-07 05:09:42 -1000)
>
> 
> Build fix for ppc64 centos7.
> Reduce the use of scratch registers for tcg/i386.
> Use _aligned_malloc for Win32.
> Enable split w^x code gen buffers.
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0
for any user-visible changes.

-- PMM

Re: [PULL 00/47] tcg patch queue

2021-01-07 Thread no-reply 
Patchew URL: 
https://patchew.org/QEMU/20210107201448.1152301-1-richard.hender...@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20210107201448.1152301-1-richard.hender...@linaro.org
Subject: [PULL 00/47] tcg patch queue

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]  patchew/20201217004349.3740927-1-wuhao...@google.com -> 
patchew/20201217004349.3740927-1-wuhao...@google.com
 * [new tag] 
patchew/20210107201448.1152301-1-richard.hender...@linaro.org -> 
patchew/20210107201448.1152301-1-richard.hender...@linaro.org
 * [new tag] patchew/20210107202135.52379-1-da...@redhat.com -> 
patchew/20210107202135.52379-1-da...@redhat.com
Switched to a new branch 'test'
baaf0fe tcg: Constify TCGLabelQemuLdst.raddr
11b7ecd tcg: Constify tcg_code_gen_epilogue
1cbfe80 tcg: Remove TCG_TARGET_SUPPORT_MIRROR
8293de7 tcg/arm: Support split-wx code generation
ee981fc tcg/mips: Support split-wx code generation
cc886de tcg/mips: Do not assert on relocation overflow
7edccfc accel/tcg: Add mips support to alloc_code_gen_buffer_splitwx_memfd
cd1d197 tcg/riscv: Support split-wx code generation
1e9023f tcg/riscv: Remove branch-over-branch fallback
918423b tcg/riscv: Fix branch range checks
9b4c46d tcg/s390: Support split-wx code generation
f4f6bfe tcg/s390: Use tcg_tbrel_diff
eeb5902 tcg/sparc: Support split-wx code generation
0063296 tcg/sparc: Use tcg_tbrel_diff
726a8d5 tcg/ppc: Support split-wx code generation
178b2f8 tcg/ppc: Use tcg_out_mem_long to reset TCG_REG_TB
34eddea tcg/ppc: Use tcg_tbrel_diff
5c598e3 tcg: Introduce tcg_tbrel_diff
49f2bb2 tcg/tci: Push const down through bytecode reading
b7dcd21 disas: Push const down through host disassembly
2f4fa86 tcg/aarch64: Support split-wx code generation
2281570 tcg/aarch64: Use B not BL for tcg_out_goto_long
3eb009f tcg/i386: Support split-wx code generation
ff582bc tcg: Return the TB pointer from the rx region from exit_tb
ff8cda4 accel/tcg: Support split-wx for darwin/iOS with vm_remap
3d11126 accel/tcg: Support split-wx for linux with memfd
3a0321d tcg: Add --accel tcg,split-wx property
7ad4a3c tcg: Use Error with alloc_code_gen_buffer
aa126e3 tcg: Make tb arg to synchronize_from_tb const
0fcb800 tcg: Make DisasContextBase.tb const
3cb9250 tcg: Adjust tb_target_set_jmp_target for split-wx
1aec9d3 tcg: Adjust tcg_register_jit for const
ad05d6b tcg: Adjust tcg_out_label for const
c2c5c8d tcg: Adjust tcg_out_call for const
5ee9e81 tcg: Adjust TCGLabel for const
853af37 tcg: Introduce tcg_splitwx_to_{rx,rw}
fe3436a tcg: Add in_code_gen_buffer
26546a3 tcg: Move tcg epilogue pointer out of TCGContext
ff316eb tcg: Move tcg prologue pointer out of TCGContext
9ad8166 util: Specialize flush_idcache_range for aarch64
b3a9807 util: Enhance flush_icache_range with separate data pointer
09ac14d tcg: Do not flush icache for interpreter
e561da4 util/oslib: Assert qemu_try_memalign() alignment is a power of 2
3ee9998 util/oslib-win32: Use _aligned_malloc for qemu_try_memalign
7acb88f tcg: Introduce INDEX_op_qemu_st8_i32
72e8b56 tcg/i386: Adjust TCG_TARGET_HAS_MEMORY_BSWAP
988e336 linux-user: Conditionalize TUNSETVNETLE

=== OUTPUT BEGIN ===
1/47 Checking commit 988e33623c3a (linux-user: Conditionalize TUNSETVNETLE)
2/47 Checking commit 72e8b5670ce2 (tcg/i386: Adjust TCG_TARGET_HAS_MEMORY_BSWAP)
3/47 Checking commit 7acb88f4c360 (tcg: Introduce INDEX_op_qemu_st8_i32)
4/47 Checking commit 3ee99982f56b (util/oslib-win32: Use _aligned_malloc for 
qemu_try_memalign)
5/47 Checking commit e561da41def8 (util/oslib: Assert qemu_try_memalign() 
alignment is a power of 2)
6/47 Checking commit 09ac14d3ad89 (tcg: Do not flush icache for interpreter)
7/47 Checking commit b3a9807019f1 (util: Enhance flush_icache_range with 
separate data pointer)
8/47 Checking commit 9ad81668d136 (util: Specialize flush_idcache_range for 
aarch64)
ERROR: externs should be avoided in .c files
#38: FILE: util/cacheflush.c:21:
+extern void sys_icache_invalidate(void *start, size_t len);

ERROR: externs should be avoided in .c files
#39: FILE: util/cacheflush.c:22:
+extern void sys_dcache_flush(void *start, size_t len);

total: 2 errors, 0 warnings, 81 lines checked

Patch 8/47 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

9/47 Checking commit ff316eb2ba9b (tcg: Move tcg prologue pointer out of 
TCGContext)
10/47 Checking commit 26546a391bfe (tcg: Move tcg epilogue pointer out of 
TCGContext)
11/47 Checking commit fe3436a9375c (tcg: Add in_code_gen_buffer)
12/47 Checking commit 853af

[PULL 00/47] tcg patch queue

2021-01-07 Thread Richard Henderson 
The following changes since commit 470dd6bd360782f5137f7e3376af6a44658eb1d3:

  Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-060121-4' 
into staging (2021-01-06 22:18:36 +)

are available in the Git repository at:

  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210107

for you to fetch changes up to e5e2e4c73926f6f3c1f5da24a350e4345d5ad232:

  tcg: Constify TCGLabelQemuLdst.raddr (2021-01-07 05:09:42 -1000)


Build fix for ppc64 centos7.
Reduce the use of scratch registers for tcg/i386.
Use _aligned_malloc for Win32.
Enable split w^x code gen buffers.


Philippe Mathieu-Daudé (1):
  util/oslib: Assert qemu_try_memalign() alignment is a power of 2

Richard Henderson (46):
  linux-user: Conditionalize TUNSETVNETLE
  tcg/i386: Adjust TCG_TARGET_HAS_MEMORY_BSWAP
  tcg: Introduce INDEX_op_qemu_st8_i32
  util/oslib-win32: Use _aligned_malloc for qemu_try_memalign
  tcg: Do not flush icache for interpreter
  util: Enhance flush_icache_range with separate data pointer
  util: Specialize flush_idcache_range for aarch64
  tcg: Move tcg prologue pointer out of TCGContext
  tcg: Move tcg epilogue pointer out of TCGContext
  tcg: Add in_code_gen_buffer
  tcg: Introduce tcg_splitwx_to_{rx,rw}
  tcg: Adjust TCGLabel for const
  tcg: Adjust tcg_out_call for const
  tcg: Adjust tcg_out_label for const
  tcg: Adjust tcg_register_jit for const
  tcg: Adjust tb_target_set_jmp_target for split-wx
  tcg: Make DisasContextBase.tb const
  tcg: Make tb arg to synchronize_from_tb const
  tcg: Use Error with alloc_code_gen_buffer
  tcg: Add --accel tcg,split-wx property
  accel/tcg: Support split-wx for linux with memfd
  accel/tcg: Support split-wx for darwin/iOS with vm_remap
  tcg: Return the TB pointer from the rx region from exit_tb
  tcg/i386: Support split-wx code generation
  tcg/aarch64: Use B not BL for tcg_out_goto_long
  tcg/aarch64: Support split-wx code generation
  disas: Push const down through host disassembly
  tcg/tci: Push const down through bytecode reading
  tcg: Introduce tcg_tbrel_diff
  tcg/ppc: Use tcg_tbrel_diff
  tcg/ppc: Use tcg_out_mem_long to reset TCG_REG_TB
  tcg/ppc: Support split-wx code generation
  tcg/sparc: Use tcg_tbrel_diff
  tcg/sparc: Support split-wx code generation
  tcg/s390: Use tcg_tbrel_diff
  tcg/s390: Support split-wx code generation
  tcg/riscv: Fix branch range checks
  tcg/riscv: Remove branch-over-branch fallback
  tcg/riscv: Support split-wx code generation
  accel/tcg: Add mips support to alloc_code_gen_buffer_splitwx_memfd
  tcg/mips: Do not assert on relocation overflow
  tcg/mips: Support split-wx code generation
  tcg/arm: Support split-wx code generation
  tcg: Remove TCG_TARGET_SUPPORT_MIRROR
  tcg: Constify tcg_code_gen_epilogue
  tcg: Constify TCGLabelQemuLdst.raddr

 accel/tcg/tcg-runtime.h  |   2 +-
 include/disas/dis-asm.h  |   4 +-
 include/disas/disas.h|   2 +-
 include/exec/exec-all.h  |   2 +-
 include/exec/gen-icount.h|   4 +-
 include/exec/log.h   |   2 +-
 include/exec/translator.h|   2 +-
 include/hw/core/cpu.h|   3 +-
 include/qemu/cacheflush.h|  15 ++-
 include/sysemu/tcg.h |   3 +-
 include/tcg/tcg-op.h |   2 +-
 include/tcg/tcg-opc.h|   5 +
 include/tcg/tcg.h|  61 +++--
 linux-user/ioctls.h  |   2 +
 tcg/aarch64/tcg-target.h |   3 +-
 tcg/arm/tcg-target.h |   3 +-
 tcg/i386/tcg-target.h|  12 +-
 tcg/mips/tcg-target.h|   3 +-
 tcg/ppc/tcg-target.h |   3 +-
 tcg/riscv/tcg-target.h   |   3 +-
 tcg/s390/tcg-target.h|   9 +-
 tcg/sparc/tcg-target.h   |   3 +-
 tcg/tci/tcg-target.h |   7 +-
 accel/tcg/cpu-exec.c |  41 +++---
 accel/tcg/tcg-all.c  |  26 +++-
 accel/tcg/tcg-runtime.c  |   4 +-
 accel/tcg/translate-all.c| 311 ++-
 accel/tcg/translator.c   |   4 +-
 bsd-user/main.c  |   2 +-
 disas.c  |   2 +-
 disas/capstone.c |   2 +-
 linux-user/main.c|   2 +-
 softmmu/physmem.c|   2 +-
 target/arm/cpu.c |   3 +-
 target/arm/translate-a64.c   |   2 +-
 target/avr/cpu.c |   3 +-
 target/hppa/cpu.c|   3 +-
 target/i386/tcg/tcg-cpu.c|   3 +-
 target/microblaze/cpu.c  |   3 +-
 target/mips/cpu.c|   3 +-
 target/riscv/cpu.c   |   3 +-
 target/rx/cpu.c  |   3 +-
 target/sh4/cpu.c |   3 +-
 target/sparc/cpu.c   |   3 +-
 target/tricore/cpu.c |   2 +-
 tcg/optimize.c   |   1 +
 tcg/tcg-op.c |  21 ++-
 tcg/tcg.c