On 5/19/20 7:41 PM, LIU Zhiwei wrote:
>> Since all of sp, gp, tp are not in risu's control, why is rs1 only excluding
>> sp, and not gp and tp as well?
> When I test the patch set, I find gp and tp will be the same in slave and
> master，
> so they can be used as source register.
Ah, try again
On 2020/5/12 0:39, Richard Henderson wrote:
On 4/30/20 12:21 AM, LIU Zhiwei wrote:
+LUI RISCV imm:20 rd:5 0110111 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
I think it would be helpful to add a function for this. e.g. greg($rd) and
gbase($rs1) (including $0). It would keep the
On 4/30/20 12:21 AM, LIU Zhiwei wrote:
> +LUI RISCV imm:20 rd:5 0110111 \
> +!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
I think it would be helpful to add a function for this. e.g. greg($rd) and
gbase($rs1) (including $0). It would keep the constraints smaller, and avoid
mistakes.
These
Signed-off-by: LIU Zhiwei
---
riscv64.risu | 141 +++
1 file changed, 141 insertions(+)
create mode 100644 riscv64.risu
diff --git a/riscv64.risu b/riscv64.risu
new file mode 100644
index 000..98141ab
--- /dev/null
+++ b/riscv64.risu
@@ -0,0
