On Tue, 18 Apr 2023 at 17:55, Guenter Roeck wrote:
> On 4/18/23 08:32, Peter Maydell wrote:
> > So looking again at that diagram on that website, I think I understand
> > now: for data transfer to/from the outside world, MAC1 talks only through
> > PHY1 and MAC2 only through PHY2 (over the links
On 4/18/23 08:32, Peter Maydell wrote:
On Tue, 18 Apr 2023 at 16:18, Guenter Roeck wrote:
On 4/18/23 07:46, Peter Maydell wrote:
I guess I don't understand what the topology is for these specific
SoCs, then. If there's only one master that might be connected
to multiple PHYs, why does one
On Tue, 18 Apr 2023 at 16:18, Guenter Roeck wrote:
> On 4/18/23 07:46, Peter Maydell wrote:
> > I guess I don't understand what the topology is for these specific
> > SoCs, then. If there's only one master that might be connected
> > to multiple PHYs, why does one ethernet device in QEMU need to
On 4/18/23 07:46, Peter Maydell wrote:
On Tue, 18 Apr 2023 at 15:42, Guenter Roeck wrote:
On 4/18/23 05:10, Peter Maydell wrote:
On Wed, 15 Mar 2023 at 14:52, Guenter Roeck wrote:
So I was having a look at this to see if it was reasonably easy to
split out the PHY into its own device
On Tue, 18 Apr 2023 at 15:42, Guenter Roeck wrote:
>
> On 4/18/23 05:10, Peter Maydell wrote:
> > On Wed, 15 Mar 2023 at 14:52, Guenter Roeck wrote:
> > So I was having a look at this to see if it was reasonably easy to
> > split out the PHY into its own device object, and I'm a bit confused.
>
On 4/18/23 05:10, Peter Maydell wrote:
On Wed, 15 Mar 2023 at 14:52, Guenter Roeck wrote:
The SOC on i.MX6UL and i.MX7 has 2 Ethernet interfaces. The PHY on each may
be connected to separate MDIO busses, or both may be connected on the same
MDIO bus using different PHY addresses. Commit
On Wed, 15 Mar 2023 at 14:52, Guenter Roeck wrote:
>
> The SOC on i.MX6UL and i.MX7 has 2 Ethernet interfaces. The PHY on each may
> be connected to separate MDIO busses, or both may be connected on the same
> MDIO bus using different PHY addresses. Commit 461c51ad4275 ("Add a phy-num
> property
The SOC on i.MX6UL and i.MX7 has 2 Ethernet interfaces. The PHY on each may
be connected to separate MDIO busses, or both may be connected on the same
MDIO bus using different PHY addresses. Commit 461c51ad4275 ("Add a phy-num
property to the i.MX FEC emulator") added support for specifying PHY
