On 16/07/20 10:20, Xiaoyao Li wrote:
> Per Intel SDM vol 1, 13.2, if CPUID.1:ECX.XSAVE[bit 26] is 0, the
> processor provides no further enumeration through CPUID function 0DH.
>
> Signed-off-by: Xiaoyao Li
> ---
> target/i386/cpu.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git
On 7/16/2020 11:15 PM, Eduardo Habkost wrote:
On Thu, Jul 16, 2020 at 04:20:18PM +0800, Xiaoyao Li wrote:
Per Intel SDM vol 1, 13.2, if CPUID.1:ECX.XSAVE[bit 26] is 0, the
processor provides no further enumeration through CPUID function 0DH.
Can you explain what's the bug you are trying to
On Thu, Jul 16, 2020 at 04:20:18PM +0800, Xiaoyao Li wrote:
> Per Intel SDM vol 1, 13.2, if CPUID.1:ECX.XSAVE[bit 26] is 0, the
> processor provides no further enumeration through CPUID function 0DH.
Can you explain what's the bug you are trying to fix?
env->features[FEAT_XSAVE_COMP_*] is already
Per Intel SDM vol 1, 13.2, if CPUID.1:ECX.XSAVE[bit 26] is 0, the
processor provides no further enumeration through CPUID function 0DH.
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
