Re: [PATCH v5] i386/cpu_dump: support AVX512 ZMM regs dump
On Mon, 2021-04-19 at 17:59 -0400, Eduardo Habkost wrote:
> On Mon, Apr 19, 2021 at 04:18:25PM -0400, Eduardo Habkost wrote:
> > On Fri, Apr 16, 2021 at 10:08:24AM +0800, Robert Hoo wrote:
> > > Since commit fa4518741e (target-i386: Rename struct XMMReg to
> > > ZMMReg),
> > > CPUX86State.xmm_regs[] has already been extended to 512bit to
> > > support
> > > AVX512.
> > > Also, other qemu level supports for AVX512 registers are there
> > > for
> > > years.
> > > But in x86_cpu_dump_state(), still only dump XMM registers no
> > > matter
> > > YMM/ZMM is enabled.
> > > This patch is to complement this, let it dump XMM/YMM/ZMM
> > > accordingly.
> > >
> > > Signed-off-by: Robert Hoo
> >
> > Queued for 6.1, thanks!
>
> Dequeuing, as it causes build failures on multiple configs:
>
> https://gitlab.com/ehabkost/qemu/-/pipelines/288890306
>
> Example:
>
>
> ../target/i386/cpu-dump.c: In function 'x86_cpu_dump_state':
> ../target/i386/cpu-dump.c:511:50: error: format '%lx' expects
> argument of type 'long unsigned int', but argument 4 has type
> 'uint64_t' {aka 'long long unsigned int'} [-Werror=format=]
> qemu_fprintf(f, "Opmask%02d=%016lx%s", i, env-
> >opmask_regs[i],
> ~^~~
> ~
> %016llx
> ../target/i386/cpu-dump.c:517:47: error: format '%lx' expects
> argument of type 'long unsigned int', but argument 4 has type
> 'uint64_t' {aka 'long long unsigned int'} [-Werror=format=]
> qemu_fprintf(f, "ZMM%02d=%016lx %016lx %016lx %016lx
> %016lx "
> ~^
> %016llx
>
Hi Eduardo,
I've sent v6
https://patchwork.kernel.org/project/qemu-devel/patch/1618986232-73826-1-git-send-email-robert...@linux.intel.com/
, would you retest and queue it?
Thanks.
>
Re: [PATCH v5] i386/cpu_dump: support AVX512 ZMM regs dump
On Mon, Apr 19, 2021 at 04:18:25PM -0400, Eduardo Habkost wrote:
> On Fri, Apr 16, 2021 at 10:08:24AM +0800, Robert Hoo wrote:
> > Since commit fa4518741e (target-i386: Rename struct XMMReg to ZMMReg),
> > CPUX86State.xmm_regs[] has already been extended to 512bit to support
> > AVX512.
> > Also, other qemu level supports for AVX512 registers are there for
> > years.
> > But in x86_cpu_dump_state(), still only dump XMM registers no matter
> > YMM/ZMM is enabled.
> > This patch is to complement this, let it dump XMM/YMM/ZMM accordingly.
> >
> > Signed-off-by: Robert Hoo
>
> Queued for 6.1, thanks!
Dequeuing, as it causes build failures on multiple configs:
https://gitlab.com/ehabkost/qemu/-/pipelines/288890306
Example:
../target/i386/cpu-dump.c: In function 'x86_cpu_dump_state':
../target/i386/cpu-dump.c:511:50: error: format '%lx' expects argument of type
'long unsigned int', but argument 4 has type 'uint64_t' {aka 'long long
unsigned int'} [-Werror=format=]
qemu_fprintf(f, "Opmask%02d=%016lx%s", i, env->opmask_regs[i],
~^~~~
%016llx
../target/i386/cpu-dump.c:517:47: error: format '%lx' expects argument of type
'long unsigned int', but argument 4 has type 'uint64_t' {aka 'long long
unsigned int'} [-Werror=format=]
qemu_fprintf(f, "ZMM%02d=%016lx %016lx %016lx %016lx %016lx "
~^
%016llx
--
Eduardo
Re: [PATCH v5] i386/cpu_dump: support AVX512 ZMM regs dump
On Fri, Apr 16, 2021 at 10:08:24AM +0800, Robert Hoo wrote: > Since commit fa4518741e (target-i386: Rename struct XMMReg to ZMMReg), > CPUX86State.xmm_regs[] has already been extended to 512bit to support > AVX512. > Also, other qemu level supports for AVX512 registers are there for > years. > But in x86_cpu_dump_state(), still only dump XMM registers no matter > YMM/ZMM is enabled. > This patch is to complement this, let it dump XMM/YMM/ZMM accordingly. > > Signed-off-by: Robert Hoo Queued for 6.1, thanks! -- Eduardo
Re: [PATCH v5] i386/cpu_dump: support AVX512 ZMM regs dump
On 4/15/21 7:08 PM, Robert Hoo wrote: Since commit fa4518741e (target-i386: Rename struct XMMReg to ZMMReg), CPUX86State.xmm_regs[] has already been extended to 512bit to support AVX512. Also, other qemu level supports for AVX512 registers are there for years. But in x86_cpu_dump_state(), still only dump XMM registers no matter YMM/ZMM is enabled. This patch is to complement this, let it dump XMM/YMM/ZMM accordingly. Signed-off-by: Robert Hoo --- Changelog: v5: fix a minor issue. rebase to latest master. v4: stringent AVX512 case and AVX case judgement criteria v3: fix some coding style issue. v2: dump XMM/YMM/ZMM according to XSAVE state-components enablement. target/i386/cpu-dump.c | 62 ++ 1 file changed, 47 insertions(+), 15 deletions(-) Reviewed-by: Richard Henderson r~
[PATCH v5] i386/cpu_dump: support AVX512 ZMM regs dump
Since commit fa4518741e (target-i386: Rename struct XMMReg to ZMMReg),
CPUX86State.xmm_regs[] has already been extended to 512bit to support
AVX512.
Also, other qemu level supports for AVX512 registers are there for
years.
But in x86_cpu_dump_state(), still only dump XMM registers no matter
YMM/ZMM is enabled.
This patch is to complement this, let it dump XMM/YMM/ZMM accordingly.
Signed-off-by: Robert Hoo
---
Changelog:
v5: fix a minor issue. rebase to latest master.
v4: stringent AVX512 case and AVX case judgement criteria
v3: fix some coding style issue.
v2: dump XMM/YMM/ZMM according to XSAVE state-components enablement.
target/i386/cpu-dump.c | 62 ++
1 file changed, 47 insertions(+), 15 deletions(-)
diff --git a/target/i386/cpu-dump.c b/target/i386/cpu-dump.c
index aac21f1..ece64e1 100644
--- a/target/i386/cpu-dump.c
+++ b/target/i386/cpu-dump.c
@@ -478,6 +478,11 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags)
qemu_fprintf(f, "EFER=%016" PRIx64 "\n", env->efer);
if (flags & CPU_DUMP_FPU) {
int fptag;
+const uint64_t avx512_mask = XSTATE_OPMASK_MASK | \
+ XSTATE_ZMM_Hi256_MASK | \
+ XSTATE_Hi16_ZMM_MASK | \
+ XSTATE_YMM_MASK | XSTATE_SSE_MASK,
+ avx_mask = XSTATE_YMM_MASK | XSTATE_SSE_MASK;
fptag = 0;
for(i = 0; i < 8; i++) {
fptag |= ((!env->fptags[i]) << i);
@@ -499,21 +504,48 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags)
else
qemu_fprintf(f, " ");
}
-if (env->hflags & HF_CS64_MASK)
-nb = 16;
-else
-nb = 8;
-for(i=0;ixmm_regs[i].ZMM_L(3),
- env->xmm_regs[i].ZMM_L(2),
- env->xmm_regs[i].ZMM_L(1),
- env->xmm_regs[i].ZMM_L(0));
-if ((i & 1) == 1)
-qemu_fprintf(f, "\n");
-else
-qemu_fprintf(f, " ");
+
+if ((env->xcr0 & avx512_mask) == avx512_mask) {
+/* XSAVE enabled AVX512 */
+for (i = 0; i < NB_OPMASK_REGS; i++) {
+qemu_fprintf(f, "Opmask%02d=%016lx%s", i, env->opmask_regs[i],
+((i & 3) == 3) ? "\n" : " ");
+}
+
+nb = (env->hflags & HF_CS64_MASK) ? 32 : 8;
+for (i = 0; i < nb; i++) {
+qemu_fprintf(f, "ZMM%02d=%016lx %016lx %016lx %016lx %016lx "
+"%016lx %016lx %016lx\n",
+ i,
+ env->xmm_regs[i].ZMM_Q(7),
+ env->xmm_regs[i].ZMM_Q(6),
+ env->xmm_regs[i].ZMM_Q(5),
+ env->xmm_regs[i].ZMM_Q(4),
+ env->xmm_regs[i].ZMM_Q(3),
+ env->xmm_regs[i].ZMM_Q(2),
+ env->xmm_regs[i].ZMM_Q(1),
+ env->xmm_regs[i].ZMM_Q(0));
+}
+} else if ((env->xcr0 & avx_mask) == avx_mask) {
+/* XSAVE enabled AVX */
+nb = env->hflags & HF_CS64_MASK ? 16 : 8;
+for (i = 0; i < nb; i++) {
+qemu_fprintf(f, "YMM%02d=%016lx %016lx %016lx %016lx\n",
+ i,
+ env->xmm_regs[i].ZMM_Q(3),
+ env->xmm_regs[i].ZMM_Q(2),
+ env->xmm_regs[i].ZMM_Q(1),
+ env->xmm_regs[i].ZMM_Q(0));
+}
+} else { /* SSE and below cases */
+nb = env->hflags & HF_CS64_MASK ? 16 : 8;
+for (i = 0; i < nb; i++) {
+qemu_fprintf(f, "XMM%02d=%016lx %016lx%s",
+ i,
+ env->xmm_regs[i].ZMM_Q(1),
+ env->xmm_regs[i].ZMM_Q(0),
+ (i & 1) ? "\n" : " ");
+}
}
}
if (flags & CPU_DUMP_CODE) {
--
1.8.3.1
