Alexey Kardashevskiy a...@ozlabs.ru writes:
On 07/13/2013 06:03 PM, David Gibson wrote:
On Fri, Jul 12, 2013 at 05:37:19PM +1000, Alexey Kardashevskiy wrote:
sPAPR PHB emulates IO ports on PCI via a special memory region which
routes all reads/writes further via cpu_in*/cpu_out* which are
On 07/16/2013 01:02 AM, Anthony Liguori wrote:
Alexey Kardashevskiy a...@ozlabs.ru writes:
On 07/13/2013 06:03 PM, David Gibson wrote:
On Fri, Jul 12, 2013 at 05:37:19PM +1000, Alexey Kardashevskiy wrote:
sPAPR PHB emulates IO ports on PCI via a special memory region which
routes all
Alexey Kardashevskiy a...@ozlabs.ru writes:
On 07/16/2013 01:02 AM, Anthony Liguori wrote:
Alexey Kardashevskiy a...@ozlabs.ru writes:
On 07/13/2013 06:03 PM, David Gibson wrote:
On Fri, Jul 12, 2013 at 05:37:19PM +1000, Alexey Kardashevskiy wrote:
sPAPR PHB emulates IO ports on PCI via a
On 07/16/2013 10:28 AM, Anthony Liguori wrote:
Alexey Kardashevskiy a...@ozlabs.ru writes:
On 07/16/2013 01:02 AM, Anthony Liguori wrote:
Alexey Kardashevskiy a...@ozlabs.ru writes:
On 07/13/2013 06:03 PM, David Gibson wrote:
On Fri, Jul 12, 2013 at 05:37:19PM +1000, Alexey Kardashevskiy
On Mon, Jul 15, 2013 at 7:39 PM, Alexey Kardashevskiy a...@ozlabs.ru wrote:
On 07/16/2013 10:28 AM, Anthony Liguori wrote:
Alexey Kardashevskiy a...@ozlabs.ru writes:
The right solution is to drop the additional IO region on sPAPR and
remove the ISA devices marking themselves as little
On 07/16/2013 12:05 PM, Anthony Liguori wrote:
On Mon, Jul 15, 2013 at 7:39 PM, Alexey Kardashevskiy a...@ozlabs.ru wrote:
On 07/16/2013 10:28 AM, Anthony Liguori wrote:
Alexey Kardashevskiy a...@ozlabs.ru writes:
The right solution is to drop the additional IO region on sPAPR and
remove the
On 07/13/2013 06:03 PM, David Gibson wrote:
On Fri, Jul 12, 2013 at 05:37:19PM +1000, Alexey Kardashevskiy wrote:
sPAPR PHB emulates IO ports on PCI via a special memory region which
routes all reads/writes further via cpu_in*/cpu_out* which are eventually
processed by MemoryRegionOps
On Fri, Jul 12, 2013 at 05:37:19PM +1000, Alexey Kardashevskiy wrote:
sPAPR PHB emulates IO ports on PCI via a special memory region which
routes all reads/writes further via cpu_in*/cpu_out* which are eventually
processed by MemoryRegionOps implemented by devices.
Hrm. That double dispatch
sPAPR PHB emulates IO ports on PCI via a special memory region which
routes all reads/writes further via cpu_in*/cpu_out* which are eventually
processed by MemoryRegionOps implemented by devices.
As devices normally take care of endianness themselves by setting
correct MemoryRegionOps::endianness
