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Subject: Re: [Qemu-devel] [PATCH v1 2/2] intel-iommu: Extend address width to 48
bits
Hi Yi L,
On 12/1/2017 3:29 AM, Liu, Yi L wrote:
On Tue, Nov 14, 2017 at
ad.w...@oracle.com; qemu-
> de...@nongnu.org; pet...@redhat.com; imamm...@redhat.com;
> pbonz...@redhat.com; r...@twiddle.net
> Subject: Re: [Qemu-devel] [PATCH v1 2/2] intel-iommu: Extend address width to
> 48
> bits
>
>
> Hi Yi L,
>
> On 12/1/2017 3:29 AM, Liu, Yi
Hi Yi L,
On 12/1/2017 3:29 AM, Liu, Yi L wrote:
On Tue, Nov 14, 2017 at 06:13:50PM -0500, prasad.singamse...@oracle.com wrote:
From: Prasad Singamsetty
The current implementation of Intel IOMMU code only supports 39 bits
iova address width. This patch provides
On Fri, Dec 01, 2017 at 09:02:30AM -0800, Prasad Singamsetty wrote:
[...]
>
> >
> > And... you may also need to create that PC_COMPAT_2_11 macro after
> > 2.11 is released. For that you can refer to a6fd5b0e050a.
> >
> > Anyway, I think this "set default" work can be postponed after recent
>
On 11/30/2017 8:43 PM, Peter Xu wrote:
On Thu, Nov 30, 2017 at 11:12:48AM -0800, Prasad Singamsetty wrote:
On 11/30/2017 10:56 AM, Michael S. Tsirkin wrote:
On Thu, Nov 30, 2017 at 10:33:50AM -0800, Prasad Singamsetty wrote:
On 11/29/2017 7:25 PM, Peter Xu wrote:
On Wed, Nov 29, 2017
On 11/29/2017 7:25 PM, Peter Xu wrote:
On Wed, Nov 29, 2017 at 01:05:22PM -0800, Prasad Singamsetty wrote:
Thanks Michael. Some comments below.
On 11/28/2017 9:32 AM, Michael S. Tsirkin wrote:
On Tue, Nov 14, 2017 at 06:13:50PM -0500, prasad.singamse...@oracle.com wrote:
From: Prasad
On Fri, Dec 01, 2017 at 09:02:30AM -0800, Prasad Singamsetty wrote:
>
>
> On 11/30/2017 8:43 PM, Peter Xu wrote:
> > On Thu, Nov 30, 2017 at 11:12:48AM -0800, Prasad Singamsetty wrote:
> > >
> > >
> > > On 11/30/2017 10:56 AM, Michael S. Tsirkin wrote:
> > > > On Thu, Nov 30, 2017 at
On Thu, Nov 30, 2017 at 11:12:48AM -0800, Prasad Singamsetty wrote:
>
>
> On 11/30/2017 10:56 AM, Michael S. Tsirkin wrote:
> > On Thu, Nov 30, 2017 at 10:33:50AM -0800, Prasad Singamsetty wrote:
> > >
> > >
> > > On 11/29/2017 7:25 PM, Peter Xu wrote:
> > > > On Wed, Nov 29, 2017 at
On 11/30/2017 10:56 AM, Michael S. Tsirkin wrote:
On Thu, Nov 30, 2017 at 10:33:50AM -0800, Prasad Singamsetty wrote:
On 11/29/2017 7:25 PM, Peter Xu wrote:
On Wed, Nov 29, 2017 at 01:05:22PM -0800, Prasad Singamsetty wrote:
Thanks Michael. Some comments below.
On 11/28/2017 9:32 AM,
On Tue, Nov 14, 2017 at 06:13:50PM -0500, prasad.singamse...@oracle.com wrote:
> From: Prasad Singamsetty
>
> The current implementation of Intel IOMMU code only supports 39 bits
> iova address width. This patch provides a new parameter (x-aw-bits)
> for
On Thu, Nov 30, 2017 at 10:33:50AM -0800, Prasad Singamsetty wrote:
>
>
> On 11/29/2017 7:25 PM, Peter Xu wrote:
> > On Wed, Nov 29, 2017 at 01:05:22PM -0800, Prasad Singamsetty wrote:
> > > Thanks Michael. Some comments below.
> > >
> > > On 11/28/2017 9:32 AM, Michael S. Tsirkin wrote:
> > >
On Thu, Nov 30, 2017 at 05:54:35PM +0800, Liu, Yi L wrote:
> On Thu, Nov 30, 2017 at 05:11:55PM +0800, Peter Xu wrote:
> > On Thu, Nov 30, 2017 at 01:22:38PM +0800, Liu, Yi L wrote:
> > > On Tue, Nov 14, 2017 at 06:13:50PM -0500, prasad.singamse...@oracle.com
> > > wrote:
> > > > From: Prasad
On Thu, Nov 30, 2017 at 05:11:55PM +0800, Peter Xu wrote:
> On Thu, Nov 30, 2017 at 01:22:38PM +0800, Liu, Yi L wrote:
> > On Tue, Nov 14, 2017 at 06:13:50PM -0500, prasad.singamse...@oracle.com
> > wrote:
> > > From: Prasad Singamsetty
> > >
> > > The current
On Thu, Nov 30, 2017 at 01:22:38PM +0800, Liu, Yi L wrote:
> On Tue, Nov 14, 2017 at 06:13:50PM -0500, prasad.singamse...@oracle.com wrote:
> > From: Prasad Singamsetty
> >
> > The current implementation of Intel IOMMU code only supports 39 bits
> > iova address
On Tue, Nov 14, 2017 at 06:13:50PM -0500, prasad.singamse...@oracle.com wrote:
> From: Prasad Singamsetty
>
> The current implementation of Intel IOMMU code only supports 39 bits
> iova address width. This patch provides a new parameter (x-aw-bits)
> for
On Wed, Nov 29, 2017 at 01:05:22PM -0800, Prasad Singamsetty wrote:
> Thanks Michael. Some comments below.
>
> On 11/28/2017 9:32 AM, Michael S. Tsirkin wrote:
> > On Tue, Nov 14, 2017 at 06:13:50PM -0500, prasad.singamse...@oracle.com
> > wrote:
> > > From: Prasad Singamsetty
Thanks Michael. Some comments below.
On 11/28/2017 9:32 AM, Michael S. Tsirkin wrote:
On Tue, Nov 14, 2017 at 06:13:50PM -0500, prasad.singamse...@oracle.com wrote:
From: Prasad Singamsetty
The current implementation of Intel IOMMU code only supports 39 bits
On Tue, Nov 14, 2017 at 06:13:50PM -0500, prasad.singamse...@oracle.com wrote:
> From: Prasad Singamsetty
>
> The current implementation of Intel IOMMU code only supports 39 bits
> iova address width. This patch provides a new parameter (x-aw-bits)
> for
From: Prasad Singamsetty
The current implementation of Intel IOMMU code only supports 39 bits
iova address width. This patch provides a new parameter (x-aw-bits)
for intel-iommu to extend its address width to 48 bits but keeping the
default the same (39 bits). The
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