I just want to mention that we've been running this patch set in
production for a few days, doing hundreds of Fedora RISC-V builds with
‘-smp 4’ and it has been rock solid.
Therefore:
Tested-by: Richard W.M. Jones
Rich.
--
Richard Jones, Virtualization Group, Red Hat http://people.redhat.com
On Sat, Feb 10, 2018 at 8:42 AM, Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 02/07/2018 05:28 PM, Michael Clark wrote:
> > create mode 100644 hw/riscv/Makefile.objs
> > create mode 100644 hw/riscv/riscv_elf.c
> > create mode 100644 hw/riscv/riscv_hart.c
> > create mode 100644
On 02/07/2018 05:28 PM, Michael Clark wrote:
> create mode 100644 hw/riscv/Makefile.objs
> create mode 100644 hw/riscv/riscv_elf.c
> create mode 100644 hw/riscv/riscv_hart.c
> create mode 100644 hw/riscv/riscv_htif.c
> create mode 100644 hw/riscv/sifive_clint.c
> create mode 100644 hw/riscv/s
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1518053328-34687-1-git-send-email-...@sifive.com
Subject: [Qemu-devel] [PATCH v5 00/23] RISC-V QEMU Port Submission
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
We are now passing all but one of the set of tests cases in riscv-tests.
The one failing set of tests relates to support for "9.2 NaN Boxing of
Narrower Values" as per the RISC-V ISA Specification v2.2. The remaining
case is where we try to use a single-precision operation on an input that
doesn't
To paraphrase; the case we are failing on is a corner case, where a
register containing a double is used as input to a single precision op. It
won't happen in correct code.
On Thu, Feb 8, 2018 at 2:55 PM, Michael Clark wrote:
> We are now passing all but one of the set of tests cases in riscv-te
QEMU RISC-V Emulation Support (RV64GC, RV32GC)
This version of the RISC-V patch series "lucky number five" contains
cleanups to the FPU code, fixes several FPU related test failures in
riscv-tests and updates the syscalls for RISC-V linux-user emulation.
The git tree for this v5 patch series (squ
