Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Michael Clark]

On Fri, Mar 9, 2018 at 12:48 AM, Daniel P. Berrangé 
wrote:

> On Thu, Mar 08, 2018 at 11:18:30AM +, Michael Clark wrote:
> > On Fri, 9 Mar 2018 at 12:10 AM, Michael Clark  wrote:
> >
> > > On Thu, 8 Mar 2018 at 11:02 PM, Peter Maydell <
> peter.mayd...@linaro.org>
> > > wrote:
> > >
> > >> On 6 March 2018 at 19:46, Michael Clark  wrote:
> > >> > -BEGIN PGP SIGNED MESSAGE-
> > >> > Hash: SHA1
> > >> >
> > >> > The following changes since commit
> > >> f32408f3b472a088467474ab152be3b6285b2d7b:
> > >> >
> > >> >   misc: don't use hwaddr as a type in trace events (2018-03-06
> 14:24:30
> > >> +)
> > >> >
> > >> > are available in the git repository at:
> > >> >
> > >> >   https://github.com/riscv/riscv-qemu.git
> tags/riscv-qemu-upstream-v8.2
> > >> >
> > >> > for you to fetch changes up to 7051b081bf6796e5e84406f6223a7c
> 4900bf7298:
> > >> >
> > >> >   RISC-V - Remove support for adhoc non-standard X_COP
> local-interrupt
> > >> (2018-03-07 08:36:03 +1300)
> > >>
> > >>
> > >> Hi -- I would have applied this, but some of the commits
> > >> have no signed-off-by lines.
> > >>
> > >> This is important, and I've already asked for it once. We cannot
> > >> accept anything that doesn't have a clear record in the commit
> > >> message of everybody (person or company) who's contributed code
> > >> to it, indicating that they're happy for their copyrighted
> > >> contributions to be taken into QEMU under our license. Lists
> > >> of names without emails in the cover letter are not sufficient.
> > >>
> > >> In fact a lot of the last part of this patchset looks like
> > >> unreviewed changes/fixes that if we were going to have them we
> > >> should have squashed into the correct patches and resent the
> > >> series for review. Please don't do this. Code review is an
> > >> important part of how the QEMU project works.
> > >
> > >
> > > You must be looking at the wrong tag. There are multiple sign-offs in
> all
> > > 23 commits. The tag is riscv-qemu-upstream-v8.2. Sagar and Bastian
> > > contacted me out of band to add their sign-offs. Please look at the
> commits
> > > again and tell me which commit id doesn’t have a sign-off on that tag
> (23
> > > commits iirc)
> > >
> >
> > I can forward you the mail out-of-band. I had to contact contributors to
> > get them to agree to change the license from MIT to GPLv2, based on a
> > request from Red Hat.
> >
> > You are making this very hard. Do you work for Arm perchance? I really
> > wouldn’t be surprised if our port is being sandbagged by Arm. Apologies
> for
> > being so direct about this, but things like this happen...
> >
> > I have complied with practically every review request and the sign-offs
> are
> > there. It’s a bit ridiculous.
> >
> > It would be nice to find someone neutral, unrelated to Arm, to merge our
> PR
>
> Please stop with these ridiculous conspiracy theories right away. It is a
> totally inappropriate and baseless accusation to make.
>

My apologies. I do tend towards conspiratorial thinking, and this is
related to a pain and anxiety disorder combined with insomnia. It seems the
issue is completely my fault and i'll apologise again on this email. I will
refrain from making any non-technical comments after this. I'm not trying
to make an excuse. I do tend towards conspiratorial thinking.

I'm obviously having trouble moving from a Github PR / merge flow, to a
Linux git-send-email based flow.

The Linux git-send-email based flow has a steeper learning curve... and the
mistakes are completely mine...

Sorry. I sincerely hope its accepted.

Peter is not trying to punish you with extra rules. Over time QEMU has been
> raising the bar for *all* contributions with extra code style checks,
> automated testing, and review. Unfortunately this does mean that the larger
> the patch series / feature, the more work is required to get to a mergable
> state, especially if the contributors are not previously familiar with QEMU
> development.
>
> Regards,
> Daniel
> --
> |: https://berrange.com  -o-https://www.flickr.com/photos/
> dberrange :|
> |: https://libvirt.org -o-
> https://fstop138.berrange.com :|
> |: https://entangle-photo.org-o-https://www.instagram.com/
> dberrange :|
>

Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Paolo Bonzini]

On 08/03/2018 13:25, Daniel P. Berrangé wrote:
> So I think you likely just need to create a v8.3 branch and
> tag with the correct set of 23 commits. Though, do note Paolo's
> comment about logic looking wrong in one of the patches. I'm
> not sure if that's something we can live with now, and fix
> up in followup patches before release or not, vs should be
> fixed right away.
> 

Luckily the logic is wrong in one of the extra 22 commits.

Paolo

Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Daniel P . Berrangé]

On Wed, Mar 07, 2018 at 08:46:26AM +1300, Michael Clark wrote:
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA1
> 
> The following changes since commit f32408f3b472a088467474ab152be3b6285b2d7b:
> 
>   misc: don't use hwaddr as a type in trace events (2018-03-06 14:24:30 +)
> 
> are available in the git repository at:
> 
>   https://github.com/riscv/riscv-qemu.git tags/riscv-qemu-upstream-v8.2
> 
> for you to fetch changes up to 7051b081bf6796e5e84406f6223a7c4900bf7298:
> 
>   RISC-V - Remove support for adhoc non-standard X_COP local-interrupt 
> (2018-03-07 08:36:03 +1300)

So to move this forward in a productive way

IIUC, the 'qemu-upstream-v8.2' branch has the correct set of 23
patches, but the 'riscv-qemu-upstream-v8.2' tag has mistakenly
gained a bunch of extra patches that were not intended for
submission yet.

So I think you likely just need to create a v8.3 branch and
tag with the correct set of 23 commits. Though, do note Paolo's
comment about logic looking wrong in one of the patches. I'm
not sure if that's something we can live with now, and fix
up in followup patches before release or not, vs should be
fixed right away.

The 'soft freeze' on next Tuesday only applies to feature
patches. So assuming we can get this initial series mergable,
you will still have time to send more pull requests with bug
fixes before release.


Regards,
Daniel
-- 
|: https://berrange.com  -o-https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o-https://fstop138.berrange.com :|
|: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|

Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Stefan Hajnoczi]

On Thu, Mar 8, 2018 at 11:41 AM, Michael Clark  wrote:
> On Fri, 9 Mar 2018 at 12:18 AM, Michael Clark  wrote:
>
>> On Fri, 9 Mar 2018 at 12:10 AM, Michael Clark  wrote:
>>
>>> On Thu, 8 Mar 2018 at 11:02 PM, Peter Maydell 
>>> wrote:
>>>
 On 6 March 2018 at 19:46, Michael Clark  wrote:
 > -BEGIN PGP SIGNED MESSAGE-
 > Hash: SHA1
 >
 > The following changes since commit
 f32408f3b472a088467474ab152be3b6285b2d7b:
 >
 >   misc: don't use hwaddr as a type in trace events (2018-03-06
 14:24:30 +)
 >
 > are available in the git repository at:
 >
 >   https://github.com/riscv/riscv-qemu.git
 tags/riscv-qemu-upstream-v8.2
 >
 > for you to fetch changes up to
 7051b081bf6796e5e84406f6223a7c4900bf7298:
 >
 >   RISC-V - Remove support for adhoc non-standard X_COP local-interrupt
 (2018-03-07 08:36:03 +1300)


 Hi -- I would have applied this, but some of the commits
 have no signed-off-by lines.

 This is important, and I've already asked for it once. We cannot
 accept anything that doesn't have a clear record in the commit
 message of everybody (person or company) who's contributed code
 to it, indicating that they're happy for their copyrighted
 contributions to be taken into QEMU under our license. Lists
 of names without emails in the cover letter are not sufficient.

 In fact a lot of the last part of this patchset looks like
 unreviewed changes/fixes that if we were going to have them we
 should have squashed into the correct patches and resent the
 series for review. Please don't do this. Code review is an
 important part of how the QEMU project works.
>>>
>>>
>>> You must be looking at the wrong tag. There are multiple sign-offs in all
>>> 23 commits. The tag is riscv-qemu-upstream-v8.2. Sagar and Bastian
>>> contacted me out of band to add their sign-offs. Please look at the commits
>>> again and tell me which commit id doesn’t have a sign-off on that tag (23
>>> commits iirc)
>>>
>>
>> I can forward you the mail out-of-band. I had to contact contributors to
>> get them to agree to change the license from MIT to GPLv2, based on a
>> request from Red Hat.
>>
>> You are making this very hard. Do you work for Arm perchance? I really
>> wouldn’t be surprised if our port is being sandbagged by Arm. Apologies for
>> being so direct about this, but things like this happen...
>>
>> I have complied with practically every review request and the sign-offs
>> are there. It’s a bit ridiculous.
>>
>> It would be nice to find someone neutral, unrelated to Arm, to merge our PR
>>
>
> Some history on the origins of RISC to put things in perspective:
>
> https://en.m.wikipedia.org/wiki/Berkeley_RISC
>
> David Patterson worked with Andrew Waterman and Krste Asanovic on the
> design of RISC-V. Sagar did most of the work on the QEMU port and he
> agreeded to sign off on all patches. The SiFive patches only have sign-offs
> from SiFive because SiFive was the sole contributor for its hardware model,
> beside the SiFiveUART which has Stefan’s sign-off.
>
> In any case it seems there is not enough review bandwidth in the QEMU
> project as a whole and the policy to accept contributions is too strict to
> be reasonable, given earnest attempts to comply with *all* review feedback.
> Not impressed.

Please take a break and stop sending emails which are going to offend
the people you need to collaborate with in order to get RISC-V support
merged.

The issues that Peter Maydell raised are completely routine pull
request requirements.  Linux has the same Signed-off-by requirement,
so it's not a QEMU-specific hurdle.

If you want to be the RISC-V maintainer in QEMU then work with Peter
Maydell (qemu.git maintainer).

Stefan

Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Daniel P . Berrangé]

On Thu, Mar 08, 2018 at 11:18:30AM +, Michael Clark wrote:
> On Fri, 9 Mar 2018 at 12:10 AM, Michael Clark  wrote:
> 
> > On Thu, 8 Mar 2018 at 11:02 PM, Peter Maydell 
> > wrote:
> >
> >> On 6 March 2018 at 19:46, Michael Clark  wrote:
> >> > -BEGIN PGP SIGNED MESSAGE-
> >> > Hash: SHA1
> >> >
> >> > The following changes since commit
> >> f32408f3b472a088467474ab152be3b6285b2d7b:
> >> >
> >> >   misc: don't use hwaddr as a type in trace events (2018-03-06 14:24:30
> >> +)
> >> >
> >> > are available in the git repository at:
> >> >
> >> >   https://github.com/riscv/riscv-qemu.git tags/riscv-qemu-upstream-v8.2
> >> >
> >> > for you to fetch changes up to 7051b081bf6796e5e84406f6223a7c4900bf7298:
> >> >
> >> >   RISC-V - Remove support for adhoc non-standard X_COP local-interrupt
> >> (2018-03-07 08:36:03 +1300)
> >>
> >>
> >> Hi -- I would have applied this, but some of the commits
> >> have no signed-off-by lines.
> >>
> >> This is important, and I've already asked for it once. We cannot
> >> accept anything that doesn't have a clear record in the commit
> >> message of everybody (person or company) who's contributed code
> >> to it, indicating that they're happy for their copyrighted
> >> contributions to be taken into QEMU under our license. Lists
> >> of names without emails in the cover letter are not sufficient.
> >>
> >> In fact a lot of the last part of this patchset looks like
> >> unreviewed changes/fixes that if we were going to have them we
> >> should have squashed into the correct patches and resent the
> >> series for review. Please don't do this. Code review is an
> >> important part of how the QEMU project works.
> >
> >
> > You must be looking at the wrong tag. There are multiple sign-offs in all
> > 23 commits. The tag is riscv-qemu-upstream-v8.2. Sagar and Bastian
> > contacted me out of band to add their sign-offs. Please look at the commits
> > again and tell me which commit id doesn’t have a sign-off on that tag (23
> > commits iirc)
> >
> 
> I can forward you the mail out-of-band. I had to contact contributors to
> get them to agree to change the license from MIT to GPLv2, based on a
> request from Red Hat.
> 
> You are making this very hard. Do you work for Arm perchance? I really
> wouldn’t be surprised if our port is being sandbagged by Arm. Apologies for
> being so direct about this, but things like this happen...
> 
> I have complied with practically every review request and the sign-offs are
> there. It’s a bit ridiculous.
> 
> It would be nice to find someone neutral, unrelated to Arm, to merge our PR

Please stop with these ridiculous conspiracy theories right away. It is a
totally inappropriate and baseless accusation to make. 

Peter is not trying to punish you with extra rules. Over time QEMU has been 
raising the bar for *all* contributions with extra code style checks,
automated testing, and review. Unfortunately this does mean that the larger
the patch series / feature, the more work is required to get to a mergable
state, especially if the contributors are not previously familiar with QEMU
development. 

Regards,
Daniel
-- 
|: https://berrange.com  -o-https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o-https://fstop138.berrange.com :|
|: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|

Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Paolo Bonzini]

On 08/03/2018 12:18, Michael Clark wrote:
>> There are multiple sign-offs in all
>> 23 commits. The tag is riscv-qemu-upstream-v8.2

Except your cover letter lists 45 commits and, as Daniel has already confirmed,
Peter is right: these commits listed in the cover letter have no sign-off and
have not been reviewed:

  RISC-V - Make virt create_fdt interface consistent with other boards
  RISC-V - Replace hardcoded device-tree constants with enum values
  RISC-V - Make virt board description match spike format
  RISC-V - Use ROM base address and size constants from memory map
  RISC-V - Remove redundant identity_translate callback from load_elf
  RISC-V - Mark ROM read-only after copying in reset vector and config
  RISC-V - Remove unused class definitions from machines
  RISC-V - Make sure the emulated mask rom has space for device-tree
  RISC-V - Include hexidecimal instruction packets in disassembly
  RISC-V - Need to hold rcu_read_lock when accessing memory directly
  RISC-V - Improve page table walker spec compliance and add comments
  RISC-V - Update E order and note that add E and I are mutually exclusive
  RISC-V - Make spike and virt header guards more specific
  RISC-V - Make virt header comment consistent with source file
  RISC-V - Use memory_region_is_ram in atomic pte update
  RISC-V - Remove EM_RISCV ELF_MACHINE indirection from load_elf
  RISC-V - Ingore satp writes and return 0 for reads when no-mmu
  RISC-V - Remove braces from satp case statement with no locals
  RISC-V - riscv-qemu port supports sv39 and sv48
  RISC-V - vectored traps for asynchrounous interrupts are optional
  RISC-V - Dont' trap on writes to misa,minstret[h],mcycle[h]
  RISC-V - Remove support for adhoc non-standard X_COP local-interrupt

> You are making this very hard. Do you work for Arm perchance? I really
> wouldn’t be surprised if our port is being sandbagged by Arm. Apologies for
> being so direct about this, but things like this happen...
> 
> I have complied with practically every review request and the sign-offs are
> there. It’s a bit ridiculous.
> 
> It would be nice to find someone neutral, unrelated to Arm, to merge our PR

Just don't do this.  If you don't trust the maintainers, I don't see why 
the maintainers should merge the RISC-V port; no one needs an history
lesson on RISC or ARM or RISC-V either.  And you can understand that adding
and reviewing 10K lines of code requires a significant effort, that some of
the maintainers are doing in their spare time.

In fact, I looked at "RISC-V - Need to hold rcu_read_lock when accessing
memory directly" and from a first look it's wrong.  So I think you owe an
apology...

Paolo

Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Daniel P . Berrangé]

On Thu, Mar 08, 2018 at 11:33:13AM +, Daniel P. Berrangé wrote:
> On Thu, Mar 08, 2018 at 11:10:00AM +, Michael Clark wrote:
> > On Thu, 8 Mar 2018 at 11:02 PM, Peter Maydell 
> > wrote:
> > 
> > > On 6 March 2018 at 19:46, Michael Clark  wrote:
> > > > -BEGIN PGP SIGNED MESSAGE-
> > > > Hash: SHA1
> > > >
> > > > The following changes since commit
> > > f32408f3b472a088467474ab152be3b6285b2d7b:
> > > >
> > > >   misc: don't use hwaddr as a type in trace events (2018-03-06 14:24:30
> > > +)
> > > >
> > > > are available in the git repository at:
> > > >
> > > >   https://github.com/riscv/riscv-qemu.git tags/riscv-qemu-upstream-v8.2
> > > >
> > > > for you to fetch changes up to 7051b081bf6796e5e84406f6223a7c4900bf7298:
> > > >
> > > >   RISC-V - Remove support for adhoc non-standard X_COP local-interrupt
> > > (2018-03-07 08:36:03 +1300)
> > >
> > >
> > > Hi -- I would have applied this, but some of the commits
> > > have no signed-off-by lines.
> > >
> > > This is important, and I've already asked for it once. We cannot
> > > accept anything that doesn't have a clear record in the commit
> > > message of everybody (person or company) who's contributed code
> > > to it, indicating that they're happy for their copyrighted
> > > contributions to be taken into QEMU under our license. Lists
> > > of names without emails in the cover letter are not sufficient.
> > >
> > > In fact a lot of the last part of this patchset looks like
> > > unreviewed changes/fixes that if we were going to have them we
> > > should have squashed into the correct patches and resent the
> > > series for review. Please don't do this. Code review is an
> > > important part of how the QEMU project works.
> > 
> > 
> > You must be looking at the wrong tag. There are multiple sign-offs in all
> > 23 commits. The tag is riscv-qemu-upstream-v8.2. Sagar and Bastian
> > contacted me out of band to add their sign-offs. Please look at the commits
> > again and tell me which commit id doesn’t have a sign-off on that tag (23
> > commits iirc)
> 
> I've just looked at the "riscv-qemu-upstream-v8.2" tag and confirm that
> the sign-offs all appear present and corrrect to me.

Actually after double checking this not correct. There are two similarly
named but subtely different tags.

Your mail referenced 'riscv-qemu-upstream-v8.2' and that does contain
extra commits without signoffs.

There is another tag 'qemu-upstream-v8.2' that contains only the
signed-off commits.

So did you mention the wrong tag in the cover letter, or push the
wrong content ?

Regards,
Daniel
-- 
|: https://berrange.com  -o-https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o-https://fstop138.berrange.com :|
|: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|

Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Michael Clark]

On Fri, 9 Mar 2018 at 12:18 AM, Michael Clark  wrote:

> On Fri, 9 Mar 2018 at 12:10 AM, Michael Clark  wrote:
>
>> On Thu, 8 Mar 2018 at 11:02 PM, Peter Maydell 
>> wrote:
>>
>>> On 6 March 2018 at 19:46, Michael Clark  wrote:
>>> > -BEGIN PGP SIGNED MESSAGE-
>>> > Hash: SHA1
>>> >
>>> > The following changes since commit
>>> f32408f3b472a088467474ab152be3b6285b2d7b:
>>> >
>>> >   misc: don't use hwaddr as a type in trace events (2018-03-06
>>> 14:24:30 +)
>>> >
>>> > are available in the git repository at:
>>> >
>>> >   https://github.com/riscv/riscv-qemu.git
>>> tags/riscv-qemu-upstream-v8.2
>>> >
>>> > for you to fetch changes up to
>>> 7051b081bf6796e5e84406f6223a7c4900bf7298:
>>> >
>>> >   RISC-V - Remove support for adhoc non-standard X_COP local-interrupt
>>> (2018-03-07 08:36:03 +1300)
>>>
>>>
>>> Hi -- I would have applied this, but some of the commits
>>> have no signed-off-by lines.
>>>
>>> This is important, and I've already asked for it once. We cannot
>>> accept anything that doesn't have a clear record in the commit
>>> message of everybody (person or company) who's contributed code
>>> to it, indicating that they're happy for their copyrighted
>>> contributions to be taken into QEMU under our license. Lists
>>> of names without emails in the cover letter are not sufficient.
>>>
>>> In fact a lot of the last part of this patchset looks like
>>> unreviewed changes/fixes that if we were going to have them we
>>> should have squashed into the correct patches and resent the
>>> series for review. Please don't do this. Code review is an
>>> important part of how the QEMU project works.
>>
>>
>> You must be looking at the wrong tag. There are multiple sign-offs in all
>> 23 commits. The tag is riscv-qemu-upstream-v8.2. Sagar and Bastian
>> contacted me out of band to add their sign-offs. Please look at the commits
>> again and tell me which commit id doesn’t have a sign-off on that tag (23
>> commits iirc)
>>
>
> I can forward you the mail out-of-band. I had to contact contributors to
> get them to agree to change the license from MIT to GPLv2, based on a
> request from Red Hat.
>
> You are making this very hard. Do you work for Arm perchance? I really
> wouldn’t be surprised if our port is being sandbagged by Arm. Apologies for
> being so direct about this, but things like this happen...
>
> I have complied with practically every review request and the sign-offs
> are there. It’s a bit ridiculous.
>
> It would be nice to find someone neutral, unrelated to Arm, to merge our PR
>

Some history on the origins of RISC to put things in perspective:

https://en.m.wikipedia.org/wiki/Berkeley_RISC

David Patterson worked with Andrew Waterman and Krste Asanovic on the
design of RISC-V. Sagar did most of the work on the QEMU port and he
agreeded to sign off on all patches. The SiFive patches only have sign-offs
from SiFive because SiFive was the sole contributor for its hardware model,
beside the SiFiveUART which has Stefan’s sign-off.

In any case it seems there is not enough review bandwidth in the QEMU
project as a whole and the policy to accept contributions is too strict to
be reasonable, given earnest attempts to comply with *all* review feedback.
Not impressed.

>

Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Daniel P . Berrangé]

On Thu, Mar 08, 2018 at 11:19:30AM +, Peter Maydell wrote:
> On 8 March 2018 at 11:10, Michael Clark  wrote:
> >
> > On Thu, 8 Mar 2018 at 11:02 PM, Peter Maydell 
> > wrote:
> >>
> >> On 6 March 2018 at 19:46, Michael Clark  wrote:
> >> > -BEGIN PGP SIGNED MESSAGE-
> >> > Hash: SHA1
> >> >
> >> > The following changes since commit
> >> > f32408f3b472a088467474ab152be3b6285b2d7b:
> >> >
> >> >   misc: don't use hwaddr as a type in trace events (2018-03-06 14:24:30
> >> > +)
> >> >
> >> > are available in the git repository at:
> >> >
> >> >   https://github.com/riscv/riscv-qemu.git tags/riscv-qemu-upstream-v8.2
> >> >
> >> > for you to fetch changes up to 7051b081bf6796e5e84406f6223a7c4900bf7298:
> >> >
> >> >   RISC-V - Remove support for adhoc non-standard X_COP local-interrupt
> >> > (2018-03-07 08:36:03 +1300)
> >>
> >>
> >> Hi -- I would have applied this, but some of the commits
> >> have no signed-off-by lines.
> >>
> >> This is important, and I've already asked for it once. We cannot
> >> accept anything that doesn't have a clear record in the commit
> >> message of everybody (person or company) who's contributed code
> >> to it, indicating that they're happy for their copyrighted
> >> contributions to be taken into QEMU under our license. Lists
> >> of names without emails in the cover letter are not sufficient.
> >>
> >> In fact a lot of the last part of this patchset looks like
> >> unreviewed changes/fixes that if we were going to have them we
> >> should have squashed into the correct patches and resent the
> >> series for review. Please don't do this. Code review is an
> >> important part of how the QEMU project works.
> >
> >
> > You must be looking at the wrong tag. There are multiple sign-offs in all 23
> > commits. The tag is riscv-qemu-upstream-v8.2. Sagar and Bastian contacted me
> > out of band to add their sign-offs. Please look at the commits again and
> > tell me which commit id doesn’t have a sign-off on that tag (23 commits
> > iirc)
> 
> I'm looking at the one this email tells me to pull:
>   https://github.com/riscv/riscv-qemu.git tags/riscv-qemu-upstream-v8.2
>   changes up to 7051b081bf6796e5e84406f6223a7c4900bf7298
> 
> Commit 7051b081bf6796e5e84406f6223a7c4900bf7298,
> 9390ed5f4ca5fd3bde10ee2dcf4e7d915d1c189d,
> b38548c4057fb670950a4b94efe5c03b8aba4118,
> etc etc all have no signoff.

There's something peculiar going on when fetching the PR.

I did a 'git fetch riscv/riscv-qemu-upstream-v8.2' which pulled into
FETCH_HEAD. If i do 'git log FETCH_HEAD' then I see those commits
you mention as missing signoff.  If I instead do 'git log 
riscv-qemu-upstream-v8.2'
then all the commits have signoffs - it ranges 
4dc62b15323bb6338c4b426f76e92be55f87db8c...25fa194b7b11901561532e435beb83d046899f7a.

I'm confused why pulling the tag is populating extra commits into
FETCH_HEAD, that are seemingly not part of the tag.

Regards,
Daniel
-- 
|: https://berrange.com  -o-https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o-https://fstop138.berrange.com :|
|: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|

Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Daniel P . Berrangé]

On Thu, Mar 08, 2018 at 11:10:00AM +, Michael Clark wrote:
> On Thu, 8 Mar 2018 at 11:02 PM, Peter Maydell 
> wrote:
> 
> > On 6 March 2018 at 19:46, Michael Clark  wrote:
> > > -BEGIN PGP SIGNED MESSAGE-
> > > Hash: SHA1
> > >
> > > The following changes since commit
> > f32408f3b472a088467474ab152be3b6285b2d7b:
> > >
> > >   misc: don't use hwaddr as a type in trace events (2018-03-06 14:24:30
> > +)
> > >
> > > are available in the git repository at:
> > >
> > >   https://github.com/riscv/riscv-qemu.git tags/riscv-qemu-upstream-v8.2
> > >
> > > for you to fetch changes up to 7051b081bf6796e5e84406f6223a7c4900bf7298:
> > >
> > >   RISC-V - Remove support for adhoc non-standard X_COP local-interrupt
> > (2018-03-07 08:36:03 +1300)
> >
> >
> > Hi -- I would have applied this, but some of the commits
> > have no signed-off-by lines.
> >
> > This is important, and I've already asked for it once. We cannot
> > accept anything that doesn't have a clear record in the commit
> > message of everybody (person or company) who's contributed code
> > to it, indicating that they're happy for their copyrighted
> > contributions to be taken into QEMU under our license. Lists
> > of names without emails in the cover letter are not sufficient.
> >
> > In fact a lot of the last part of this patchset looks like
> > unreviewed changes/fixes that if we were going to have them we
> > should have squashed into the correct patches and resent the
> > series for review. Please don't do this. Code review is an
> > important part of how the QEMU project works.
> 
> 
> You must be looking at the wrong tag. There are multiple sign-offs in all
> 23 commits. The tag is riscv-qemu-upstream-v8.2. Sagar and Bastian
> contacted me out of band to add their sign-offs. Please look at the commits
> again and tell me which commit id doesn’t have a sign-off on that tag (23
> commits iirc)

I've just looked at the "riscv-qemu-upstream-v8.2" tag and confirm that
the sign-offs all appear present and corrrect to me.

There's checkpatch failures on several commits, but you've documented
rationale for ignoring the genuine failures, and the other failures are
false positives.

Regards,
Daniel
-- 
|: https://berrange.com  -o-https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o-https://fstop138.berrange.com :|
|: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|

Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Peter Maydell]

On 8 March 2018 at 11:10, Michael Clark  wrote:
>
> On Thu, 8 Mar 2018 at 11:02 PM, Peter Maydell 
> wrote:
>>
>> On 6 March 2018 at 19:46, Michael Clark  wrote:
>> > -BEGIN PGP SIGNED MESSAGE-
>> > Hash: SHA1
>> >
>> > The following changes since commit
>> > f32408f3b472a088467474ab152be3b6285b2d7b:
>> >
>> >   misc: don't use hwaddr as a type in trace events (2018-03-06 14:24:30
>> > +)
>> >
>> > are available in the git repository at:
>> >
>> >   https://github.com/riscv/riscv-qemu.git tags/riscv-qemu-upstream-v8.2
>> >
>> > for you to fetch changes up to 7051b081bf6796e5e84406f6223a7c4900bf7298:
>> >
>> >   RISC-V - Remove support for adhoc non-standard X_COP local-interrupt
>> > (2018-03-07 08:36:03 +1300)
>>
>>
>> Hi -- I would have applied this, but some of the commits
>> have no signed-off-by lines.
>>
>> This is important, and I've already asked for it once. We cannot
>> accept anything that doesn't have a clear record in the commit
>> message of everybody (person or company) who's contributed code
>> to it, indicating that they're happy for their copyrighted
>> contributions to be taken into QEMU under our license. Lists
>> of names without emails in the cover letter are not sufficient.
>>
>> In fact a lot of the last part of this patchset looks like
>> unreviewed changes/fixes that if we were going to have them we
>> should have squashed into the correct patches and resent the
>> series for review. Please don't do this. Code review is an
>> important part of how the QEMU project works.
>
>
> You must be looking at the wrong tag. There are multiple sign-offs in all 23
> commits. The tag is riscv-qemu-upstream-v8.2. Sagar and Bastian contacted me
> out of band to add their sign-offs. Please look at the commits again and
> tell me which commit id doesn’t have a sign-off on that tag (23 commits
> iirc)

I'm looking at the one this email tells me to pull:
  https://github.com/riscv/riscv-qemu.git tags/riscv-qemu-upstream-v8.2
  changes up to 7051b081bf6796e5e84406f6223a7c4900bf7298

Commit 7051b081bf6796e5e84406f6223a7c4900bf7298,
9390ed5f4ca5fd3bde10ee2dcf4e7d915d1c189d,
b38548c4057fb670950a4b94efe5c03b8aba4118,
etc etc all have no signoff.

thanks
-- PHMM

Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Michael Clark]

On Fri, 9 Mar 2018 at 12:10 AM, Michael Clark  wrote:

> On Thu, 8 Mar 2018 at 11:02 PM, Peter Maydell 
> wrote:
>
>> On 6 March 2018 at 19:46, Michael Clark  wrote:
>> > -BEGIN PGP SIGNED MESSAGE-
>> > Hash: SHA1
>> >
>> > The following changes since commit
>> f32408f3b472a088467474ab152be3b6285b2d7b:
>> >
>> >   misc: don't use hwaddr as a type in trace events (2018-03-06 14:24:30
>> +)
>> >
>> > are available in the git repository at:
>> >
>> >   https://github.com/riscv/riscv-qemu.git tags/riscv-qemu-upstream-v8.2
>> >
>> > for you to fetch changes up to 7051b081bf6796e5e84406f6223a7c4900bf7298:
>> >
>> >   RISC-V - Remove support for adhoc non-standard X_COP local-interrupt
>> (2018-03-07 08:36:03 +1300)
>>
>>
>> Hi -- I would have applied this, but some of the commits
>> have no signed-off-by lines.
>>
>> This is important, and I've already asked for it once. We cannot
>> accept anything that doesn't have a clear record in the commit
>> message of everybody (person or company) who's contributed code
>> to it, indicating that they're happy for their copyrighted
>> contributions to be taken into QEMU under our license. Lists
>> of names without emails in the cover letter are not sufficient.
>>
>> In fact a lot of the last part of this patchset looks like
>> unreviewed changes/fixes that if we were going to have them we
>> should have squashed into the correct patches and resent the
>> series for review. Please don't do this. Code review is an
>> important part of how the QEMU project works.
>
>
> You must be looking at the wrong tag. There are multiple sign-offs in all
> 23 commits. The tag is riscv-qemu-upstream-v8.2. Sagar and Bastian
> contacted me out of band to add their sign-offs. Please look at the commits
> again and tell me which commit id doesn’t have a sign-off on that tag (23
> commits iirc)
>

I can forward you the mail out-of-band. I had to contact contributors to
get them to agree to change the license from MIT to GPLv2, based on a
request from Red Hat.

You are making this very hard. Do you work for Arm perchance? I really
wouldn’t be surprised if our port is being sandbagged by Arm. Apologies for
being so direct about this, but things like this happen...

I have complied with practically every review request and the sign-offs are
there. It’s a bit ridiculous.

It would be nice to find someone neutral, unrelated to Arm, to merge our PR

>

Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Michael Clark]

On Thu, 8 Mar 2018 at 11:02 PM, Peter Maydell 
wrote:

> On 6 March 2018 at 19:46, Michael Clark  wrote:
> > -BEGIN PGP SIGNED MESSAGE-
> > Hash: SHA1
> >
> > The following changes since commit
> f32408f3b472a088467474ab152be3b6285b2d7b:
> >
> >   misc: don't use hwaddr as a type in trace events (2018-03-06 14:24:30
> +)
> >
> > are available in the git repository at:
> >
> >   https://github.com/riscv/riscv-qemu.git tags/riscv-qemu-upstream-v8.2
> >
> > for you to fetch changes up to 7051b081bf6796e5e84406f6223a7c4900bf7298:
> >
> >   RISC-V - Remove support for adhoc non-standard X_COP local-interrupt
> (2018-03-07 08:36:03 +1300)
>
>
> Hi -- I would have applied this, but some of the commits
> have no signed-off-by lines.
>
> This is important, and I've already asked for it once. We cannot
> accept anything that doesn't have a clear record in the commit
> message of everybody (person or company) who's contributed code
> to it, indicating that they're happy for their copyrighted
> contributions to be taken into QEMU under our license. Lists
> of names without emails in the cover letter are not sufficient.
>
> In fact a lot of the last part of this patchset looks like
> unreviewed changes/fixes that if we were going to have them we
> should have squashed into the correct patches and resent the
> series for review. Please don't do this. Code review is an
> important part of how the QEMU project works.


You must be looking at the wrong tag. There are multiple sign-offs in all
23 commits. The tag is riscv-qemu-upstream-v8.2. Sagar and Bastian
contacted me out of band to add their sign-offs. Please look at the commits
again and tell me which commit id doesn’t have a sign-off on that tag (23
commits iirc)

Michael

>
>

Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Peter Maydell]

On 6 March 2018 at 19:46, Michael Clark  wrote:
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA1
>
> The following changes since commit f32408f3b472a088467474ab152be3b6285b2d7b:
>
>   misc: don't use hwaddr as a type in trace events (2018-03-06 14:24:30 +)
>
> are available in the git repository at:
>
>   https://github.com/riscv/riscv-qemu.git tags/riscv-qemu-upstream-v8.2
>
> for you to fetch changes up to 7051b081bf6796e5e84406f6223a7c4900bf7298:
>
>   RISC-V - Remove support for adhoc non-standard X_COP local-interrupt 
> (2018-03-07 08:36:03 +1300)


Hi -- I would have applied this, but some of the commits
have no signed-off-by lines.

This is important, and I've already asked for it once. We cannot
accept anything that doesn't have a clear record in the commit
message of everybody (person or company) who's contributed code
to it, indicating that they're happy for their copyrighted
contributions to be taken into QEMU under our license. Lists
of names without emails in the cover letter are not sufficient.

In fact a lot of the last part of this patchset looks like
unreviewed changes/fixes that if we were going to have them we
should have squashed into the correct patches and resent the
series for review. Please don't do this. Code review is an
important part of how the QEMU project works.

thanks
-- PMM

Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Michael Clark]

On Wed, 7 Mar 2018 at 11:11 PM, Richard W.M. Jones 
wrote:

> On Wed, Mar 07, 2018 at 01:09:29PM +1300, Michael Clark wrote:
> > Hopefully, this PR gets merged...
>
> I hope so too.  We've been testing v8 (substantially the same as v8.2)
> extensively, including SMP.  It's building hundreds of packages a day
> in the autobuilder, and being used for manual builds by several
> people.
>
> Please don't forget about the softfloat fix!  Although it's not
> specific to riscv-qemu, it is required for reliable operation and I
> don't see if in the v8.2 tree.


I’ll try to get it in. I’ve reviewed the new minmax code and it should not
be difficult to add IEEE-754 201x minimumNumber/maximumNumber. I just ran
out of time today.

It’s a relatively rare corner case where the RISC-V behaviour is different
when an sNaN operand and a valid operand are provided to fmin/fmax. The
IEEE-754 201x minimumNumber/maximumNumber always returns the valid operand
when passed anyNaN and a valid operand however an sNaN operand causes the
invalid flag to be raised, whereas iirc the IEEE-764 2008 minNum/maxNum
will raise the invalid flag and return the sNaN when one operand is an sNaN
and the other is valid. Both of their behaviours are the same when passed
qNaN and a valid operand.

I have the test suite which includes both signalling and quiet NaN
fmin/fmax test cases so it is easy to verify and RISC-V is the only QEMU
port to use the IEEE-754 201x  minimumNumber/maximumNumber semantics so we
can easily isolate and test the change without affecting existing code.

Michael

Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Richard W.M. Jones]

On Wed, Mar 07, 2018 at 01:09:29PM +1300, Michael Clark wrote:
> Hopefully, this PR gets merged...

I hope so too.  We've been testing v8 (substantially the same as v8.2)
extensively, including SMP.  It's building hundreds of packages a day
in the autobuilder, and being used for manual builds by several
people.

Please don't forget about the softfloat fix!  Although it's not
specific to riscv-qemu, it is required for reliable operation and I
don't see if in the v8.2 tree.

Rich.

-- 
Richard Jones, Virtualization Group, Red Hat http://people.redhat.com/~rjones
Read my programming and virtualization blog: http://rwmj.wordpress.com
virt-p2v converts physical machines to virtual machines.  Boot with a
live CD or over the network (PXE) and turn machines into KVM guests.
http://libguestfs.org/virt-v2v

Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Michael Clark]

FYI - Travis completed builds for v8.2 and it's all green.

- https://travis-ci.org/riscv/riscv-qemu/builds/349981074

The Travis folks kindly bumped our build timeout limit so we can run the
full upstream Travis checks. I've manually tested Linux in all of the
relevant machines, including SMP in the RISC-V virt machine, along with
embedded binaries for the SiFive E series MCU. We test 'sifive_e' with MCU
samples from SiFive's Freedom E SDK. the Freedom U SDK has a
Linux buildroot setup for testing the 'virt' machine. There is additional
documentation on the wiki, such as links to the Fedora images that Richard
W. M. Jones et al have been working on.

- https://github.com/sifive/freedom-e-sdk/
- https://github.com/sifive/freedom-u-sdk/
- https://github.com/riscv/riscv-qemu/wiki

Hopefully, this PR gets merged...

On Wed, Mar 7, 2018 at 8:46 AM, Michael Clark  wrote:

> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA1
>
> The following changes since commit f32408f3b472a088467474ab152be3
> b6285b2d7b:
>
>   misc: don't use hwaddr as a type in trace events (2018-03-06 14:24:30
> +)
>
> are available in the git repository at:
>
>   https://github.com/riscv/riscv-qemu.git tags/riscv-qemu-upstream-v8.2
>
> for you to fetch changes up to 7051b081bf6796e5e84406f6223a7c4900bf7298:
>
>   RISC-V - Remove support for adhoc non-standard X_COP local-interrupt
> (2018-03-07 08:36:03 +1300)
>
> - 
> QEMU RISC-V Emulation Support (RV64GC, RV32GC)
>
> This release renames the SiFive machines to sifive_e and sifive_u
> to represent the SiFive Everywhere and SiFive Unleashed platforms.
> SiFive has configurable soft-core IP, so it is intended that these
> machines will be extended to enable a variety of SiFive IP blocks.
> The CPU definition infrastructure has been improved and there are
> now vendor CPU modules including the SiFiVe E31, E51, U34 and U54
> cores. The emulation accuracy for the E series has been improved
> by disabling the MMU for the E series. S mode has been disabled on
> cores that only support M mode and U mode. The two Spike machines
> that support two privileged ISA versions have been coalesced into
> one file. This series has Signed-off-by from the core contributors.
>
> *** Known Issues ***
>
> * Disassembler has some checkpatch warnings for the sake of code brevity
> * scripts/qemu-binfmt-conf.sh has checkpatch warnings due to line length
> * PMP (Physical Memory Protection) is as-of-yet unused and needs testing
>
> *** Changelog ***
>
> v8.2
>
> * Rebase
>
> v8.1
>
> * Fix missed case of renaming spike_v1.9 to spike_v1.9.1
>
> v8
>
> * Added linux-user/riscv/target_elf.h during rebase
> * Make resetvec configurable and clear mpp and mie on reset
> * Use SiFive E31, E51, U34 and U54 cores in SiFive machines
> * Define SiFive E31, E51, U34 and U54 cores
> * Refactor CPU core definition in preparation for vendor cores
> * Prevent S or U mode unless S or U extensions are present
> * SiFive E Series cores have no MMU
> * SiFive E Series cores have U mode
> * Make privileged ISA v1.10 implicit in CPU types
> * Remove DRAM_BASE and EXT_IO_BASE as they vary by machine
> * Correctly handle mtvec and stvec alignment with respect to RVC
> * Print more machine mode state in riscv_cpu_dump_state
> * Make riscv_isa_string use compact extension order method
> * Fix bug introduced in v6 RISCV_CPU_TYPE_NAME macro change
> * Parameterize spike v1.9.1 config string
> * Coalesce spike_v1.9.1 and spike_v1.10 machines
> * Rename sifive_e300 to sifive_e, and sifive_u500 to sifive_u
>
> v7
>
> * Make spike_v1.10 the default machine
> * Rename spike_v1.9 to spike_v1.9.1 to match privileged spec version
> * Remove empty target/riscv/trace-events file
> * Monitor ROM 32-bit reset code needs to be target endian
> * Add TARGET_TIOCGPTPEER to linux-user/riscv/termbits.h
> * Add -initrd support to the virt board
> * Fix naming in spike machine interface header
> * Update copyright notice on RISC-V Spike machines
> * Update copyright notice on RISC-V HTIF Console device
> * Change CPU Core and translator to GPLv2+
> * Change RISC-V Disassembler to GPLv2+
> * Change SiFive Test Finisher to GPLv2+
> * Change SiFive CLINT to GPLv2+
> * Change SiFive PRCI to GPLv2+
> * Change SiFive PLIC to GPLv2+
> * Change RISC-V spike machines to GPLv2+
> * Change RISC-V virt machine to GPLv2+
> * Change SiFive E300 machine to GPLv2+
> * Change SiFive U500 machine to GPLv2+
> * Change RISC-V Hart Array to GPLv2+
> * Change RISC-V HTIF device to GPLv2+
> * Change SiFiveUART device to GPLv2+
>
> v6
>
> * Drop IEEE 754-201x minimumNumber/maximumNumber for fmin/fmax
> * Remove some unnecessary commented debug statements
> * Change RISCV_CPU_TYPE_NAME to use riscv-cpu suffix
> * Define all CPU variants for linux-user
> * qemu_log calls require trailing \n
> * Replace PLIC printfs with qemu_log
> * Tear out unused HTIF code and eliminate shouting debug messages
> * Fix 

[Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Michael Clark]

-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1

The following changes since commit f32408f3b472a088467474ab152be3b6285b2d7b:

  misc: don't use hwaddr as a type in trace events (2018-03-06 14:24:30 +)

are available in the git repository at:

  https://github.com/riscv/riscv-qemu.git tags/riscv-qemu-upstream-v8.2

for you to fetch changes up to 7051b081bf6796e5e84406f6223a7c4900bf7298:

  RISC-V - Remove support for adhoc non-standard X_COP local-interrupt 
(2018-03-07 08:36:03 +1300)

- 
QEMU RISC-V Emulation Support (RV64GC, RV32GC)

This release renames the SiFive machines to sifive_e and sifive_u
to represent the SiFive Everywhere and SiFive Unleashed platforms.
SiFive has configurable soft-core IP, so it is intended that these
machines will be extended to enable a variety of SiFive IP blocks.
The CPU definition infrastructure has been improved and there are
now vendor CPU modules including the SiFiVe E31, E51, U34 and U54
cores. The emulation accuracy for the E series has been improved
by disabling the MMU for the E series. S mode has been disabled on
cores that only support M mode and U mode. The two Spike machines
that support two privileged ISA versions have been coalesced into
one file. This series has Signed-off-by from the core contributors.

*** Known Issues ***

* Disassembler has some checkpatch warnings for the sake of code brevity
* scripts/qemu-binfmt-conf.sh has checkpatch warnings due to line length
* PMP (Physical Memory Protection) is as-of-yet unused and needs testing

*** Changelog ***

v8.2

* Rebase

v8.1

* Fix missed case of renaming spike_v1.9 to spike_v1.9.1

v8

* Added linux-user/riscv/target_elf.h during rebase
* Make resetvec configurable and clear mpp and mie on reset
* Use SiFive E31, E51, U34 and U54 cores in SiFive machines
* Define SiFive E31, E51, U34 and U54 cores
* Refactor CPU core definition in preparation for vendor cores
* Prevent S or U mode unless S or U extensions are present
* SiFive E Series cores have no MMU
* SiFive E Series cores have U mode
* Make privileged ISA v1.10 implicit in CPU types
* Remove DRAM_BASE and EXT_IO_BASE as they vary by machine
* Correctly handle mtvec and stvec alignment with respect to RVC
* Print more machine mode state in riscv_cpu_dump_state
* Make riscv_isa_string use compact extension order method
* Fix bug introduced in v6 RISCV_CPU_TYPE_NAME macro change
* Parameterize spike v1.9.1 config string
* Coalesce spike_v1.9.1 and spike_v1.10 machines
* Rename sifive_e300 to sifive_e, and sifive_u500 to sifive_u

v7

* Make spike_v1.10 the default machine
* Rename spike_v1.9 to spike_v1.9.1 to match privileged spec version
* Remove empty target/riscv/trace-events file
* Monitor ROM 32-bit reset code needs to be target endian
* Add TARGET_TIOCGPTPEER to linux-user/riscv/termbits.h
* Add -initrd support to the virt board
* Fix naming in spike machine interface header
* Update copyright notice on RISC-V Spike machines
* Update copyright notice on RISC-V HTIF Console device
* Change CPU Core and translator to GPLv2+
* Change RISC-V Disassembler to GPLv2+
* Change SiFive Test Finisher to GPLv2+
* Change SiFive CLINT to GPLv2+
* Change SiFive PRCI to GPLv2+
* Change SiFive PLIC to GPLv2+
* Change RISC-V spike machines to GPLv2+
* Change RISC-V virt machine to GPLv2+
* Change SiFive E300 machine to GPLv2+
* Change SiFive U500 machine to GPLv2+
* Change RISC-V Hart Array to GPLv2+
* Change RISC-V HTIF device to GPLv2+
* Change SiFiveUART device to GPLv2+

v6

* Drop IEEE 754-201x minimumNumber/maximumNumber for fmin/fmax
* Remove some unnecessary commented debug statements
* Change RISCV_CPU_TYPE_NAME to use riscv-cpu suffix
* Define all CPU variants for linux-user
* qemu_log calls require trailing \n
* Replace PLIC printfs with qemu_log
* Tear out unused HTIF code and eliminate shouting debug messages
* Fix illegal instruction when sfence.vma is passed (rs2) arguments
* Make updates to PTE accessed and dirty bits atomic
* Only require atomic PTE updates on MTTCG enabled guests
* Page fault if accessed or dirty bits can't be updated
* Fix get_physical_address PTE reads and writes on riscv32
* Remove erroneous comments from the PLIC
* Default enable MTTCG
* Make WFI less conservative
* Unify local interrupt handling
* Expunge HTIF interrupts
* Always access mstatus.mip under a lock
* Don't implement rdtime/rdtimeh in system mode (bbl emulates them)
* Implement insreth/cycleh for rv32 and always enable user-mode counters
* Add GDB stub support for reading and writing CSRs
* Rename ENABLE_CHARDEV #ifdef from HTIF code
* Replace bad HTIF ELF code with load_elf symbol callback
* Convert chained if else fault handlers to switch statements
* Use RISCV exception codes for linux-user page faults

v5

* Implement NaN-boxing for flw, set high order bits to 1
* Use float_muladd_negate_* flags to floatXX_muladd
* Use IEEE 754-201x minimumNumber/maximumNumber for fmin/fmax
* Fix