Re: [Qemu-devel] [V15 3/4] hw/i386: Introduce AMD IOMMU

On Fri, Aug 12, 2016 at 10:10 PM, Valentine Sinitsyn < valentine.sinit...@gmail.com> wrote: > Hi David, > > On 02.08.2016 13:39, David Kiarie wrote: > >> Add AMD IOMMU emulaton to Qemu in addition to Intel IOMMU. >> The IOMMU does basic translation, error checking and has a >> minimal IOTLB

Re: [Qemu-devel] [V15 3/4] hw/i386: Introduce AMD IOMMU

On 13.08.2016 00:40, David Kiarie wrote: On Fri, Aug 12, 2016 at 10:10 PM, Valentine Sinitsyn > wrote: Hi David, On 02.08.2016 13:39, David Kiarie wrote: Add AMD IOMMU emulaton to Qemu in addition to Intel

Re: [Qemu-devel] [V15 3/4] hw/i386: Introduce AMD IOMMU

Hi David, On 02.08.2016 13:39, David Kiarie wrote: Add AMD IOMMU emulaton to Qemu in addition to Intel IOMMU. The IOMMU does basic translation, error checking and has a minimal IOTLB implementation. This IOMMU bypassed the need for target aborts by responding with IOMMU_NONE access rights and

Re: [Qemu-devel] [V15 3/4] hw/i386: Introduce AMD IOMMU

On 11.08.2016 13:32, David Kiarie wrote: On Thu, Aug 11, 2016 at 11:23 AM, Valentine Sinitsyn > wrote: Hi, On 02.08.2016 13:39, David Kiarie wrote: +static void amdvi_writeq_raw(AMDVIState *s, uint64_t

Re: [Qemu-devel] [V15 3/4] hw/i386: Introduce AMD IOMMU

On Thu, Aug 11, 2016 at 11:23 AM, Valentine Sinitsyn < valentine.sinit...@gmail.com> wrote: > Hi, > > > On 02.08.2016 13:39, David Kiarie wrote: > >> +static void amdvi_writeq_raw(AMDVIState *s, uint64_t val, hwaddr addr) >> +{+ >> +static void amdvi_generate_msi_interrupt(AMDVIState *s) >> +{ >>

Re: [Qemu-devel] [V15 3/4] hw/i386: Introduce AMD IOMMU

Hi, On 02.08.2016 13:39, David Kiarie wrote: Add AMD IOMMU emulaton to Qemu in addition to Intel IOMMU. The IOMMU does basic translation, error checking and has a minimal IOTLB implementation. This IOMMU bypassed the need for target aborts by responding with IOMMU_NONE access rights and exempts

Re: [Qemu-devel] [V15 3/4] hw/i386: Introduce AMD IOMMU

On Wed, Aug 10, 2016 at 5:08 AM, Peter Xu wrote: > On Tue, Aug 09, 2016 at 03:52:07PM +0300, David Kiarie wrote: > > [...] > > > > > +if (dma_memory_write(_space_memory, s->evtlog_len + > > > s->evtlog_tail, > > > > +, AMDVI_EVENT_LEN)) { > > > > > > Check with

Re: [Qemu-devel] [V15 3/4] hw/i386: Introduce AMD IOMMU

On Tue, Aug 09, 2016 at 03:52:07PM +0300, David Kiarie wrote: [...] > > > +if (dma_memory_write(_space_memory, s->evtlog_len + > > s->evtlog_tail, > > > +, AMDVI_EVENT_LEN)) { > > > > Check with MEMTX_OK? > > > > I'm not sure what exactly you mean here. I mean we have return code

Re: [Qemu-devel] [V15 3/4] hw/i386: Introduce AMD IOMMU

On Tue, Aug 09, 2016 at 08:46:09PM +0300, David Kiarie wrote: > On Tue, Aug 9, 2016 at 8:44 AM, Peter Xu wrote: > > > On Tue, Aug 02, 2016 at 11:39:06AM +0300, David Kiarie wrote: > > > > [...] > > > > > +/* external write */ > > > +static void amdvi_writew(AMDVIState *s,

[Qemu-devel] [V15 3/4] hw/i386: Introduce AMD IOMMU

Add AMD IOMMU emulaton to Qemu in addition to Intel IOMMU. The IOMMU does basic translation, error checking and has a minimal IOTLB implementation. This IOMMU bypassed the need for target aborts by responding with IOMMU_NONE access rights and exempts the region 0xfee0-0xfeef from

Re: [Qemu-devel] [V15 3/4] hw/i386: Introduce AMD IOMMU

On Tue, Aug 9, 2016 at 8:44 AM, Peter Xu wrote: > On Tue, Aug 02, 2016 at 11:39:06AM +0300, David Kiarie wrote: > > [...] > > > +/* external write */ > > +static void amdvi_writew(AMDVIState *s, hwaddr addr, uint16_t val) > > +{ > > +uint16_t romask =

Re: [Qemu-devel] [V15 3/4] hw/i386: Introduce AMD IOMMU

On Tue, Aug 9, 2016 at 4:01 PM, Valentine Sinitsyn < valentine.sinit...@gmail.com> wrote: > Hi all, > > On 09.08.2016 17:52, David Kiarie wrote: > >> >> >> On Tue, Aug 9, 2016 at 8:44 AM, Peter Xu > > wrote: >> >> On Tue, Aug 02, 2016 at

Re: [Qemu-devel] [V15 3/4] hw/i386: Introduce AMD IOMMU

Hi all, On 09.08.2016 17:52, David Kiarie wrote: On Tue, Aug 9, 2016 at 8:44 AM, Peter Xu > wrote: On Tue, Aug 02, 2016 at 11:39:06AM +0300, David Kiarie wrote: [...] > +/* invalidate internal caches for devid */ > +typedef

Re: [Qemu-devel] [V15 3/4] hw/i386: Introduce AMD IOMMU

On Tue, Aug 9, 2016 at 8:44 AM, Peter Xu wrote: > On Tue, Aug 02, 2016 at 11:39:06AM +0300, David Kiarie wrote: > > [...] > > > +/* invalidate internal caches for devid */ > > +typedef struct QEMU_PACKED { > > +#ifdef HOST_WORDS_BIGENDIAN > > +uint64_t devid;

Re: [Qemu-devel] [V15 3/4] hw/i386: Introduce AMD IOMMU

On Tue, Aug 09, 2016 at 03:07:43PM +0300, David Kiarie wrote: > On Tue, Aug 9, 2016 at 8:44 AM, Peter Xu wrote: > > > On Tue, Aug 02, 2016 at 11:39:06AM +0300, David Kiarie wrote: > > > > [...] > > > > > Hi Peter. > > Most of your comments are valid thought some are

Re: [Qemu-devel] [V15 3/4] hw/i386: Introduce AMD IOMMU

On Tue, Aug 9, 2016 at 8:44 AM, Peter Xu wrote: > On Tue, Aug 02, 2016 at 11:39:06AM +0300, David Kiarie wrote: > > [...] > > Hi Peter. Most of your comments are valid thought some are subjective :-). I'm covering most if not all of them on next version (should coming

Re: [Qemu-devel] [V15 3/4] hw/i386: Introduce AMD IOMMU

On Tue, Aug 02, 2016 at 11:39:06AM +0300, David Kiarie wrote: [...] > +/* invalidate internal caches for devid */ > +typedef struct QEMU_PACKED { > +#ifdef HOST_WORDS_BIGENDIAN > +uint64_t devid;/* device to invalidate */ > +uint64_t reserved_1:44; > +uint64_t

[Qemu-devel] [V15 3/4] hw/i386: Introduce AMD IOMMU

Add AMD IOMMU emulaton to Qemu in addition to Intel IOMMU. The IOMMU does basic translation, error checking and has a minimal IOTLB implementation. This IOMMU bypassed the need for target aborts by responding with IOMMU_NONE access rights and exempts the region 0xfee0-0xfeef from