Il 05/12/2013 23:59, H. Peter Anvin ha scritto:
Hi, I'm currently reviewing internally another set of patches for MPX
support which would at least in part conflict with these. I don't see
the rest of the series -- where was it posted?
It was posted to kvm-devel and not threaded. :(
Paolo
Hi,
Now the advice given was to have virtio-vga wrap virtio-gpu-base but
from what I can see it really can't. Since it needs to act and look
like a PCI device
Oops, yes. VirtIOPCIProxy wasn't on my radar. That makes things a bit
more messy. Can you just push what you have now somewhere?
On 12/06/2013 01:38 AM, Paolo Bonzini wrote:
Il 05/12/2013 17:17, Marcelo Tosatti ha scritto:
I agree it is a bit ugly, but in my testing QEMU seemed to loop over all
the VCPUS fast enough for the kernel side kvm_write_tsc() to do a
reasonable job of matching the offsets (the Linux guest did
VCPU TSC is not cleared by a warm reset (*), which leaves some types of Linux
guests (non-pvops guests and those with the kernel parameter no-kvmclock set)
vulnerable to the overflow in cyc2ns_offset fixed by upstream commit
9993bc635d01a6ee7f6b833b4ee65ce7c06350b1 (sched/x86: Fix overflow in
Il 06/12/2013 09:24, Fernando Luis Vázquez Cao ha scritto:
Could we start with the patch that I already sent? It's been
tested, it is conservative in the sense that it does the minimum
necessary to fix an existing bug, and should be easy to
backport. I will be replying to this email with an
Newer kernels are capable of synchronizing TSC values of multiple VCPUs
on writeback, but we were excluding the power up case, which is not needed
anymore.
Signed-off-by: Fernando Luis Vazquez Cao ferna...@oss.ntt.co.jp
---
diff -urNp qemu-orig/target-i386/kvm.c qemu/target-i386/kvm.c
---
On 12/06/2013 05:36 PM, Paolo Bonzini wrote:
Il 06/12/2013 09:24, Fernando Luis Vázquez Cao ha scritto:
Could we start with the patch that I already sent? It's been
tested, it is conservative in the sense that it does the minimum
necessary to fix an existing bug, and should be easy to
backport.
On Fri, Dec 6, 2013 at 6:24 PM, Gerd Hoffmann kra...@redhat.com wrote:
Hi,
Now the advice given was to have virtio-vga wrap virtio-gpu-base but
from what I can see it really can't. Since it needs to act and look
like a PCI device
Oops, yes. VirtIOPCIProxy wasn't on my radar. That makes
On Thu, Dec 05, 2013 at 11:34:28AM +0100, Paolo Bonzini wrote:
Il 05/12/2013 10:24, Stefan Hajnoczi ha scritto:
That's what already happens actually. vring_push has
+g_slice_free(VirtQueueElement, elem);
+
/* Don't touch vring if a fatal error occurred */
Il 06/12/2013 09:56, Fernando Luis Vázquez Cao ha scritto:
I will also be sending a patch that makes the TSC writeback
unconditional, but this one should probably be kept on hold
until it is properly tested.
If you test it, I can drop the if myself from your patch.
Unfortunately I will
On Thu, Dec 05, 2013 at 10:12:00AM -0600, Will Drewry wrote:
On Thu, Dec 5, 2013 at 7:15 AM, Stefan Hajnoczi stefa...@gmail.com wrote:
On Wed, Dec 04, 2013 at 11:21:12AM -0200, Eduardo Otubo wrote:
On 12/04/2013 07:39 AM, Stefan Hajnoczi wrote:
On Fri, Nov 22, 2013 at 11:00:24AM -0500, Paul
On 2013年12月06日 18:08, Paolo Bonzini wrote:
Il 06/12/2013 09:56, Fernando Luis Vázquez Cao ha scritto:
I will also be sending a patch that makes the TSC writeback
unconditional, but this one should probably be kept on hold
until it is properly tested.
If you test it, I can drop the if myself
Il 04/12/2013 08:58, Wanlong Gao ha scritto:
As you know, QEMU can't direct it's memory allocation now, this may cause
guest cross node access performance regression.
And, the worse thing is that if PCI-passthrough is used,
direct-attached-device uses DMA transfer between device and qemu
On Thu, Dec 05, 2013 at 02:48:12AM -0800, Xin Tong wrote:
I am wondering whether it is possible to propose project in QEMU google
summer of code as a student ? I have some ideas regarding TLB emulation in
system mode and would like to find a mentor to do a gsoc for it.
Hi,
Please email
On 12/06/2013 05:06 PM, Paolo Bonzini wrote:
I think patches 1-4 and 7 are fine. For the rest, I'd rather wait for
Igor's patches and try to integrate with Igor's memory hotplug patches.
So, how about apply them first and then I can help Igor to rebase my
remaining patches for him?
Thanks,
Hi,
Here we go. Update seabios to pre-1.7.4 snapshot so we get some
testing for the 1.7.4 freeze. Update to final 1.7.4 most likely
later this year.
please pull,
Gerd
The following changes since commit 7dc65c02fe3fb8f3146ce0b9ff5fec5945329f0e:
Open 2.0 development tree (2013-11-27
Adding xhci support to seabios made it jump over the 128k line.
Changing the bios size breaks migration, so we have to keep a
128k seabios binary for old machine types. New machine types can
use a large 256k bios which should be big enougth for a while.
This patch updates the seabios build
Updates seabios to git master snapshot. seabios is in freeze now,
update to final 1.7.4 will follow later this year.
Summary of major changes:
* Support for acpi table loading from qemu.
* Support for the xhci host adapter.
* Support for the pvscsi HBA.
* Various minor bug fixes.
* Lots of
r...@twiddle.net writes:
On 12/06/2013 10:51 AM, Peter Maydell wrote:
+if (invert) {
+tcg_gen_not_i64(tcg_rm, tcg_rm);
+}
+
+tcg_rd = cpu_reg(s, rd);
+tcg_rn = cpu_reg(s, rn);
+
+switch (opc) {
+case 0: /* AND, BIC */
+case 3: /* ANDS, BICS */
+
Signed-off-by: Gerd Hoffmann kra...@redhat.com
---
roms/Makefile | 2 ++
1 file changed, 2 insertions(+)
diff --git a/roms/Makefile b/roms/Makefile
index fc716c1..1e04669 100644
--- a/roms/Makefile
+++ b/roms/Makefile
@@ -73,9 +73,11 @@ build-seabios-config-%: config.%
mkdir -p
This patch adds firmware to the machine options. -bios file becomes a
shortcut for -machine firmware=file. Advantage is that the firmware
can be specified via config file as -machine is parsed using QemuOpts
and it is also possible to use different defaults for different
machine types (via
Signed-off-by: Gerd Hoffmann kra...@redhat.com
---
hw/i386/pc_piix.c | 14 --
hw/i386/pc_q35.c | 11 ++-
2 files changed, 22 insertions(+), 3 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 2111f01..9329f04 100644
--- a/hw/i386/pc_piix.c
+++
Signed-off-by: Gerd Hoffmann kra...@redhat.com
---
hw/i386/pc_piix.c | 4 +++-
hw/i386/pc_q35.c | 4 +++-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 9329f04..ab56285 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -339,7
Il 04/12/2013 08:58, Wanlong Gao ha scritto:
According to this patch set, we are able to set guest nodes memory policy
like following:
-numa node,nodeid=0,cpus=0, \
-numa mem,size=1024M,policy=membind,host-nodes=0-1 \
-numa node,nodeid=1,cpus=1 \
-numa
Il 06/12/2013 10:31, Wanlong Gao ha scritto:
I think patches 1-4 and 7 are fine. For the rest, I'd rather wait for
Igor's patches and try to integrate with Igor's memory hotplug patches.
So, how about apply them first and then I can help Igor to rebase my
remaining patches for him?
Yes.
Am 05.12.2013 um 18:41 hat Max Reitz geschrieben:
When trying to implement this, I hit the problem that BlockdevRef
allows you to reference an existing block device; however, this
seems currently unimplemented. This is further hindered by the fact
how this reference is done: If you want to
Am 05.12.2013 um 19:35 hat Max Reitz geschrieben:
On 05.12.2013 18:41, Max Reitz wrote:
[…]
Second, if specifying a reference to an existing device should
really be supported, bdrv_open() should ideally not call
bdrv_file_open() anymore, but a function bdrv_find_ref() instead
which
Stefan Hajnoczi stefa...@redhat.com writes:
After starting the QEMU process and initializing the QMP connection, we
can read the pid file and unlink it.
Just stash away the pid instead of the pid filename. This way we can
avoid pid file leaks since running tests may abort(3) without
On 06.12.2013 11:43, Kevin Wolf wrote:
Am 05.12.2013 um 18:41 hat Max Reitz geschrieben:
When trying to implement this, I hit the problem that BlockdevRef
allows you to reference an existing block device; however, this
seems currently unimplemented. This is further hindered by the fact
how this
On 06.12.2013 11:45, Kevin Wolf wrote:
Am 05.12.2013 um 19:35 hat Max Reitz geschrieben:
On 05.12.2013 18:41, Max Reitz wrote:
[…]
Second, if specifying a reference to an existing device should
really be supported, bdrv_open() should ideally not call
bdrv_file_open() anymore, but a function
Stefan Hajnoczi stefa...@redhat.com writes:
GLib uses abort(3) to exit failed test cases. As a result, the pid file and
UNIX domain sockets for a running test are leaked upon failure.
Since abort(3) does not call atexit(3) handler functions, we could set up a
SIGABRT handler that performs
On 06.12.2013 12:00, Max Reitz wrote:
On 06.12.2013 11:43, Kevin Wolf wrote:
Am 05.12.2013 um 18:41 hat Max Reitz geschrieben:
When trying to implement this, I hit the problem that BlockdevRef
allows you to reference an existing block device; however, this
seems currently unimplemented. This
On 06.12.2013 12:14, Max Reitz wrote:
On 06.12.2013 12:00, Max Reitz wrote:
On 06.12.2013 11:43, Kevin Wolf wrote:
Am 05.12.2013 um 18:41 hat Max Reitz geschrieben:
When trying to implement this, I hit the problem that BlockdevRef
allows you to reference an existing block device; however,
Paolo Bonzini pbonz...@redhat.com writes:
Il 05/12/2013 13:42, Alexey Kardashevskiy ha scritto:
Thanks!
Just out of curiosity. A lot (in fact, all around me) dvd drives do not
support trayclose as they are in laptops or servers (which use the same
laptop models). I cannot even verify how
qemu uses pci as name for pci bridges in the firmware device path.
seabios expects pci-bridge. Result is that bootorder is broken for
devices behind pci bridges.
Some googling suggests that pci-bridge is the correct one. At least
PPC-based Apple machines are using this. See question How do I
Eric Blake ebl...@redhat.com writes:
On 12/05/2013 03:13 AM, Markus Armbruster wrote:
For error_propagate, if the destination error is error_abort, then
the abort happens at propagation time.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
changed since v1:
Delayed
On Fri, Dec 6, 2013 at 9:59 PM, Markus Armbruster arm...@redhat.com wrote:
Eric Blake ebl...@redhat.com writes:
On 12/05/2013 03:13 AM, Markus Armbruster wrote:
For error_propagate, if the destination error is error_abort, then
the abort happens at propagation time.
Signed-off-by: Peter
On 5 December 2013 22:26, Richard Henderson r...@twiddle.net wrote:
On 12/06/2013 10:51 AM, Peter Maydell wrote:
+if (cond = 0x0e) { /* condition always */
+tcg_src = read_cpu_reg(s, rn, sf);
+tcg_gen_mov_i64(tcg_rd, tcg_src);
I wonder if it's worth adding that 0x0[ef]
When we're running in non-64bit mode with qemu-system-x86_64 we can
still end up with virtual addresses that are above the 32bit boundary
if a segment offset is set up.
GNU Hurd does exactly that. It sets the segment offset to 0x8000 and
puts its EIP value to 0x8xxx to access low memory.
Peter Crosthwaite peter.crosthwa...@xilinx.com writes:
On Fri, Dec 6, 2013 at 9:59 PM, Markus Armbruster arm...@redhat.com wrote:
Eric Blake ebl...@redhat.com writes:
On 12/05/2013 03:13 AM, Markus Armbruster wrote:
For error_propagate, if the destination error is error_abort, then
the
From: Alexander Graf ag...@suse.de
Add support for the instructions described in C3.5.10 Logical
(shifted register).
We store the flags in the same locations as the 32 bit decoder.
This is slightly awkward when calculating 64 bit results, but seems
a better tradeoff than having to rework the
From: Alexander Graf ag...@suse.de
This adds 2-src variable shift register instructions:
C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV
Signed-off-by: Alexander Graf ag...@suse.de
[claudio: adapted to new decoder, use enums for shift types]
Signed-off-by: Claudio Fontana
From: Alexander Graf ag...@suse.de
This adds support for the C5.6.147 RBIT instruction.
Signed-off-by: Alexander Graf ag...@suse.de
[claudio: adapted to new decoder, use bswap64,
make RBIT part standalone from the rest of the patch,
splitting REV into a separate patch]
On Sat, Dec 07, 2013 at 02:52:54AM +0800, Qiaowei Ren wrote:
This patch adds the Documentation/intel_mpx.txt file with some
information about Intel MPX.
Signed-off-by: Qiaowei Ren qiaowei@intel.com
Signed-off-by: Xudong Hao xudong@intel.com
Signed-off-by: Liu Jinsong
From: Alexander Graf ag...@suse.de
This patch adds emulation support for the EXTR instruction.
Signed-off-by: Alexander Graf ag...@suse.de
[claudio: adapted for new decoder, removed a few temporaries,
fixed the 32bit bug, added checks for more
unallocated cases]
From: Alexander Graf ag...@suse.de
This patch adds support for decoding 2-src data processing insns,
and the first users, UDIV and SDIV.
Signed-off-by: Alexander Graf ag...@suse.de
[claudio: adapted to new decoder adding the 2-src decoding level,
always zero-extend result in 32bit
From: Claudio Fontana claudio.font...@linaro.org
This patch adds support for the instruction group C3.5.6
Conditional select: CSEL, CSINC, CSINV, CSNEG.
Signed-off-by: Claudio Fontana claudio.font...@linaro.org
[PMM: Improved code generated in the nomatch case as per RTH suggestions]
From: Claudio Fontana claudio.font...@linaro.org
This patch implements the C3.4.2 Bitfield instructions:
SBFM, BFM, UBFM.
Signed-off-by: Claudio Fontana claudio.font...@linaro.org
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Richard Henderson r...@twiddle.net
---
From: Claudio Fontana claudio.font...@linaro.org
This patch adds support for decoding 1-src data processing insns,
and the first user, C5.6.40 CLZ (count leading zeroes).
Signed-off-by: Claudio Fontana claudio.font...@linaro.org
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by:
From: Claudio Fontana claudio.font...@linaro.org
this patch introduces wrappers for the clrsb builtins,
which count the leading redundant sign bits.
Signed-off-by: Claudio Fontana claudio.font...@linaro.org
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Richard Henderson
From: Claudio Fontana claudio.font...@linaro.org
This adds support for C5.6.149 REV, C5.6.151 REV32, C5.6.150 REV16.
Signed-off-by: Claudio Fontana claudio.font...@linaro.org
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Richard Henderson r...@twiddle.net
---
From: Alexander Graf ag...@suse.de
Add support for the instructions described in
C3.4.6 PC-rel. addressing (ADR and ADRP).
Signed-off-by: Alexander Graf ag...@suse.de
[claudio: adapted to new decoder structure]
Signed-off-by: Claudio Fontana claudio.font...@linaro.org
Reviewed-by: Richard
From: Alexander Graf ag...@suse.de
This patch adds support for C3.4.4 Logical (immediate),
which include AND, ANDS, ORR, EOR.
Signed-off-by: Alexander Graf ag...@suse.de
[claudio: adapted to new decoder, function renaming,
removed a TCG temp variable]
Signed-off-by: Claudio Fontana
Second revision of the second chunk of A64 decoder patches:
a grabbag of miscellaneous logic and bit-twiddling operations,
plus some other minor stuff like ADR and conditional-select.
Changes v1-v2:
* added a couple of OPTME comments as suggested by RTH
* lowercased stray TRUE/FALSE
* in
From: Claudio Fontana claudio.font...@linaro.org
this patch adds support for the CLS instruction.
Signed-off-by: Claudio Fontana claudio.font...@linaro.org
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-arm/helper-a64.c| 10
On Sat, Dec 07, 2013 at 02:52:55AM +0800, Qiaowei Ren wrote:
Signed-off-by: Qiaowei Ren qiaowei@intel.com
Signed-off-by: Xudong Hao xudong@intel.com
Signed-off-by: Liu Jinsong jinsong@intel.com
---
arch/x86/include/asm/cpufeature.h |2 ++
1 files changed, 2 insertions(+),
On Sat, Dec 07, 2013 at 02:52:56AM +0800, Qiaowei Ren wrote:
Commit message please.
Signed-off-by: Qiaowei Ren qiaowei@intel.com
Signed-off-by: Xudong Hao xudong@intel.com
Signed-off-by: Liu Jinsong jinsong@intel.com
---
arch/x86/include/asm/processor.h | 23
On Tue, 3 Dec 2013 13:00:15 +0100
Paolo Bonzini pbonz...@redhat.com wrote:
This fixes an abort if you invoke the migrate command while the
guest is being debugged.
Cc: qemu-sta...@nongnu.org
Cc: lcapitul...@redhat.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
Applied to the qmp
On Thu, 05 Dec 2013 18:49:15 -0700
Lin Ma l...@suse.com wrote:
In qemu-1.4.x, When performing migrate_cancel on hmp, Sometimes
s-state is incorrrectly saved to MIG_STATE_ERROR instead of
MIG_STATE_CANCELLED.
If the migrate_fd_cancel in main thread is scheduled to run before
the thread
Intel has released Memory Protection Extensions (MPX) recently.
Please refer to
http://download-software.intel.com/sites/default/files/319433-015.pdf
These 2 patches are version2 to support Intel MPX at qemu side.
Version 1:
* Fix cpuid leaf 0x0d bug which incorrectly parsed eax and ebx;
*
On 3 December 2013 07:00, Peter Crosthwaite
peter.crosthwa...@xilinx.com wrote:
Some processors (notably A9 within Highbank) define and use the
CP15 configuration base address (CBAR). This is vendor specific
so its best implemented as a CPU property (otherwise we would need
vendor specific
From ee8b72df3b5503514b748035e6b1cb4d61f8e701 Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Thu, 5 Dec 2013 08:32:12 +0800
Subject: [PATCH v3 1/2] target-i386: Intel MPX
Add some MPX related definiation, and hardcode sizes and offsets
of xsave features 3 and 4. It also
From 12fa3564b7342c4e034b13671dc922ff23ac4b1e Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Sat, 7 Dec 2013 05:18:35 +0800
Subject: [PATCH v3 2/2] target-i386: MSR_IA32_BNDCFGS handle
Signed-off-by: Liu Jinsong jinsong@intel.com
---
target-i386/cpu.h |3 +++
On Fri, Dec 06, 2013 at 05:24:18PM +0900, Fernando Luis Vázquez Cao wrote:
On 12/06/2013 01:38 AM, Paolo Bonzini wrote:
Il 05/12/2013 17:17, Marcelo Tosatti ha scritto:
I agree it is a bit ugly, but in my testing QEMU seemed to loop over all
the VCPUS fast enough for the kernel side
On Thu, 5 Dec 2013 18:15:00 +0100
Benoît Canet ben...@irqsave.net wrote:
--- a/qapi-schema.json
+++ b/qapi-schema.json
@@ -1675,7 +1675,11 @@
# determine which ones are encrypted, set the passwords with this command,
and
# then start the guest with the @cont command.
#
-# @device:
Paolo Bonzini wrote:
Il 02/12/2013 17:46, Liu, Jinsong ha scritto:
From e9ba40b3d1820b8ab31431c73226ee3ed485edd1 Mon Sep 17 00:00:00
2001
From: Liu Jinsong jinsong@intel.com
Date: Tue, 3 Dec 2013 07:02:27 +0800
Subject: [PATCH 3/4] KVM/X86: Intel MPX vmx and msr handle
Signed-off-by:
This patch adds the Documentation/intel_mpx.txt file with some
information about Intel MPX.
Signed-off-by: Qiaowei Ren qiaowei@intel.com
Signed-off-by: Xudong Hao xudong@intel.com
Signed-off-by: Liu Jinsong jinsong@intel.com
---
Documentation/intel_mpx.txt | 77
On 3 December 2013 07:00, Peter Crosthwaite
peter.crosthwa...@xilinx.com wrote:
The cp15.c15 space is implementation defined. Currently there is a
dummy placeholder register RAZing it. Allow overriding of this RAZ
so implementations of specific registers can take precedence.
Signed-off-by:
Signed-off-by: Qiaowei Ren qiaowei@intel.com
Signed-off-by: Xudong Hao xudong@intel.com
Signed-off-by: Liu Jinsong jinsong@intel.com
---
arch/x86/include/asm/cpufeature.h |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/x86/include/asm/cpufeature.h
Signed-off-by: Qiaowei Ren qiaowei@intel.com
Signed-off-by: Xudong Hao xudong@intel.com
Signed-off-by: Liu Jinsong jinsong@intel.com
---
arch/x86/include/asm/processor.h | 23 +++
arch/x86/include/asm/xsave.h |6 +-
2 files changed, 28 insertions(+),
On 3 December 2013 07:01, Peter Crosthwaite
peter.crosthwa...@xilinx.com wrote:
The reset Value of the CP15 CBAR is a vendor (machine) configurable
no need to capitalize value here.
property. If ARM_FEATURE_CBAR is set, add it as a property at
post_init time.
Signed-off-by: Peter
On 3 December 2013 07:01, Peter Crosthwaite
peter.crosthwa...@xilinx.com wrote:
To allow the machine model to set device properties before CPU
realization.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
-- PMM
On 3 December 2013 07:02, Peter Crosthwaite
peter.crosthwa...@xilinx.com wrote:
Fix the CBAR initialisation by using the newly defined static property.
CBAR is now set before realization, so the intended value is now
actually used.
So I have kind of tested this. I booted an ARM kernel on
On 3 December 2013 07:02, Peter Crosthwaite
peter.crosthwa...@xilinx.com wrote:
To allow the machine model to set device properties before CPU
realization.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
-- PMM
On 3 December 2013 07:03, Peter Crosthwaite
peter.crosthwa...@xilinx.com wrote:
Fix the CBAR initialisation by using the newly defined static property.
Zynq will now correctly init the CBAR to the SCU base address.
Needed to boot Linux on the xilinx_zynq machine model.
Signed-off-by: Peter
This patch extends the frontend-backend interface so that it is possible
to pass a new flag (QEMU_NET_PACKET_FLAG_MORE) when sending a packet to the
other peer. The new flag acts as a hint for the receiving peer, which can
accumulate a batch of packets before forwarding those packets (to the host
On 3 December 2013 07:04, Peter Crosthwaite
peter.crosthwa...@xilinx.com wrote:
GIC_BASE_ADDR is not the base address of the GIC. Its clear from the
code that this is the base address of the MPCore. Rename to
MPCORE_PERIPHBASE accordingly.
Signed-off-by: Peter Crosthwaite
On 3 December 2013 13:19, Andreas Färber afaer...@suse.de wrote:
Am 03.12.2013 07:59, schrieb Peter Crosthwaite:
Currently the uintXX property adders make a read only property. This
is not useful for devices that want to create board (or container)
configurable dynamic device properties. Fix
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
qemu-options.hx |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/qemu-options.hx b/qemu-options.hx
index 8b94264..7f12f02 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -2089,7 +2089,7 @@ ETEXI
DEF(iscsi,
On 12/06/2013 07:06 AM, Liu, Jinsong wrote:
Intel has released Memory Protection Extensions (MPX) recently.
Please refer to
http://download-software.intel.com/sites/default/files/319433-015.pdf
These 2 patches are version2 to support Intel MPX at qemu side.
You still aren't threading
On 4 December 2013 05:53, Peter Crosthwaite
peter.crosthwa...@xilinx.com wrote:
Hi Peter,
This series updated cadence GEM (ethernet in Zynq) with a number of
bugfixes and enhancements. Most of this has come out of some stress
testing we have done internally.
I have also testing briefly
On 12/06/2013 07:27 AM, Luiz Capitulino wrote:
On Thu, 5 Dec 2013 18:15:00 +0100
Benoît Canet ben...@irqsave.net wrote:
-{ 'command': 'block_passwd', 'data': {'device': 'str', 'password': 'str'} }
+{ 'command': 'block_passwd', 'data': {'*device': 'str',
+
On 12/05/2013 10:14 AM, Benoît Canet wrote:
Signed-off-by: Benoit Canet ben...@irqsave.net
---
block.c | 44 +++-
1 file changed, 39 insertions(+), 5 deletions(-)
Reviewed-by: Eric Blake ebl...@redhat.com
--
Eric Blake eblake redhat com
On Fri, Dec 6, 2013 at 3:13 AM, Stefan Hajnoczi stefa...@gmail.com wrote:
On Thu, Dec 05, 2013 at 10:12:00AM -0600, Will Drewry wrote:
On Thu, Dec 5, 2013 at 7:15 AM, Stefan Hajnoczi stefa...@gmail.com wrote:
On Wed, Dec 04, 2013 at 11:21:12AM -0200, Eduardo Otubo wrote:
On 12/04/2013 07:39
Il 06/12/2013 15:06, Liu, Jinsong ha scritto:
Intel has released Memory Protection Extensions (MPX) recently.
Please refer to
http://download-software.intel.com/sites/default/files/319433-015.pdf
These 2 patches are version2 to support Intel MPX at qemu side.
Version 1:
* Fix cpuid leaf
-Original Message-
From: Borislav Petkov [mailto:b...@alien8.de]
Sent: Friday, December 06, 2013 9:27 PM
To: Ren, Qiaowei
Cc: Paolo Bonzini; H. Peter Anvin; Ingo Molnar; Thomas Gleixner;
x...@kernel.org; linux-ker...@vger.kernel.org; qemu-devel@nongnu.org;
k...@vger.kernel.org;
The following changes since commit 607bb022f2a44797cbf40e85e84da4134e2f0e01:
Update version for 1.7.0-rc1 release (2013-11-21 08:11:47 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/virt/kvm/qemu-kvm.git uq/master
Alex Williamson (1):
kvm: Query KVM for
From: Liu Jinsong jinsong@intel.com
Fix cpuid leaf 0x0d which incorrectly parsed eax and ebx.
However, before this patch the CPUID worked fine -- the .offset
field contained the size _and_ was stored in the register that
is supposed to hold the size (eax), and likewise the .size field
From: Marcelo Tosatti mtosa...@redhat.com
v4: s/fail/failed/ (Peter Maydell)
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
Signed-off-by: Marcelo Tosatti mtosa...@redhat.com
---
exec.c | 59 +++---
qemu-options.hx |2 -
vl.c
On Fri, Dec 06, 2013 at 03:55:10PM +, Ren, Qiaowei wrote:
It is from public introduction and specification, you can refer to
http://software.intel.com/en-us/articles/introduction-to-intel-memory-protection-extensions
Yep, saw it there too. Which doesn't make it any less strange :)
Btw, if
On 12/05/2013 10:14 AM, Benoît Canet wrote:
Signed-off-by: Benoit Canet ben...@irqsave.net
---
block.c | 16
blockdev.c| 5 +
include/block/block.h | 1 +
qapi-schema.json | 11 +++
qmp-commands.hx | 19 +++
No... we always ask for cpufeature.h patches separately because they sometimes
cause conflicts between branches.
Borislav Petkov b...@alien8.de wrote:
On Sat, Dec 07, 2013 at 02:52:55AM +0800, Qiaowei Ren wrote:
Signed-off-by: Qiaowei Ren qiaowei@intel.com
Signed-off-by: Xudong Hao
-Original Message-
From: Borislav Petkov [mailto:b...@alien8.de]
Sent: Friday, December 06, 2013 9:47 PM
To: Ren, Qiaowei
Cc: Paolo Bonzini; H. Peter Anvin; Ingo Molnar; Thomas Gleixner;
x...@kernel.org; linux-ker...@vger.kernel.org; qemu-devel@nongnu.org;
k...@vger.kernel.org;
-Original Message-
From: Borislav Petkov [mailto:b...@alien8.de]
Sent: Saturday, December 07, 2013 12:06 AM
To: Ren, Qiaowei
Cc: Paolo Bonzini; H. Peter Anvin; Ingo Molnar; Thomas Gleixner;
x...@kernel.org; linux-ker...@vger.kernel.org; qemu-devel@nongnu.org;
k...@vger.kernel.org;
Eric Blake wrote:
On 12/06/2013 07:06 AM, Liu, Jinsong wrote:
Intel has released Memory Protection Extensions (MPX) recently.
Please refer to
http://download-software.intel.com/sites/default/files/319433-015.pdf
These 2 patches are version2 to support Intel MPX at qemu side.
You still
Paolo Bonzini wrote:
Il 06/12/2013 15:06, Liu, Jinsong ha scritto:
Intel has released Memory Protection Extensions (MPX) recently.
Please refer to
http://download-software.intel.com/sites/default/files/319433-015.pdf
These 2 patches are version2 to support Intel MPX at qemu side.
Version
On top of Kevin's block pull request from last week that is still pending.
The following changes since commit 981cbf59b5360647e908186e7306ee9013a58c88:
qemu-iotests: Add sample image and test for VMDK version 3 (2013-11-29
17:41:14 +0100)
are available in the git repository at:
From: Paolo Bonzini pbonz...@redhat.com
bdrv_co_discard is only covering drivers which have a .bdrv_co_discard()
implementation, but not those with .bdrv_aio_discard(). Not very nice,
and easy to avoid.
Suggested-by: Kevin Wolf kw...@redhat.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
From: Paolo Bonzini pbonz...@redhat.com
This will be used by the SCSI layer.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
Reviewed-by: Peter Lieven p...@kamp.de
Signed-off-by: Stefan Hajnoczi stefa...@redhat.com
---
block.c | 11 +++
include/block/block.h | 3 +++
From: Paolo Bonzini pbonz...@redhat.com
This lets bdrv_co_do_rw receive flags, so that it can be used for
zero writes.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
Reviewed-by: Peter Lieven p...@kamp.de
Signed-off-by: Stefan Hajnoczi stefa...@redhat.com
---
block.c | 17
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