Re: [Qemu-devel] [PATCH qemu v7 0/4] vfio-pci: Allow mmap of MSIX BAR

Hi, This series failed build test on s390x host. Please find the details below. Type: series Message-id: 20180209075503.16996-1-...@ozlabs.ru Subject: [Qemu-devel] [PATCH qemu v7 0/4] vfio-pci: Allow mmap of MSIX BAR === TEST SCRIPT BEGIN === #!/bin/bash # Testing script will be invoked under

Re: [Qemu-devel] [PATCH v2] rtc: placing RTC memory region outside BQL

> > > > > > > $ cat strace_c.sh > > > strace -tt -p $1 -c -o result_$1.log & > > > sleep $2 > > > pid=$(pidof strace) > > > kill $pid > > > cat result_$1.log > > > > > > Before appling this change: > > > $ ./strace_c.sh 10528 30 > > > % time seconds usecs/call callserrors syscall > >

Re: [Qemu-devel] [PATCH v7 0/3] qemu-img: Document --force-share / -U

On Fri, Feb 09, 2018 at 01:29:12PM +0800, Fam Zheng wrote: > v7: Tweak wording again "allowing concurrent writers" -> "allowing other QEMU > processes to open it in write mode". [Eric, Stefan, Kevin] > Add patch to document share-rw. [Stefan] > > v6: Tweak wording ("concurrent writers").

Re: [Qemu-devel] [PATCH v2] block: unify blocksize types

Hi, This series failed build test on s390x host. Please find the details below. Type: series Message-id: 1518169992-19288-1-git-send-email-sa...@skytechnology.pl Subject: [Qemu-devel] [PATCH v2] block: unify blocksize types === TEST SCRIPT BEGIN === #!/bin/bash # Testing script will be invoked

[Qemu-devel] [PATCH v3] block: unify blocksize types

BlockSizes structure used in block size probing has uint32_t types for logical and physical sizes. These fields are wrongfully assigned to uint16_t in BlockConf, which results, among other errors, in assigning 0 instead of 65536 (which will be the case in at least future LizardFS block device

[Qemu-devel] [PATCH 3/4] memory: introduce memory_global_after_dirty_log_sync

There is a race between TCG and accesses to the dirty log: vCPU thread reader thread --- --- TLB check -> slow path notdirty_mem_write write to RAM set dirty flag

[Qemu-devel] [PATCH 2/4] memory: hide memory_region_sync_dirty_bitmap behind DirtyBitmapSnapshot

Simplify the users of memory_region_snapshot_and_clear_dirty, so that they do not have to call memory_region_sync_dirty_bitmap explicitly. Signed-off-by: Paolo Bonzini --- hw/display/cg3.c | 1 - hw/display/exynos4210_fimd.c | 1 - hw/display/framebuffer.c

Re: [Qemu-devel] [PATCH v2 1/2] hw/arm/aspeed: directly map the serial device to the system address space

On 02/09/2018 09:57 AM, Philippe Mathieu-Daudé wrote: > (qemu) info mtree > address-space: cpu-memory-0 >- (prio 0, i/o): system > -07ff (prio 0, rom): aspeed.boot_rom > 1e60-1e7f (prio -1, i/o):

[Qemu-devel] [PULL 11/30] target/arm: implement SM4 instructions

From: Ard Biesheuvel This implements emulation of the new SM4 instructions that have been added as an optional extension to the ARMv8 Crypto Extensions in ARM v8.2. Signed-off-by: Ard Biesheuvel Message-id:

[Qemu-devel] [PATCH v3] spapr: set vsmt to MAX(8, smp_threads)

We ignore silently the value of smp_threads when we set the default VSMT value, and if smp_threads is greater than VSMT kernel is going into trouble later. Fixes: 8904e5a750 ("spapr: Adjust default VSMT value for better migration compatibility") Signed-off-by: Laurent Vivier

Re: [Qemu-devel] [PATCH] target-i386: adds PV_DEDICATED hint CPUID feature bit

On 08/02/2018 19:12, Eduardo Habkost wrote: > On Thu, Feb 08, 2018 at 05:44:20PM +0800, Wanpeng Li wrote: >> From: Wanpeng Li >> >> Add PV_DEDICATED hint cpuid feature bit. >> > [...] >> diff --git a/target/i386/cpu.c b/target/i386/cpu.c >> index d70954b..cf48931 100644 >>

[Qemu-devel] [PATCH v2 2/2] hw/arm/aspeed: simplify using the 'unimplemented device' for aspeed_soc.io

(qemu) info mtree address-space: cpu-memory-0 - (prio 0, i/o): system -07ff (prio 0, rom): aspeed.boot_rom -1e60-1e7f (prio -1, i/o): aspeed_soc.io +1e60-1e7f (prio -1000,

Re: [Qemu-devel] [PATCH v5 12/23] RISC-V HTIF Console

https://github.com/michaeljclark/riscv-qemu/commit/17272f5c66adf8532f196d660d2a593c2178ac95 hw/core/loader.c | 18 -- include/hw/elf_ops.h | 28 include/hw/loader.h | 17 - 3 files changed, 48 insertions(+), 15 deletions(-)

Re: [Qemu-devel] [PATCH] hw/char/stm32f2xx_usart: improve TXE/TC bit handling

On Thu, Feb 08, 2018 at 02:58:29PM +, Peter Maydell wrote: > On 4 February 2018 at 20:41, Richard Braun wrote: > > Consider that data is always immediately sent. As a result, keep > > the SR_TXE and SR_TC bits always set. In addition, fix the reset value > > of the USART

[Qemu-devel] [PULL 13/29] s390x: fix size + content of STSI blocks

From: David Hildenbrand All blocks are 4k in size, which is only true for two of them right now. Also some reserved fields were wrong, fix it and convert all reserved fields to u8. This also fixes the LPAR part output in /proc/sysinfo under TCG. (for now, everything was

[Qemu-devel] [PULL 09/29] s390x/flic: make floating interrupts on TCG actually floating

From: David Hildenbrand Move floating interrupt handling into the flic. Floating interrupts will now be considered by all CPUs, not just CPU #0. While at it, convert I/O interrupts to use a list and make sure we properly consider I/O sub-classes in s390_cpu_has_io_int().

[Qemu-devel] [PULL 15/29] s390x/tcg: remove SMP warning

From: David Hildenbrand We should be pretty good in shape now. Floating interrupts are working and atomic instructions should be atomic. Signed-off-by: David Hildenbrand Message-Id: <20180129125623.21729-15-da...@redhat.com> Signed-off-by: Cornelia Huck

[Qemu-devel] [PULL 26/29] s390x/pci: use the right pal and pba in reg_ioat()

From: Yi Min Zhao When registering ioat, pba should be comprised of leftmost 52 bits and rightmost 12 binary zeros, and pal should be comprised of leftmost 52 bits and right most 12 binary ones. The lower 12 bits of words 5 and 7 of the FIB are ignored by the facility.

Re: [Qemu-devel] [PATCH] block: unify blocksize types

On 09.02.2018 03:19, Fam Zheng wrote: On Thu, 02/08 14:28, Piotr Sarna wrote: BlockSizes structure used in block size probing has uint32_t types for logical and physical sizes. These fields are wrongfully assigned to uint16_t in BlockConf, which results, among other errors, in assigning 0

Re: [Qemu-devel] [PULL 00/26] virtio, vhost, pci, pc: features, fixes and cleanups

On 8 February 2018 at 19:08, Michael S. Tsirkin wrote: > The following changes since commit 008a51bbb343972dd8cf09126da8c3b87f4e1c96: > > Merge remote-tracking branch 'remotes/famz/tags/staging-pull-request' into > staging (2018-02-08 14:31:51 +) > > are available in the

[Qemu-devel] [PATCH 4/4] memory: unify loops to sync dirty log bitmap

Now that memory_region_sync_dirty_bitmap is NULL, we can unify its loop with memory_global_dirty_log_sync's. The only difference is that memory_region_sync_dirty_bitmap will no longer call log_sync on FlatRanges that do have a zero dirty_log_mask, but this is okay because video memory is always

[Qemu-devel] [PATCH 0/4] tcg: fix dirty bitmap race with MTTCG

This is a race that can happen when migrating TCG guests under load. It was introduced by the change to run vCPUs outside the big QEMU lock. Paolo Bonzini (4): memory: remove memory_region_test_and_clear_dirty memory: hide memory_region_sync_dirty_bitmap behind DirtyBitmapSnapshot

[Qemu-devel] [PATCH 1/4] memory: remove memory_region_test_and_clear_dirty

It is unused after g364fb has been converted to use DirtyBitmapSnapshot. Signed-off-by: Paolo Bonzini --- include/exec/memory.h | 24 +++- memory.c | 8 2 files changed, 3 insertions(+), 29 deletions(-) diff --git

Re: [Qemu-devel] [PATCH v2 0/3] virtio-balloon: free page hint reporting support

* Wei Wang (wei.w.w...@intel.com) wrote: > On 02/09/2018 04:15 AM, Dr. David Alan Gilbert wrote: > > * Wei Wang (wei.w.w...@intel.com) wrote: > > > This is the deivce part implementation to add a new feature, > > > VIRTIO_BALLOON_F_FREE_PAGE_HINT to the virtio-balloon device. The device > > >

[Qemu-devel] [PULL 13/30] sdhci: Add i.MX specific subtype of SDHCI

From: Andrey Smirnov IP block found on several generations of i.MX family does not use vanilla SDHCI implementation and it comes with a number of quirks. Introduce i.MX SDHCI subtype of SDHCI block to add code necessary to support unmodified Linux guest driver. Cc:

[Qemu-devel] [PULL 00/30] target-arm queue

-20180208' into staging (2018-02-08 17:41:15 +) are available in the Git repository at: git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180209 for you to fetch changes up to bbba7757bacc9f890a3f028d328b4b429dbe78ec: hw/core/generic-loader: Allow PC to be set

[Qemu-devel] [PULL 19/30] i.MX: Add i.MX7 GPT variant

From: Andrey Smirnov Add minimal code needed to allow upstream Linux guest to boot. Cc: Peter Maydell Cc: Jason Wang Cc: Philippe Mathieu-Daudé Cc: Marcel Apfelbaum Cc:

[Qemu-devel] [PULL 15/30] i.MX: Add code to emulate i.MX7 CCM, PMU and ANALOG IP blocks

From: Andrey Smirnov Add minimal code needed to allow upstream Linux guest to boot. Cc: Peter Maydell Cc: Jason Wang Cc: Philippe Mathieu-Daudé Cc: Marcel Apfelbaum Cc:

[Qemu-devel] [PULL 10/30] target/arm: implement SM3 instructions

From: Ard Biesheuvel This implements emulation of the new SM3 instructions that have been added as an optional extension to the ARMv8 Crypto Extensions in ARM v8.2. Signed-off-by: Ard Biesheuvel Message-id:

[Qemu-devel] [PATCH] qcow2: Use g_try_realloc() in qcow2_expand_zero_clusters()

g_realloc() aborts the program if it fails to allocate the required amount of memory. We want to detect that scenario and return an error instead, so let's use g_try_realloc(). Signed-off-by: Alberto Garcia --- block/qcow2-cluster.c | 10 +- 1 file changed, 9

[Qemu-devel] [PATCH v12 07/30] sdhci: add a 'spec_version property' (default to v2)

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/sd/sdhci-internal.h | 4 ++-- include/hw/sd/sdhci.h | 2 ++ hw/sd/sdhci.c | 27 +++ 3 files changed, 27 insertions(+), 6 deletions(-)

[Qemu-devel] [PATCH v12 02/30] sdhci: add qtest to check the SD capabilities register

The PCI model is tested with the pc/x86_64 machine, the SysBus model with the smdkc210/arm machine. Suggested-by: Paolo Bonzini Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Paolo Bonzini --- tests/sdhci-test.c | 145

[Qemu-devel] [PATCH v12 00/30] SDHCI: clean v1/2 Specs, UHS-I cards tuning sequence

This series is expected to be taken by Paolo. It includes the last versions of both series: - SDHCI: clean v1/v2 Specs (part 2) - SDHCI: add tuning sequence for UHS-I cards (part 3) Since v11: - rebased due to conflict (IMX_USDHC fd1e5c817964) - QSDHCI uses union (Paolo) - do not enable UNIMP

[Qemu-devel] [PATCH v12 13/30] sdhci: check Spec v2 capabilities (DMA and 64-bit bus)

Incorrect value will throw an error. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/sd/sdhci-internal.h | 14 +++--- hw/sd/sdhci.c | 19 +++ 2 files changed, 22 insertions(+), 11

[Qemu-devel] [PATCH v12 23/30] hw/arm/bcm2835_peripherals: implement SDHCI Spec v3

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/arm/bcm2835_peripherals.c | 21 + 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/hw/arm/bcm2835_peripherals.c

[Qemu-devel] [PATCH v12 06/30] sdhci: add qtest to check the SD Spec version

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Stefan Hajnoczi --- tests/sdhci-test.c | 24 1 file changed, 24 insertions(+) diff --git a/tests/sdhci-test.c b/tests/sdhci-test.c index 7c50c0482b..24feea744a 100644 ---

[Qemu-devel] [PATCH v12 19/30] sdhci: implement the Host Control 2 register (tuning sequence)

[based on a patch from Alistair Francis from qemu/xilinx tag xilinx-v2015.2] Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/sd/sdhci-internal.h | 10 ++ include/hw/sd/sdhci.h | 1 +

[Qemu-devel] [PATCH v12 22/30] sdhci: implement CMD/DAT[] fields in the Present State register

[based on a patch from Alistair Francis from qemu/xilinx tag xilinx-v2015.2] Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/sd/sdhci-internal.h | 2 ++ include/hw/sd/sd.h | 4

[Qemu-devel] [PATCH v12 30/30] sdhci: add Spec v4.2 register definitions

Signed-off-by: Philippe Mathieu-Daudé --- hw/sd/sdhci-internal.h | 9 + hw/sd/sdhci.c | 14 ++ 2 files changed, 23 insertions(+) diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h index 0092627076..e1bb733aed 100644 ---

Re: [Qemu-devel] [PATCH] block: unify blocksize types

Am 09.02.2018 um 10:44 hat Piotr Sarna geschrieben: > On 09.02.2018 03:19, Fam Zheng wrote: > > On Thu, 02/08 14:28, Piotr Sarna wrote: > > > BlockSizes structure used in block size probing has uint32_t types > > > for logical and physical sizes. These fields are wrongfully assigned > > > to

[Qemu-devel] [PATCH v12 28/30] sdhci: check Spec v3 capabilities qtest

Signed-off-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis --- tests/sdhci-test.c | 12 tests/Makefile.include | 1 + 2 files changed, 13 insertions(+) diff --git a/tests/sdhci-test.c b/tests/sdhci-test.c index

Re: [Qemu-devel] [PATCH v3] block: unify blocksize types

Am 09.02.2018 um 11:36 hat Piotr Sarna geschrieben: > BlockSizes structure used in block size probing has uint32_t types > for logical and physical sizes. These fields are wrongfully assigned > to uint16_t in BlockConf, which results, among other errors, > in assigning 0 instead of 65536 (which

Re: [Qemu-devel] [PATCH 0/3] block: fix blk_aio_*() segfault when blk->root == NULL

On 02/08/2018 11:18 AM, Stefan Hajnoczi wrote: Using bdrv_inc_in_flight(blk_bs(blk)) doesn't work since BlockBackend->root may be NULL. This patch series solves the issue by adding an BlockBackend->in_flight counter so requests can be tracked even when there is no BlockDriverState. This should

[Qemu-devel] ANNOUNCE: libguestfs 1.38 released

I'm pleased to announce libguestfs 1.38, a library and a set of tools for accessing and modifying virtual machine disk images. This release represents about a year of work by many contributors. I'd like to call out in particular substantial contributions from: Cédric Bosdonnat, Pavel Butsykin,

Re: [Qemu-devel] [Qemu-block] [PATCH] block/nvme: fix Coverity reports

On 09/02/2018 17:16, Kevin Wolf wrote: > Am 09.02.2018 um 16:24 hat Paolo Bonzini geschrieben: >> 1) string not null terminated in sysfs_find_group_file >> >> 2) NULL pointer dereference and dead local variable in nvme_init. >> >> Signed-off-by: Paolo Bonzini >> --- >>

[Qemu-devel] [PATCH v2 02/11] hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handling

The PENDNMISET/CLR bits in the ICSR should be RAZ/WI from NonSecure state if the AIRCR.BFHFNMINS bit is zero. We had misimplemented this as making the bits RAZ/WI from both Secure and NonSecure states. Fix this bug by checking attrs.secure so that Secure code can pend and unpend NMIs.

Re: [Qemu-devel] [PATCH v2] qmp: add query-cpus-fast

On 09.02.2018 15:27, Eduardo Habkost wrote: [...] >> I'm keeping it mainly for s390. Viktor, libvirt is still using >> this field in s390, no? >> >> Dropping halted and having management software still using query-cpus >> because of halted would be a total failure of query-cpus-fast. > > If I

Re: [Qemu-devel] [PATCH] qcow2: Use g_try_realloc() in qcow2_expand_zero_clusters()

Am 09.02.2018 um 15:42 hat Alberto Garcia geschrieben: > g_realloc() aborts the program if it fails to allocate the required > amount of memory. We want to detect that scenario and return an error > instead, so let's use g_try_realloc(). > > Signed-off-by: Alberto Garcia

Re: [Qemu-devel] [PATCH v3] block: unify blocksize types

On 02/09/2018 04:36 AM, Piotr Sarna wrote: BlockSizes structure used in block size probing has uint32_t types for logical and physical sizes. These fields are wrongfully assigned to uint16_t in BlockConf, which results, among other errors, in assigning 0 instead of 65536 (which will be the case

[Qemu-devel] [PATCH v2 06/11] hw/intc/armv7m_nvic: Implement SCR

We were previously making the system control register (SCR) just RAZ/WI. Although we don't implement the functionality this register controls, we should at least provide the state, including the banked state for v8M. Signed-off-by: Peter Maydell --- target/arm/cpu.h

Re: [Qemu-devel] [PATCH 1/3] block: add BlockBackend->in_flight counter

On 09/02/2018 18:23, Kevin Wolf wrote: > Am 09.02.2018 um 17:28 hat Paolo Bonzini geschrieben: >> On 08/02/2018 18:18, Stefan Hajnoczi wrote: >>> +BlockDriverState *bs = blk_bs(blk); >>> + >>> +if (bs) { >>> +bdrv_drained_begin(bs); >>> +} >>> + >>> +/* We may have aio

Re: [Qemu-devel] [PATCH 1/3] block: add BlockBackend->in_flight counter

Am 09.02.2018 um 17:28 hat Paolo Bonzini geschrieben: > On 08/02/2018 18:18, Stefan Hajnoczi wrote: > > +BlockDriverState *bs = blk_bs(blk); > > + > > +if (bs) { > > +bdrv_drained_begin(bs); > > +} > > + > > +/* We may have aio requests like -ENOMEDIUM in flight */ > > +

[Qemu-devel] [PATCH/RFC 1/5] vfio/platform: make the vfio-platform device non abstract

From: Auger Eric Up to now the vfio-platform device has been abstract and could not be instantiated. The integration of a new vfio platform device required to create a dummy derived device which only set the compatibility string. Following the few vfio-platform device

[Qemu-devel] [PATCH/RFC 3/6] clk: renesas: r8a7795: Mark the GPIO6 clock critical

The GPIO6 block will be exported to a guest. As long as the guest won't manage its module clock, it must be kept running by the host. Not-Signed-off-by: Geert Uytterhoeven --- TODO: Find a way to manage module clocks using PM Domains and Runtime PM on the guest.

Re: [Qemu-devel] [PATCH 3/4] 9pfs: stat_to_qid: use device as input to qid.path

On Fri, 9 Feb 2018 10:06:05 -0600 Eric Blake wrote: > On 02/09/2018 09:13 AM, Greg Kurz wrote: > > On Thu, 8 Feb 2018 19:00:18 +0100 > > wrote: > > > >> From: Antonios Motakis > >> > >> To support multiple devices

Re: [Qemu-devel] [PATCH 07/27] qcow2: Handle full/falloc preallocation in qcow2_create2()

On 2018-02-08 20:23, Kevin Wolf wrote: > Once qcow2_create2() can be called directly on an already existing node, > we must provide the 'full' and 'falloc' preallocation modes outside of > creating the image on the protocol layer. Fortunately, we have > preallocated truncate now which can provide

Re: [Qemu-devel] [PATCH 09/27] qdict: Introduce qdict_rename_keys()

On 2018-02-09 19:18, Max Reitz wrote: > On 2018-02-08 20:23, Kevin Wolf wrote: >> A few block drivers will need to rename .bdrv_create options for their >> QAPIfication, so let's have a helper function for that. >> >> Signed-off-by: Kevin Wolf >> --- >> include/qapi/qmp/qdict.h

Re: [Qemu-devel] [PATCH 09/27] qdict: Introduce qdict_rename_keys()

On 2018-02-08 20:23, Kevin Wolf wrote: > A few block drivers will need to rename .bdrv_create options for their > QAPIfication, so let's have a helper function for that. > > Signed-off-by: Kevin Wolf > --- > include/qapi/qmp/qdict.h | 6 ++ > qobject/qdict.c | 30

[Qemu-devel] [PATCH 2/2] 9p: fix leak in synth_name_to_path()

Leak found thanks to ASAN: Direct leak of 8 byte(s) in 1 object(s) allocated from: #0 0x55995789ac90 in __interceptor_malloc (/home/elmarco/src/qemu/build/x86_64-softmmu/qemu-system-x86_64+0x1510c90) #1 0x7f0a91190f0c in g_malloc /home/elmarco/src/gnome/glib/builddir/../glib/gmem.c:94

Re: [Qemu-devel] [PATCH v7 17/26] target/i386: encrypt bios rom

* Brijesh Singh (brijesh.si...@amd.com) wrote: > SEV requires that guest bios must be encrypted before booting the guest. I'm curious; is it just the main BIOS that needs encryption - what about things like device/PXE rom images? Dave > > Cc: "Michael S. Tsirkin" > Cc: Paolo

Re: [Qemu-devel] [PATCH v2] qmp: add query-cpus-fast

On Fri, 9 Feb 2018 15:50:00 +0100 Viktor Mihajlovski wrote: > On 09.02.2018 15:27, Eduardo Habkost wrote: > [...] > >> I'm keeping it mainly for s390. Viktor, libvirt is still using > >> this field in s390, no? > >> > >> Dropping halted and having management software

Re: [Qemu-devel] [PATCH v2 31/32] arm/translate-a64: implement simd_scalar_three_reg_same_fp16

On 02/08/2018 09:31 AM, Alex Bennée wrote: > This covers the encoding group: > > Advanced SIMD scalar three same FP16 > > As all the helpers are already there it is simply a case of calling the > existing helpers in the scalar context. > > Signed-off-by: Alex Bennée >

[Qemu-devel] [PATCHv2 00/12] cuda: various fixes, tidy-ups, and move 6522 to separate device

The Mac CUDA device (also known as via-cuda) consists of two parts: a 6522 VIA acting as an interface chip and the CUDA device itself. Currently there are at least 2 other upcoming Mac devices that include their own 6522 VIA implementations: Ben's via-pmu device and Laurent's mac_via device with

[Qemu-devel] [PATCHv2 01/12] cuda: do not use old_mmio accesses

Signed-off-by: Mark Cave-Ayland --- hw/misc/macio/cuda.c | 40 1 file changed, 8 insertions(+), 32 deletions(-) diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index 008d8bd4d5..6631017ca2 100644 ---

[Qemu-devel] [PATCHv2 02/12] cuda: don't allow writes to port output pins

Use the direction registers as a mask to ensure that only input pins are updated upon write. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daudé --- hw/misc/macio/cuda.c | 4 ++-- 1

[Qemu-devel] [PATCHv2 09/12] misc: introduce new mos6522 VIA device and enable it for ppc builds

The MOS6522 VIA forms the bridge part of several Mac devices, including the Mac via-cuda and via-pmu devices. Introduce a standard mos6522 device that can be shared amongst multiple implementations. This is effectively taking the 6522 parts out of cuda.c and turning them into a separate device

Re: [Qemu-devel] [PATCHv2 00/12] cuda: various fixes, tidy-ups, and move 6522 to separate device

Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20180209185142.17151-1-mark.cave-ayl...@ilande.co.uk Subject: [Qemu-devel] [PATCHv2 00/12] cuda: various fixes, tidy-ups, and move 6522 to separate device === TEST SCRIPT

[Qemu-devel] [PULL 1/2] iotests: 205: support luks format

From: Vladimir Sementsov-Ogievskiy Support default luks options in VM.add_drive and in new library function qemu_img_create. Use it in 205 iotests. Signed-off-by: Vladimir Sementsov-Ogievskiy Message-Id:

Re: [Qemu-devel] [PATCHv2 00/12] cuda: various fixes, tidy-ups, and move 6522 to separate device

On 09/02/18 19:12, no-re...@patchew.org wrote: Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20180209185142.17151-1-mark.cave-ayl...@ilande.co.uk Subject: [Qemu-devel] [PATCHv2 00/12] cuda: various fixes, tidy-ups,

Re: [Qemu-devel] [PATCH v5 00/23] RISC-V QEMU Port Submission

On 02/07/2018 05:28 PM, Michael Clark wrote: > create mode 100644 hw/riscv/Makefile.objs > create mode 100644 hw/riscv/riscv_elf.c > create mode 100644 hw/riscv/riscv_hart.c > create mode 100644 hw/riscv/riscv_htif.c > create mode 100644 hw/riscv/sifive_clint.c > create mode 100644

[Qemu-devel] [Bug 1738283] Re: 'Less than' (<), 'more than' (>), and 'pipe' (|) can't be typed via VNC

We ran into this as well, using qemu 2.11.0. We're not using the "-k en-us" command line flag, and we're using noVNC as a client (which supports the QEMUExtendedKeyEvent encoding) -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU.

Re: [Qemu-devel] [PATCH] net: fix misaligned member access

Hi Marc-André, On 02/09/2018 04:03 PM, Marc-André Lureau wrote: > Fixes the following ASAN warnings: > > /home/elmarco/src/qemu/hw/net/net_tx_pkt.c:201:27: runtime error: member > access within misaligned address 0x63128846 for type 'struct ip_header', > which requires 4 byte alignment >

[Qemu-devel] [PATCH/RFC 6/6] arm64: Add virt_defconfig

Add a simple defconfig for virtualized arm64 machines, based on an OpenWRT config. This expects "initramfs.cpio" to exist, which can be extracted from e.g. an OpenWRT image using binwalk. CONFIG_GPIO_RCAR is enabled for testing GPIO pass-through on R-Car Gen3. Not-Signed-off-by: Geert

Re: [Qemu-devel] [PATCH v2 3/3] block/iscsi: fix ioctl cancel use-after-free

On 03/02/2018 07:16, Stefan Hajnoczi wrote: > iscsi_aio_cancel() does not increment the request's reference count, > causing a use-after-free when ABORT TASK finishes after the request has > already completed. > > There are some additional issues with iscsi_aio_cancel(): > 1. Several ABORT TASKs

Re: [Qemu-devel] [PATCH v2 1/3] block/iscsi: drop unused IscsiAIOCB->buf field

On 03/02/2018 07:16, Stefan Hajnoczi wrote: > The IscsiAIOCB->buf field has not been used since commit > e49ab19fcaa617ad6cdfe1ac401327326b6a2552 ("block/iscsi: bump libiscsi > requirement to 1.9.0"). It used to be a linear buffer for old libiscsi > versions that didn't support scatter-gather.

Re: [Qemu-devel] [PATCH v2 25/32] arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16

On 02/08/2018 09:31 AM, Alex Bennée wrote: > We go with the localised helper. > > Signed-off-by: Alex Bennée > --- > target/arm/helper-a64.c| 29 + > target/arm/helper-a64.h| 1 + > target/arm/translate-a64.c | 4 > 3 files

Re: [Qemu-devel] [PATCH v2 24/32] arm/translate-a64: add FP16 FRECPE

On 02/08/2018 09:31 AM, Alex Bennée wrote: > Now we have added f16 during the re-factoring we can simply call the > helper. > > Signed-off-by: Alex Bennée > --- > target/arm/translate-a64.c | 8 > 1 file changed, 8 insertions(+) Reviewed-by: Richard Henderson

[Qemu-devel] [PATCH 1/1] hw/ppc: rename functions in comments

Commit bcb5ce08cf ("spapr: Rename machine init functions for clarity") renamed ppc_spapr_reset to spapr_machine_reset and ppc_spapr_init to spapr_machine_init. Let's also rename the references in comments. Signed-off-by: Daniel Henrique Barboza --- hw/ppc/spapr.c

[Qemu-devel] [PATCHv2 12/12] cuda: convert to trace-events

Signed-off-by: Mark Cave-Ayland --- Makefile.objs | 1 + hw/misc/macio/cuda.c | 50 -- hw/misc/macio/trace-events | 11 ++ 3 files changed, 29 insertions(+), 33 deletions(-) create mode 100644

[Qemu-devel] [PATCHv2 07/12] cuda: set timer 1 frequency property to CUDA_TIMER_FREQ

Now that we have successfully decoupled the timebase frequency and the hardware timer frequency, set the timer 1 frequency property to CUDA_TIMER_FREQ and alter get_next_irq_time() to use it rather than the hard-coded constant. In addition to this we must now switch the tb_diff calculation over

[Qemu-devel] [PATCHv2 08/12] cuda: factor out timebase-derived counter value and load time

Commit b981289c49 "PPC: Cuda: Use cuda timer to expose tbfreq to guest" altered the timer calculations from those based upon the hardware CUDA clock frequency to those based upon the CPU timebase frequency. In fact we can isolate the differences to 2 simple changes: one to the counter read value

[Qemu-devel] [PATCH] net: fix misaligned member access

Fixes the following ASAN warnings: /home/elmarco/src/qemu/hw/net/net_tx_pkt.c:201:27: runtime error: member access within misaligned address 0x63128846 for type 'struct ip_header', which requires 4 byte alignment 0x63128846: note: pointer points here 01 00 00 00 45 00 01 a9 01 00 00

[Qemu-devel] QEMU leaves pidfile behind on exit

QEMU leaves the pidfile behind on a clean exit when using the option -pidfile /var/run/qemu.pid. Should QEMU leave it behind or should it clean up after itself? I'm willing to take a crack at a patch to fix the issue, but before I do, I want to make sure that leaving the pidfile behind was

[Qemu-devel] [qemu-web PATCH] Add "Understanding QEMU devices" blog post

Last July, Eric Blake wrote a nice summary for newcomers about what QEMU has to do to emulate devices for the guests. So far, we missed integratating this somewhere into the QEM web site or wiki, so let's publish this now as a nice blog post for the users. Signed-off-by: Thomas Huth

Re: [Qemu-devel] [PATCHv2 01/12] cuda: do not use old_mmio accesses

Hi Mark, On 02/09/2018 03:51 PM, Mark Cave-Ayland wrote: > Signed-off-by: Mark Cave-Ayland > --- > hw/misc/macio/cuda.c | 40 > 1 file changed, 8 insertions(+), 32 deletions(-) > > diff --git a/hw/misc/macio/cuda.c

Re: [Qemu-devel] [Qemu-block] [PATCH v2 3/3] block/iscsi: fix ioctl cancel use-after-free

On 03/02/2018 07:16, Stefan Hajnoczi wrote: > @@ -298,14 +301,25 @@ iscsi_aio_cancel(BlockAIOCB *blockacb) > IscsiAIOCB *acb = (IscsiAIOCB *)blockacb; > IscsiLun *iscsilun = acb->iscsilun; > > -if (acb->status != -EINPROGRESS) { > +qemu_mutex_lock(>mutex); > + > +/* If it

[Qemu-devel] [PATCH/RFC 2/5] hw/arm/sysbus-fdt: Allow device matching with compat string

From: Auger Eric Up to now we have relied on the device type to identify a device tree node creation function. Since we would like the VFIO-PLATFORM device to be instantiable with different compatibility strings we introduce the capability to specialize the node creation

[Qemu-devel] [PATCH/RFC 5/6] gpio: rcar: Add virtualization workarounds

Allow to enable the driver if virtualization is enabled. Handle the absence of clocks and interrupts, to support guests that don't provide these yet. Not-Signed-off-by: Geert Uytterhoeven --- To be dropped once clocks and interrupts are supported on the guest. ---

[Qemu-devel] [Bug 1350435] Re: tcg.c:1693: tcg fatal error

(wrong bug, sorry!) -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1350435 Title: tcg.c:1693: tcg fatal error Status in launchpad-buildd: Won't Fix Status in QEMU: Fix Released Status in qemu

Re: [Qemu-devel] [PATCH v2 29/32] arm/translate-a64: add FP16 FMOV to simd_mod_imm

On 02/08/2018 09:31 AM, Alex Bennée wrote: > Only one half-precision instruction has been added to this group. > > Signed-off-by: Alex Bennée > > --- > v2 > - checkpatch fixes > --- > target/arm/translate-a64.c | 48 > -- >

Re: [Qemu-devel] [PATCH 10/27] qcow2: Use visitor for options in qcow2_create()

On 2018-02-08 20:23, Kevin Wolf wrote: > Signed-off-by: Kevin Wolf > --- > block/qcow2.c | 219 > - > tests/qemu-iotests/049.out | 8 +- > tests/qemu-iotests/112.out | 4 +- > 3 files changed, 84 insertions(+), 147

[Qemu-devel] [PATCHv2 06/12] cuda: minor cosmetic tidy-ups to get_next_irq_time()

Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé --- hw/misc/macio/cuda.c | 23 --- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index

[Qemu-devel] [PATCHv2 05/12] cuda: rename frequency property to tb_frequency

This allows us to more easily differentiate between the timebase frequency used to calibrate the MacOS timers and the actual frequency of the hardware clock as indicated by CUDA_TIMER_FREQ. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé

Re: [Qemu-devel] [PATCH v5 12/23] RISC-V HTIF Console

On 02/09/2018 01:08 AM, Michael Clark wrote: > https://github.com/michaeljclark/riscv-qemu/commit/17272f5c66adf8532f196d660d2a593c2178ac95 > >  hw/core/loader.c     |   18 -- >  include/hw/elf_ops.h |   28 >  include/hw/loader.h  |   17

[Qemu-devel] [PATCH v1 1/3] cpus: properly inititalize CPU > 1 under single-threaded TCG

All but the first CPU are currently not fully inititalized (e.g. cpu->created is never set). Signed-off-by: David Hildenbrand --- cpus.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/cpus.c b/cpus.c index f298b659f4..ade1651032 100644 --- a/cpus.c +++ b/cpus.c @@

[Qemu-devel] [PATCH v1 2/3] cpus: wait for CPU creation at central place

We can now also wait for the CPU creation for single-threaded TCG, so we can move the waiting bits further out. Signed-off-by: David Hildenbrand --- cpus.c | 22 -- 1 file changed, 4 insertions(+), 18 deletions(-) diff --git a/cpus.c b/cpus.c index

Re: [Qemu-devel] [PATCHv2 11/12] ppc: move CUDAState and other CUDA-related definitions into separate cuda.h file

On 02/09/2018 03:51 PM, Mark Cave-Ayland wrote: > Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé > --- > hw/misc/macio/cuda.c | 1 + > hw/misc/macio/macio.c| 1 + > hw/ppc/mac.h | 77

[Qemu-devel] [PATCH/RFC 5/5] hw/arm/sysbus-fdt: Enable rcar-gen3-gpio dynamic instantiation

Allow the instantiation of a Renesas R-Car Gen3 GPIO controller device from the QEMU command line: -device vfio-platform,host=,manufacturer=renesas,model=rcar-gen3-gpio -device vfio-platform,sysfsdev=,manufacturer=renesas,model=rcar-gen3-gpio A specialized device tree node is created for the

[Qemu-devel] [PATCH/RFC 4/5] vfio: No-IOMMU mode support

From: Xiao Feng Ren Add qemu support for the newly introduced VFIO No-IOMMU driver. We need to add special handling for: - Group character device is /dev/vfio/noiommu-$GROUP. - No-IOMMU does not rely on a memory listener. - No IOMMU will be set for its group, so no

[Qemu-devel] [PATCH/RFC 0/5] R-Car Gen3 GPIO Pass-Through Prototype (QEMU)

Hi all, This RFC patch series is the QEMU side of a GPIO Pass-Through prototype for Renesas R-Car platforms using vfio-platform. Together with its counterpart for Linux, it provides direct access from a QEMU+KVM guest to a GPIO controller in an R-Car Gen3 SoC. This allows the guest to

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