Rename the ThrottleLimits member names and modify related code
Signed-off-by: xiezhide
---
qapi/block-core.json | 70 +++---
util/throttle.c | 163 +--
2 files changed, 116 insertions(+), 117 deletions(-)
diff --git
Rewrite BlockIOThrottle with ThrottleLimits as its base class and modify
related code
Signed-off-by: xiezhide
---
blockdev.c | 2 ++
qapi/block-core.json | 73 ++--
2 files changed, 4 insertions(+), 71 deletions(-)
diff --git
On 11/16/18 6:10 AM, Emilio G. Cota wrote:
> It's possible that newer machines with larger reorder buffers
> will be able to take better advantage of the higher instruction
> locality, hiding the latency of having to execute more instructions.
> I'll test on Skylake tomorrow.
I've noticed that
On Thu, Nov 15, 2018 at 09:47:44AM -0600, Eric Blake wrote:
> On 11/15/18 9:15 AM, Erik Skultety wrote:
> > Since QEMU always picks the default DRI device, libvirt doesn't know which
> > one
> > to put into the mount namespace and relabel it accordingly, hence hitting
> > permission issues,
On 11/15/18 11:35 PM, Alistair Francis wrote:
> Signed-off-by: Alistair Francis
> Signed-off-by: Michael Clark
> ---
> tcg/riscv/tcg-target.inc.c | 34 ++
> 1 file changed, 34 insertions(+)
Reviewed-by: Richard Henderson
r~
On Mon, 5 Nov 2018 02:40:41 +0100
Samuel Ortiz wrote:
> It is going to be used by the PC machine type as the MADT table builder
> method and thus needs to be exported outside of acpi-build.c
>
> Also, now that the generic build_madt() API is exported, we have to
> rename the ARM static one in
Because the CMB BAR has a min_access_size of 2, if you read the last
byte it will try to memcpy *2* bytes from n->cmbuf, causing an off-by-one
error. This is CVE-2018-16847.
Another way to fix this might be to register the CMB as a RAM memory
region, which would also be more efficient. However,
This patches provide qmp interface to query/set io throttle parameters of a
fsdev.
Some of patches also refactor the code and structure that was present in block
and fsdev files.
xiezhide (6):
fsdev-throttle-qmp: factor out throttle code to reuse code
fsdev-throttle-qmp: Rename the
Factor out throttle parameter parsing code to a new common
function which will be used by block and fsdev.
Rename function throttle_parse_options to throttle_parse_group
to resolve function name conflict
Reviewed-by: Eric Blake
Signed-off-by: xiezhide
---
block/throttle.c| 6
-Original Message-
From: Eric Blake [mailto:ebl...@redhat.com]
Sent: 2018年11月16日 4:56
To: xiezhide ; qemu-devel@nongnu.org
Cc: gr...@kaod.org; aneesh.ku...@linux.vnet.ibm.com; arm...@redhat.com;
be...@igalia.com; zengcanfu 00215970 ; Jinxuefeng
; Chenhui (Felix, Euler)
Subject: Re:
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: cover.1542321076.git.alistair.fran...@wdc.com
Type: series
Subject: [Qemu-devel] [RFC v1 00/23] Add RISC-V TCG backend support
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
On 11/15/18 11:35 PM, Alistair Francis wrote:
> Signed-off-by: Alistair Francis
> Signed-off-by: Michael Clark
> ---
> tcg/riscv/tcg-target.inc.c | 62 ++
> 1 file changed, 62 insertions(+)
>
> diff --git a/tcg/riscv/tcg-target.inc.c
Hi Artyom,
I noticed that QEMU aborts the hard way when it is simply started like this:
$ sparc64-softmmu/qemu-system-sparc64 -M sun4v
qemu: fatal: Trap 0x0010 while trap level (6) >= MAXTL (6), Error state
pc: 0200 npc: 0204
%g0-3:
>> >> add pvpanic device in virt acpi table, so when kenrel command line uses
>> >> acpi=force, kernel can get info from acpi table in aarch64.
>>
>> [...]
>>
>> >>
>> >> +static void acpi_dsdt_add_pvpanic(Aml *scope, const MemMapEntry
>> >> *pvpanic_memmap)
>> >> +{
>> >> +Aml *dev =
On Fri, Nov 16, 2018 at 10:24:30AM +0100, Erik Skultety wrote:
> On Fri, Nov 16, 2018 at 09:43:52AM +0100, Gerd Hoffmann wrote:
> > It's simple enough and we are early in the -rc cycle still, I think it
> > would be okay for 3.1.
>
> As far as upstream's concerned, I'm okay with both because
On Mon, 5 Nov 2018 02:40:42 +0100
Samuel Ortiz wrote:
> From: Sebastien Boeuf
>
> Instead of using the machine type specific method find_i440fx() to
> retrieve the PCI bus, this commit aims to rely on the fact that the
> PCI bus is known by the structure AcpiPciHpState.
>
> When the
provides two interfaces:
1. set the IO limits for the required fsdev device
2. query info of all the fsdev devices.
Signed-off-by: xiezhide
---
Makefile| 27 -
Makefile.objs | 12 --
fsdev/qemu-fsdev-dummy.c| 11 +
On 11/15/18 11:35 PM, Alistair Francis wrote:
> +case 'L':
> +/* qemu_ld/qemu_st constraint */
> +ct->ct |= TCG_CT_REG;
> +ct->u.regs = 0x;
> +/* qemu_ld/qemu_st uses TCG_REG_TMP0 */
> +#if defined(CONFIG_SOFTMMU)
> +/* tcg_out_tlb_load uses
On Fri, 16 Nov 2018 at 00:21, Peter Maydell wrote:
>
> On 19 October 2018 at 09:55, Hongbo Zhang wrote:
> > there are two commit reverts I have to do to boot system currently, these
> > block not only my new 'sbsa-ref', but also the 'virt'.
> > (other two workarounds can be ignored, they are
On 11/15/18 11:35 PM, Alistair Francis wrote:
> +static int32_t encode_simm12(uint32_t imm)
> +{
> +return ((imm << 20) >> 25) << 25 | ((imm << 27) >> 27) << 7;
> +}
I'm not fond of triple shifts like this, as it makes me count.
I'd be ok with a formulation like
return ((imm & 0x1f) <<
On 11/15/18 11:35 PM, Alistair Francis wrote:
> +static void reloc_sbimm12(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
> +{
> +intptr_t offset = (intptr_t)target - (intptr_t)code_ptr;
> +tcg_debug_assert(offset == sextract32(offset, 1, 12) << 1);
> +
> +code_ptr[0] |=
On 11/15/18 11:36 PM, Alistair Francis wrote:
> +static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
> + TCGReg arg2, TCGLabel *l)
> +{
> +RISCVInsn op = tcg_brcond_to_riscv[cond].op;
> +bool swap = tcg_brcond_to_riscv[cond].swap;
> +
> +
On Fri, Nov 16, 2018 at 06:50:06PM +0800, Peng Hao wrote:
> Add mmio support info in docs/specs/pvpanic.txt.
>
> Signed-off-by: Peng Hao
> ---
> docs/specs/pvpanic.txt | 16 +++-
> 1 file changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/docs/specs/pvpanic.txt
Hi Jean, Bharat,
On 11/14/18 5:41 PM, Auger Eric wrote:
> Hi Jean,
>
> On 11/14/18 5:01 PM, Jean-Philippe Brucker wrote:
>> On 09/11/2018 11:29, Eric Auger wrote:
>>> +static void create_virtio_iommu(VirtMachineState *vms,
>>> +const char *pciehb_nodename, PCIBus
On Thu, Nov 15, 2018 at 10:41:55AM +0100, Luc Michel wrote:
> Add a couple of helper functions to cope with GDB threads and processes.
>
> The gdb_get_process() function looks for a process given a pid.
>
> The gdb_get_cpu() function returns the CPU corresponding to the (pid,
> tid) pair given
On Thu, Nov 15, 2018 at 10:41:56AM +0100, Luc Michel wrote:
> Add the gdb_first_cpu() and gdb_next_cpu() to iterate over all
> the CPUs in currently attached processes.
>
> Add the gdb_first_cpu_in_process() and gdb_next_cpu_in_process() to
> iterate over CPUs of a given process.
>
> Use them to
On Thu, Nov 15, 2018 at 10:42:00AM +0100, Luc Michel wrote:
> Add support for multiprocess extension in gdb_vm_state_change()
> function.
>
> Signed-off-by: Luc Michel
> Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
> ---
> gdbstub.c | 15 ---
> 1 file
On Thu, Nov 15, 2018 at 10:41:59AM +0100, Luc Michel wrote:
> Change the Xfer:features:read: packet handling to support the
> multiprocess extension. This packet is used to request the XML
> description of the CPU. In multiprocess mode, different descriptions can
> be sent for different processes.
David Hildenbrand writes:
> The input visitor has some problems right now, especially
> - unsigned type "Range" is used to process signed ranges, resulting in
> inconsistent behavior and ugly/magical code
> - uint64_t are parsed like int64_t, so big uint64_t values are not
> supported and
On Thu, Nov 15, 2018 at 10:42:03AM +0100, Luc Michel wrote:
> Add support for the vAttach packets. In multiprocess mode, GDB sends
> them to attach to additional processes.
>
> Signed-off-by: Luc Michel
Reviewed-by: Edgar E. Iglesias
> ---
> gdbstub.c | 35
As libvirt can't predict which rendernode QEMU would pick, it
won't adjust the permissions on the device, hence QEMU getting
"Permission denied" when opening the DRI device. Therefore, enable
'rendernode' option for egl-headless display type.
Resolves:
On Thu, Nov 15, 2018 at 10:42:05AM +0100, Luc Michel wrote:
> When gdb_set_stop_cpu() is called with a CPU associated to a process
> currently not attached by the GDB client, return without modifying the
> stop CPU. Otherwise, GDB gets confused if it receives packets with a
> thread-id it does not
Eric Blake writes:
> Adding a new qapi module requires some rather tedious repetition to
> wire it into Makefile and Makefile.objs. Add some indirection by
> taking advantage of GNU Make string processing to expand a list
> of module names into all the required artifacts, so that future
>
On Thu, Nov 15, 2018 at 10:41:51AM +0100, Luc Michel wrote:
Hi Luc,
I think I've either reviewed all of the patches or commented on all now.
Great work!
Thanks,
Edgar
> changes since v5:
> - patch 1Rebased on top of master
>
> - patch 2Cluster ID handling hardening to ensure
On Thu, Nov 15, 2018 at 10:42:06AM +0100, Luc Michel wrote:
> Add multiprocess extension support by enabling multiprocess mode when
> the peer requests it, and by replying that we actually support it in the
> qSupported reply packet.
>
> Signed-off-by: Luc Michel
> Reviewed-by: Philippe
On Thu, Nov 15, 2018 at 04:50:52PM -0600, Eric Blake wrote:
> Adding a new qapi module requires some rather tedious repetition to
> wire it into Makefile and Makefile.objs. Add some indirection by
> taking advantage of GNU Make string processing to expand a list
> of module names into all the
Gerd Hoffmann 于2018年11月16日周五 下午6:43写道：
> Signed-off-by: Gerd Hoffmann
>
Reviewed-by: Li Qiang
> ---
> ui/keymaps.c | 7 +++
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/ui/keymaps.c b/ui/keymaps.c
> index 085889b555..6e44f738ed 100644
> --- a/ui/keymaps.c
> +++
After the event data was pushed in the O/S Event Queue, the IVPE
raises the bit corresponding to the priority of the pending interrupt
in the register IBP (Interrupt Pending Buffer) to indicate there is an
event pending in one of the 8 priority queues. The Pending Interrupt
Priority Register
We will need to use xics_max_server_number() to create the sPAPRXive
object modeling the interrupt controller of the machine which is
created before the CPUs.
Signed-off-by: Cédric Le Goater
---
hw/ppc/spapr.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git
The XIVE IRQ backend uses the same layout as the new XICS backend but
covers the full range of the IRQ number space. The IRQ numbers for the
CPU IPIs are allocated at the bottom of this space, below 4K, to
preserve compatibility with XICS which does not use that range.
This should be enough given
Initialize the MSI bitmap from it as this will be necessary for the
sPAPR IRQ backend for XIVE.
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/spapr_irq.h | 1 +
hw/ppc/spapr.c | 2 +-
hw/ppc/spapr_irq.c | 16 +++-
3 files changed, 13 insertions(+), 6
The Event Notification Descriptor also contains two Event State
Buffers providing further coalescing of interrupts, one for the
notification event (ESn) and one for the escalation events (ESe). A
MMIO page is assigned for each to control the EOI through loads
only. Stores are not allowed.
The END
Introduce a new sPAPR IRQ handler to handle resend after migration
when the machine is using a KVM XICS interrupt controller model.
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/spapr_irq.h | 2 ++
hw/ppc/spapr.c | 13 +
hw/ppc/spapr_irq.c | 27
Currently, the interrupt presenter of the VPCU is set at realize
time. Setting it at reset will become useful when the new machine
supporting both interrupt modes is introduced. In this machine, the
interrupt mode is chosen at CAS time and activated after a reset.
Signed-off-by: Cédric Le Goater
The XIVE models for the QEMU and KVM accelerators will have a lot in
common. Introduce an abstract class for the source, the thread context
and the interrupt controller object to handle the differences in the
object initialization. These classes will also be used to define state
synchronization
The IVPE scans the O/S CAM line of the XIVE thread interrupt contexts
to find a matching Notification Virtual Target (NVT) among the NVTs
dispatched on the HW processor threads.
On a real system, the thread interrupt contexts are updated by the
hypervisor when a Virtual Processor is scheduled to
We will need it to initialize the KVM XIVE device globally from the
machine when the XIVE interrupt mode is selected.
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/spapr_xive.h | 2 ++
hw/intc/spapr_xive_kvm.c| 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git
This is simple model of the POWER9 XIVE interrupt controller for the
PowerNV machine. XIVE for baremetal is a complex controller and the
model only addresses the needs of the skiboot firmware.
* Overall architecture
XIVE Interrupt Controller
Replace the abort with an error report which will be handled by the
caller.
Signed-off-by: Cédric Le Goater
---
hw/intc/xics_kvm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/intc/xics_kvm.c b/hw/intc/xics_kvm.c
index efad1b19d821..9662e208fa81 100644
---
The different XIVE virtualization structures (sources and event queues)
are configured with a set of Hypervisor calls :
- H_INT_GET_SOURCE_INFO
used to obtain the address of the MMIO page of the Event State
Buffer (ESB) entry associated with the source.
- H_INT_SET_SOURCE_CONFIG
The KVM IRQ device activation will depend on the interrupt mode chosen
at CAS time by the machine and some methods used at reset or by the
migration need to be protected.
Signed-off-by: Cédric Le Goater
---
hw/intc/spapr_xive_kvm.c | 5 +
hw/intc/xics_kvm.c | 20
This will be used to remove the MMIO regions of the POWER9 XIVE
interrupt controller when the sPAPR machine is reseted.
Signed-off-by: Cédric Le Goater
---
include/hw/sysbus.h | 1 +
hw/core/sysbus.c| 10 ++
2 files changed, 11 insertions(+)
diff --git a/include/hw/sysbus.h
On 11/15/18 11:34 PM, Alistair Francis wrote:
> Signed-off-by: Alistair Francis
> Signed-off-by: Michael Clark
> ---
> tcg/riscv/tcg-target.inc.c | 45 ++
> 1 file changed, 45 insertions(+)
I think this whole patch should be merged with the prologue. They
introduces io throttling hmp interfaces for the fsdev devices
Signed-off-by: xiezhide
---
hmp-commands-info.hx | 15 ++
hmp-commands.hx | 15 ++
hmp.c| 81 ++--
hmp.h| 4 +++
4 files changed,
Move ThrottleLimits into a new file for future reuse.
Signed-off-by: xiezhide
---
Makefile | 9 +
Makefile.objs | 4
qapi/block-core.json | 49 +--
qapi/qapi-schema.json | 1 +
qapi/tlimits.json | 53
On 11/16/18 2:13 AM, Emilio G. Cota wrote:
> This allows us to discard most TBs; in the example above,
> we end up *not* discarding only ~70 TBs, that is we end up keeping
> only 70/2500 = 2.8% of the TBs that we'd discard without OOL.
Thanks.
When I apply this I think I'll rename "n_ool_thunks"
-Original Message-
From: Eric Blake [mailto:ebl...@redhat.com]
Sent: 2018年11月16日 6:03
To: xiezhide ; qemu-devel@nongnu.org
Cc: be...@igalia.com; arm...@redhat.com; zengcanfu 00215970
; gr...@kaod.org; aneesh.ku...@linux.vnet.ibm.com;
Jinxuefeng ; Chenhui (Felix, Euler)
Subject: Re:
-Original Message-
From: Eric Blake [mailto:ebl...@redhat.com]
Sent: 2018年11月16日 5:41
To: xiezhide ; qemu-devel@nongnu.org
Cc: gr...@kaod.org; aneesh.ku...@linux.vnet.ibm.com; arm...@redhat.com;
be...@igalia.com; zengcanfu 00215970 ; Jinxuefeng
; Chenhui (Felix, Euler)
Subject: Re:
On 11/15/18 11:35 PM, Alistair Francis wrote:
> Signed-off-by: Alistair Francis
> Signed-off-by: Michael Clark
> ---
> tcg/riscv/tcg-target.inc.c | 40 ++
> 1 file changed, 40 insertions(+)
Reviewed-by: Richard Henderson
r~
On 11/15/18 11:36 PM, Alistair Francis wrote:
> Signed-off-by: Alistair Francis
> Signed-off-by: Michael Clark
> ---
> tcg/riscv/tcg-target.inc.c | 56 ++
> 1 file changed, 56 insertions(+)
>
> diff --git a/tcg/riscv/tcg-target.inc.c
On Fri, Nov 16, 2018 at 09:45:42AM +0800, peng.h...@zte.com.cn wrote:
> >> add pvpanic device in virt acpi table, so when kenrel command line uses
> >> acpi=force, kernel can get info from acpi table in aarch64.
>
> [...]
>
> >>
> >> +static void acpi_dsdt_add_pvpanic(Aml *scope, const
On 11/15/18 11:36 PM, Alistair Francis wrote:
> +static void tcg_out_mb(TCGContext *s, TCGArg a0)
> +{
> +static const RISCVInsn fence[] = {
> +[0 ... TCG_MO_ALL] = OPC_FENCE_RW_RW,
> +[TCG_MO_LD_LD] = OPC_FENCE_R_R,
> +[TCG_MO_ST_LD] = OPC_FENCE_W_R,
> +
On Fri, Nov 16, 2018 at 09:43:52AM +0100, Gerd Hoffmann wrote:
> On Thu, Nov 15, 2018 at 09:47:44AM -0600, Eric Blake wrote:
> > On 11/15/18 9:15 AM, Erik Skultety wrote:
> > > Since QEMU always picks the default DRI device, libvirt doesn't know
> > > which one
> > > to put into the mount
On 16 November 2018 at 05:01, Peter Xu wrote:
> I would guess there aren't many people like me to prefer booting a VM
> using console, though I agree that it'll be nice if we put something
> into the prebuilt images like what's suggested by Ilya (and so far I
> don't see anything bad with that):
On Thu, Nov 15, 2018 at 10:41:57AM +0100, Luc Michel wrote:
> Change the sC packet handling to support the multiprocess extension.
> Instead of returning the first thread, we return the first thread of the
> current process.
>
> Signed-off-by: Luc Michel
> Reviewed-by: Philippe Mathieu-Daudé
>
On 16 November 2018 at 03:28, John Snow wrote:
> I looked again. I think Vladimir's patch will shut up Coverity for sure,
> feel free to apply it if you want this out of your hair.
>
> Stefan suggests the following, however;
>
>
> diff --git a/migration/block-dirty-bitmap.c
On Thu, Nov 15, 2018 at 10:42:02AM +0100, Luc Michel wrote:
> Add support for the '!' extended mode packet. This is required for the
> multiprocess extension.
>
> Signed-off-by: Luc Michel
Reviewed-by: Edgar E. Iglesias
> ---
> gdbstub.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff
Eric Blake writes:
> Prompted by my review of xiezhide's work. No semantic change, but
> not technically a bug fix, so I don't care if it goes in 3.1 or
> waits for 4.0.
Reviewed-by: Markus Armbruster
https://bugzilla.redhat.com/show_bug.cgi?id=1648236
Changes since v1:
- adjusted the QAPI version and description commentaries for egl-headless
Erik Skultety (3):
qapi: Add "rendernode" display option for egl-headless
ui: Allow specifying 'rendernode' display option for egl-headless
help:
On Thu, Nov 15, 2018 at 10:42:04AM +0100, Luc Michel wrote:
> When a new connection is established, we set the first process to be
> attached, and the others detached. The first CPU of the first process
> is selected as the current CPU.
>
> Signed-off-by: Luc Michel
> Reviewed-by: Alistair
On Fri, 16 Nov 2018 at 17:58, Peter Maydell wrote:
>
> On 16 November 2018 at 08:23, Hongbo Zhang wrote:
> > Well, for the SMP booting, when GICv2 used, there is no problem, max
> > CPU number 8 can be booted, including all the three cases: kernel
> > only, UEFI+kernel and ATF+UEFI+kernel.
> >
>
Hello,
Here is the version 5 of the QEMU models adding support for the XIVE
interrupt controller to the sPAPR machine, under TCG and KVM, and to
the PowerNV POWER9 machine.
The most important changes for sPAPR are the introduction of a new
'dual' pseries machine supporting both interrupt mode:
The XiveFabric offers a simple interface, between the XiveSource
object and the main interrupt controller of the machine. It will
forward event notifications to the XIVE Interrupt Virtualization
Routing Engine (IVRE).
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/xive.h | 23
The 'sent' status of the LSI interrupt source is modeled with the 'P'
bit of the ESB and the assertion status of the source is maintained in
an array under the main sPAPRXive object. The type of the source is
stored in the same array for practical reasons.
Signed-off-by: Cédric Le Goater
---
This introduces a set of XIVE models specific to KVM which derive from
the XIVE base models. The interfaces with KVM are a new capability and
a new KVM device for the XIVE native exploitation interrupt mode.
They handle the initialization of the TIMA and the source ESB memory
regions which have a
Each interrupt mode has its own specific interrupt presenter object,
that we store under the CPU object, one for XICS and one for XIVE.
Extend the sPAPR IRQ backend with a new handler to support them both.
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/spapr.h | 1 +
Each POWER9 processor chip has a XIVE presenter that can generate four
different exceptions to its threads:
- hypervisor exception,
- O/S exception
- Event-Based Branch (EBB)
- msgsnd (doorbell).
Each exception has a state independent from the others called a Thread
Interrupt Management
The XIVE interface for the guest is described in the device tree under
the "interrupt-controller" node. A couple of new properties are
specific to XIVE :
- "reg"
contains the base address and size of the thread interrupt
managnement areas (TIMA), for the User level and for the Guest OS
If a new interrupt mode is chosen by CAS, the machine generates a
reset to reconfigure. At this point, the connection with the previous
KVM device needs to be closed and a new connection needs to opened
with the KVM device operating the chosen interrupt mode.
New routines are introduced to
Removing RTAS handlers will become necessary when the new pseries
machine supporting multiple interrupt mode is introduced.
Signed-off-by: Cédric Le Goater
---
hw/ppc/spapr_rtas.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
index
This routine gathers all the KVM initialization of the XICS KVM
presenter. It will be useful when the initialization of the KVM XICS
device is moved to a global routine.
Signed-off-by: Cédric Le Goater
---
hw/intc/xics_kvm.c | 29 +++--
1 file changed, 19 insertions(+),
We will use it to get the CPU interrupt presenter in XIVE.
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/ppc.h | 1 +
hw/ppc/pnv.c | 16
hw/ppc/ppc.c | 16
3 files changed, 17 insertions(+), 16 deletions(-)
diff --git
On Mon, 5 Nov 2018 02:40:45 +0100
Samuel Ortiz wrote:
All remaining patches a bit out of proper order,
they should be around patch 12/24 where you started to touch MCFG code.
> For building the MCFG table, we need to track a given machine
> type PCI host pointer, and we can't get it from the
On 16 November 2018 at 10:46, Hongbo Zhang wrote:
> On Fri, 16 Nov 2018 at 00:05, Peter Maydell wrote:
>> If after you've done that this patch is still more than
>> about 500 lines long, I would recommend that you split it
>> up into coherent pieces, to make it easier to review.
> I think
On 11/15/18 4:22 PM, Philippe Mathieu-Daudé wrote:
On 15/11/18 20:24, miny...@acm.org wrote:
From: Corey Minyard
smbus.c and smbus.h had device side code, master side code, and
smbus.h has some smbus_eeprom.c definitions. Split them into
separate files.
Lovely cleanup!
Yes, this really
The following changes since commit cb968d275c145467c8b385a3618a207ec111eab1:
Update version for v3.1.0-rc1 release (2018-11-13 18:16:14 +)
are available in the git repository at:
git://git.kraxel.org/qemu tags/fixes-31-20181116-pull-request
for you to fetch changes up
From: Erik Skultety
EGL headless has been missing from QEMU's help or man page, we should
mention that such a thing exists, especially since projects like libvirt
might rely on that. This patch also adds the newly introduced option for
egl-headless 'rendernode'.
Signed-off-by: Erik Skultety
From: Erik Skultety
Unlike SPICE, egl-headless doesn't offer a way of specifying the DRM
node used for OpenGL, hence QEMU always selecting the first one that is
available. Thus, add the 'rendernode' option for egl-headless to QAPI.
Signed-off-by: Erik Skultety
Message-id:
From: Erik Skultety
As libvirt can't predict which rendernode QEMU would pick, it
won't adjust the permissions on the device, hence QEMU getting
"Permission denied" when opening the DRI device. Therefore, enable
'rendernode' option for egl-headless display type.
Resolves:
On 11/15/18 5:01 PM, Philippe Mathieu-Daudé wrote:
Hi Corey,
On 15/11/18 20:24, miny...@acm.org wrote:
These changes allow SMBus access while doing a state transfer.
Seems like a good idea to me in general.
I have these queued for the SMBus IPMI driver work, of course.
I had submitted this
On 14.11.18 14:54, Alberto Garcia wrote:
> On Thu 11 Oct 2018 09:21:34 AM CEST, Fam Zheng wrote:
>> The lock_fd field is not strictly necessary because transferring locked
>> bytes from old fd to the new one shouldn't fail anyway. This spares the
>> user one fd per image.
>>
>> Signed-off-by: Fam
On 29 October 2018 at 15:53, Richard Henderson
wrote:
> This is less complex than the LPAE case, but still we now avoid the
> flush in case it is only the PROCID field that is changing.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper.c | 34 --
> 1
On 16 November 2018 at 08:23, Hongbo Zhang wrote:
> Well, for the SMP booting, when GICv2 used, there is no problem, max
> CPU number 8 can be booted, including all the three cases: kernel
> only, UEFI+kernel and ATF+UEFI+kernel.
>
> But when GICv3 used, these two cases still work: kernel only,
On Thu, Nov 15, 2018 at 10:41:58AM +0100, Luc Michel wrote:
> Change the thread info related packets handling to support multiprocess
> extension.
>
> Add the CPUs class name in the extra info to help differentiate
> them in multiprocess mode.
>
> Signed-off-by: Luc Michel
> Reviewed-by:
On Thu, Nov 15, 2018 at 10:42:01AM +0100, Luc Michel wrote:
> 'D' packets are used by GDB to detach from a process. In multiprocess
> mode, the PID to detach from is sent in the request.
>
> Signed-off-by: Luc Michel
> Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
> ---
EGL headless has been missing from QEMU's help or man page, we should
mention that such a thing exists, especially since projects like libvirt
might rely on that. This patch also adds the newly introduced option for
egl-headless 'rendernode'.
Signed-off-by: Erik Skultety
---
qemu-options.hx | 6
Unlike SPICE, egl-headless doesn't offer a way of specifying the DRM
node used for OpenGL, hence QEMU always selecting the first one that is
available. Thus, add the 'rendernode' option for egl-headless to QAPI.
Signed-off-by: Erik Skultety
---
qapi/ui.json | 17 -
1 file
Paolo Bonzini 于2018年11月16日周五 下午5:31写道：
> Because the CMB BAR has a min_access_size of 2, if you read the last
> byte it will try to memcpy *2* bytes from n->cmbuf, causing an off-by-one
> error. This is CVE-2018-16847.
>
> Another way to fix this might be to register the CMB as a RAM memory
>
Copy the content into the sl and sv files (the only ones left which are
not generated by qemu-keymap).
Signed-off-by: Gerd Hoffmann
---
Makefile | 2 +-
pc-bios/keymaps/common | 174
pc-bios/keymaps/sl | 177
"common" is the only file using it, so we can just include it directly.
Signed-off-by: Gerd Hoffmann
---
Makefile | 2 +-
pc-bios/keymaps/common| 19 ++-
pc-bios/keymaps/modifiers | 18 --
3 files changed, 19 insertions(+), 20 deletions(-)
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