Oh, that's cool. It must be part of the kvmvapic migration data. Still,
there are very likely some rare cases that would break (on any machine),
e.g. if migrating while seabios is accessing the list of option roms.
Paolo
Il mer 8 set 2021, 18:36 Daniel P. Berrangé ha
scritto:
> On Wed, Sep 08,
Fix 'hotplugabble' -> 'hotpluggabble' typo.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/acpi-build.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index d1f5fa3b5a5..478263e12c9 100644
--- a/hw/i386/acpi-build.c
+++
On Wed, Sep 8, 2021, 9:42 AM Markus Armbruster wrote:
> Needs a rebase now. Let's finish discussing my review of pt5b [v2]
> first. Pending patches to expr.py should have made it to master by
> then. If you're impatient, suggest to base on master + "[PATCH 0/5]
> qapi: Another round of minor
Introduce qemu_security_policy_taint() which allows unsafe (read
"not very maintained") code to 'taint' QEMU security policy.
The "security policy" is the @SecurityPolicy QAPI enum, composed of:
- "none" (no policy, current behavior)
- "warn" (display a warning when the policy is tainted,
Hi,
This series is experimental! The goal is to better limit the
boundary of what code is considerated security critical, and
what is less critical (but still important!).
This approach was quickly discussed few months ago with Markus
then Daniel. Instead of classifying the code on a file path
Add the AccelClass::secure_policy_supported field to classify
safe (within security boundary) vs unsafe accelerators.
Signed-off-by: Philippe Mathieu-Daudé
---
include/qemu/accel.h | 5 +
accel/kvm/kvm-all.c | 1 +
accel/xen/xen-all.c | 1 +
softmmu/vl.c | 3 +++
4 files changed,
Stefan, the patch looks great.
Thank you for debugging the performance issue that was happening with
SafeStack.
On 9/2/2021 4:10 AM, Stefan Hajnoczi wrote:
On Wed, Sep 01, 2021 at 05:09:23PM +0100, Stefan Hajnoczi wrote:
It was reported that enabling SafeStack reduces IOPS significantly
(>25%)
> On Sep 6, 2021, at 11:58 PM, Cédric Le Goater wrote:
>
> The Aspeed SoCs have a dual boot function for firmware fail-over
> recovery. The system auto-reboots from the second flash if the main
> flash does not boot sucessfully within a certain amount of time. This
> function is called
On Tue, Sep 7, 2021 at 8:06 AM Dr. David Alan Gilbert
wrote:
> > Possibly, yes. This really need David G's input since he understands
> > the code in way more detail than me.
>
> Hmm I'm not entirely sure why we have the sync after each iteration;
> the case I can think of is if we're doing async
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sdhci-pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/sd/sdhci-pci.c b/hw/sd/sdhci-pci.c
index c737c8b930e..7a36f88fd87 100644
--- a/hw/sd/sdhci-pci.c
+++ b/hw/sd/sdhci-pci.c
@@ -64,6 +64,7 @@ static void
On Wed, Sep 08, 2021 at 10:32:27AM +0200, Philippe Mathieu-Daudé wrote:
> On 9/8/21 10:19 AM, Yang Zhong wrote:
> > Add the sgx_get_info() interface for hmp and QMP usage, which
> > will get the SGX info from this API.
> >
> > Signed-off-by: Yang Zhong
> > ---
> > hw/i386/sgx.c | 21
Commit 5e8892db93 fixed several function signatures but tcg_out_vec_op
for arm is missing. It causes a build error on armv6 and armv7:
tcg-target.c.inc:2718:42: error: argument 5 of type 'const TCGArg *'
{aka 'const unsigned int *'} declared as a pointer [-Werror=array-parameter=]
const TCGArg
On 9/8/21 8:53 PM, Jose R. Ziviani wrote:
> Commit 5e8892db93 fixed several function signatures but tcg_out_vec_op
> for arm is missing. It causes a build error on armv6 and armv7:
>
> tcg-target.c.inc:2718:42: error: argument 5 of type 'const TCGArg *'
> {aka 'const unsigned int *'} declared as
On Wed, Sep 08, 2021 at 05:08:08PM +0100, Daniel P. Berrangé wrote:
> Given the libvirt XML snippet
>
>
> ...
>
> ...
>
>
> libvirt QEMU driver will always format
>
> -device sga
>
> Libguestfs uses this syntax, so we need to make sure it still works
> in future even if
On Wed, Sep 08, 2021 at 05:25:50PM -0300, Leonardo Bras Soares Passos wrote:
> On Tue, Sep 7, 2021 at 8:06 AM Dr. David Alan Gilbert
> wrote:
> > > Possibly, yes. This really need David G's input since he understands
> > > the code in way more detail than me.
> >
> > Hmm I'm not entirely sure why
Signed-off-by: Philippe Mathieu-Daudé
---
hw/hyperv/hyperv_testdev.c | 1 +
hw/misc/pc-testdev.c | 1 +
hw/misc/pci-testdev.c | 1 +
3 files changed, 3 insertions(+)
diff --git a/hw/hyperv/hyperv_testdev.c b/hw/hyperv/hyperv_testdev.c
index 9a56ddf83fe..6a75c350389 100644
---
On Wed, Sep 8, 2021 at 6:45 AM Jason Wang wrote:
>
> On Tue, Sep 7, 2021 at 6:40 PM Yuri Benditovich
> wrote:
> >
> > On Wed, Sep 1, 2021 at 9:42 AM Jason Wang wrote:
> > >
> > >
> > > 在 2021/8/31 上午1:07, Yuri Benditovich 写道:
> > > > On Fri, Aug 20, 2021 at 6:41 AM Jason Wang wrote:
> > > >>
>
On Mon, Sep 06, 2021 at 03:01:54PM +0200, Philippe Mathieu-Daudé wrote:
> On 9/6/21 2:20 PM, Bin Meng wrote:
> > It's been a requirement that at least one function pointer for read
> > and one for write are provided ever since the MemoryRegion APIs were
> > introduced in 2012.
> >
> >
Hi,
On Wed, 1 Sep 2021 15:39:10 +0100
Peter Maydell wrote:
> Coverity points out that if the PDB file we're trying to read
> has a header specifying a block_size of zero then we will
> end up trying to divide by zero in pdb_ds_read_file().
> Check for this and fail cleanly instead.
>
> Fixes:
On Wed, Sep 08, 2021 at 05:13:40PM -0300, Leonardo Bras Soares Passos wrote:
> On Tue, Sep 7, 2021 at 1:44 PM Peter Xu wrote:
> >
> > On Thu, Sep 02, 2021 at 03:59:25AM -0300, Leonardo Bras Soares Passos wrote:
> > > I also suggested something like that, but I thought it could be good if
> > >
Hi,
On Wed, 1 Sep 2021 17:25:09 +0200
Philippe Mathieu-Daudé wrote:
> On 9/1/21 4:39 PM, Peter Maydell wrote:
> > Coverity points out that we aren't checking the return value
> > from curl_easy_setopt().
> >
> > Fixes: Coverity CID 1458895
> > Signed-off-by: Peter Maydell
> > ---
> >
On Wed, Sep 08, 2021 at 01:05:13PM -0500, Eric Blake wrote:
> On Wed, Sep 08, 2021 at 11:37:09AM +0100, Daniel P. Berrangé wrote:
> > Signed-off-by: Daniel P. Berrangé
> > ---
> > target/i386/cpu-dump.c | 325 ++---
> > target/i386/cpu.c | 2 +-
> >
Add DeviceClass::taints_security_policy field to allow an
unsafe device to eventually taint the global security policy
in DeviceRealize().
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/qdev-core.h | 6 ++
hw/core/qdev.c | 11 +++
2 files changed, 17 insertions(+)
Signed-off-by: Philippe Mathieu-Daudé
---
hw/display/artist.c | 1 +
hw/display/ati.c| 1 +
2 files changed, 2 insertions(+)
diff --git a/hw/display/artist.c b/hw/display/artist.c
index 21b7fd1b440..067a4b2cb59 100644
--- a/hw/display/artist.c
+++ b/hw/display/artist.c
@@ -1482,6 +1482,7 @@
On Thu, Sep 9, 2021 at 8:00 AM Yuri Benditovich
wrote:
>
> On Wed, Sep 8, 2021 at 6:45 AM Jason Wang wrote:
> >
> > On Tue, Sep 7, 2021 at 6:40 PM Yuri Benditovich
> > wrote:
> > >
> > > On Wed, Sep 1, 2021 at 9:42 AM Jason Wang wrote:
> > > >
> > > >
> > > > 在 2021/8/31 上午1:07, Yuri
On Wed, Sep 08, 2021 at 10:57:06PM +0100, Daniel P. Berrangé wrote:
> We think we're probably ok with migration as we are going to rely on the
> face that we eventually pause the guest to stop page changes during the
> final switchover. None the less I really strongly dislike the idea of
> not
VMDK files support an attribute that represents the version of the guest
tools that are installed on the disk.
This attribute is used by vSphere before a machine has been started to
determine if the VM has the guest tools installed.
This is important when configuring "Operating system
On Wed, Sep 08, 2021 at 10:50:53PM +0200, Gerd Hoffmann wrote:
> On Wed, Sep 08, 2021 at 05:08:08PM +0100, Daniel P. Berrangé wrote:
> > Given the libvirt XML snippet
> >
> >
> > ...
> >
> > ...
> >
> >
> > libvirt QEMU driver will always format
> >
> > -device sga
> >
> >
On 9/8/21 11:43 PM, Viktor Prutyanov wrote:
> On Wed, 1 Sep 2021 17:25:09 +0200
> Philippe Mathieu-Daudé wrote:
>
>> On 9/1/21 4:39 PM, Peter Maydell wrote:
>>> Coverity points out that we aren't checking the return value
>>> from curl_easy_setopt().
>>>
>>> Fixes: Coverity CID 1458895
>>>
On Wed, Sep 8, 2021 at 11:19 PM Peter Xu wrote:
>
> On Wed, Sep 08, 2021 at 09:19:27AM +0100, Dr. David Alan Gilbert wrote:
> > * Jason Wang (jasow...@redhat.com) wrote:
> > > On Wed, Sep 8, 2021 at 2:32 AM Peter Xu wrote:
> > > >
> > > > On Thu, Sep 02, 2021 at 04:22:55AM -0300, Leonardo Bras
On Wed, Sep 08, 2021 at 10:34:39AM +0200, Philippe Mathieu-Daudé wrote:
> On 9/8/21 10:19 AM, Yang Zhong wrote:
> > The Qemu should enable bit mask macro like Linux did in the
> > kernel, the GENMASK(h, l) and GENMASK_ULL(h, l) will set the
> > bit to 1 from l to h bit in the 32 bit or 64 bit long
On Tue, Sep 7, 2021 at 1:44 PM Peter Xu wrote:
>
> On Thu, Sep 02, 2021 at 03:59:25AM -0300, Leonardo Bras Soares Passos wrote:
> > I also suggested something like that, but I thought it could be good if we
> > could
> > fall back to io_writev() if we didn't have the zerocopy feature (or
> > the
On Fri, 3 Sep 2021 17:36:11 +0800
Kunkun Jiang wrote:
> The MSI-X structures of some devices and other non-MSI-X structures
> are in the same BAR. They may share one host page, especially in the
> case of large page granularity, suck as 64K.
s/suck/such/
> For example, MSIX-Table size of 82599
On Fri, 3 Sep 2021 17:36:10 +0800
Kunkun Jiang wrote:
> We expand MemoryRegions of vfio-pci sub-page MMIO BARs to
> vfio_pci_write_config to improve IO performance.
> The MemoryRegions of destination VM will not be expanded
> successful in live migration, because their addresses have
> been
On Wed, Sep 08, 2021 at 05:09:33PM -0400, Peter Xu wrote:
> On Wed, Sep 08, 2021 at 05:25:50PM -0300, Leonardo Bras Soares Passos wrote:
> > On Tue, Sep 7, 2021 at 8:06 AM Dr. David Alan Gilbert
> > wrote:
> > > > Possibly, yes. This really need David G's input since he understands
> > > > the
See commit b317006a3f1 ("docs/secure-coding-practices: Describe how
to use 'null-co' block driver") for rationale.
Signed-off-by: Philippe Mathieu-Daudé
---
block/null.c | 8
1 file changed, 8 insertions(+)
diff --git a/block/null.c b/block/null.c
index cc9b1d4ea72..11e428f3cc2 100644
Add the BlockDriver::bdrv_taints_security_policy() handler.
Drivers implementing it might taint the global QEMU security
policy.
Signed-off-by: Philippe Mathieu-Daudé
---
include/block/block_int.h | 6 +-
block.c | 6 ++
2 files changed, 11 insertions(+), 1 deletion(-)
While being listed as 'supported' in MAINTAINERS, this driver
does not have many reviewers and contains various /* TODO */
unattended since various years. Not safe enough for production
environment, so have it taint the global security policy.
Signed-off-by: Philippe Mathieu-Daudé
---
Signed-off-by: Philippe Mathieu-Daudé
---
hw/net/tulip.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/net/tulip.c b/hw/net/tulip.c
index ca69f7ea5e1..eaad3266212 100644
--- a/hw/net/tulip.c
+++ b/hw/net/tulip.c
@@ -1025,6 +1025,7 @@ static void tulip_class_init(ObjectClass *klass, void
Hi
On Wed, Sep 8, 2021 at 8:51 PM Ian Jackson wrote:
> Marc-André Lureau writes ("Re: [RFC v3 13/32] rust: use vendored-sources"):
> > Yes, this is the shim to provide a C ABI QMP handler from Rust. This is
> where
> > all the FFI<->Rust conversion takes place.
> >
> > The "safe" code is
On 9/8/21 8:50 PM, Peter Xu wrote:
> On Mon, Sep 06, 2021 at 03:01:54PM +0200, Philippe Mathieu-Daudé wrote:
>> On 9/6/21 2:20 PM, Bin Meng wrote:
>>> It's been a requirement that at least one function pointer for read
>>> and one for write are provided ever since the MemoryRegion APIs were
>>>
> -Original Message-
> From: Eric Blake
> Sent: Wednesday, September 8, 2021 7:56 PM
> To: Weissschuh, Thomas [ext]
> Cc: Fam Zheng ; Kevin Wolf ; Hanna Reitz
> ; Markus Armbruster ; qemu-
> bl...@nongnu.org; tho...@t-8ch.de; qemu-devel@nongnu.org
> Subject: Re: [PATCH] vmdk: allow
On Mon, Aug 30, 2021 at 3:54 AM Alexey Baturo wrote:
>
> Signed-off-by: Alexey Baturo
> ---
> target/riscv/cpu.c | 6 +
> target/riscv/cpu.h | 11 ++
> target/riscv/csr.c | 276 +
> 3 files changed, 293 insertions(+)
>
> diff --git
On Wed, Sep 08, 2021 at 10:38:59AM +0200, Philippe Mathieu-Daudé wrote:
> On 9/8/21 10:19 AM, Yang Zhong wrote:
> > Libvirt can use qmp_query_sgx_capabilities() to get the host
> > sgx capabilities.
> >
> > Signed-off-by: Yang Zhong
> > ---
> > hw/i386/sgx.c | 66
On Thu, 9 Sep 2021, Philippe Mathieu-Daudé wrote:
> Fix 'hotplugabble' -> 'hotpluggabble' typo.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Ani Sinha
> ---
> hw/i386/acpi-build.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/hw/i386/acpi-build.c
From: Alistair Francis
This is the initial commit of the SiFive PWM timer. This is used by
guest software as a timer and is included in the SiFive FU540 SoC.
Signed-off-by: Justin Restivo
Signed-off-by: Alexandra Clifford
Signed-off-by: Amanda Strnad
Signed-off-by: Alistair Francis
---
On Thu, Sep 9, 2021 at 11:55 AM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> Connect the SiFive PWM device and expose it via the device tree.
>
> Signed-off-by: Alistair Francis
> ---
> docs/system/riscv/sifive_u.rst | 1 +
> include/hw/riscv/sifive_u.h| 14 -
>
Daniel P. Berrangé writes:
> On Wed, Sep 08, 2021 at 05:09:13PM +0200, Markus Armbruster wrote:
>> Daniel P. Berrangé writes:
>>
>> > We are still adding HMP commands without any QMP counterparts. This is
>> > done because there are a reasonable number of scenarios where the cost
>> > of
On Wed, Sep 8, 2021 at 11:05 PM Peter Xu wrote:
>
> On Wed, Sep 08, 2021 at 10:57:06PM +0100, Daniel P. Berrangé wrote:
> > We think we're probably ok with migration as we are going to rely on the
> > face that we eventually pause the guest to stop page changes during the
> > final switchover.
On Thu, Sep 09, 2021 at 05:35:40AM +, John Johnson wrote:
>
>
> > On Sep 7, 2021, at 7:31 AM, Stefan Hajnoczi wrote:
> >
> > On Mon, Aug 16, 2021 at 09:42:41AM -0700, Elena Ufimtseva wrote:
> >> @@ -1514,6 +1515,16 @@ bool vfio_get_info_dma_avail(struct
> >> vfio_iommu_type1_info *info,
>
在 2021/9/2 下午1:44, Jason Wang 写道:
When mergeable buffer is enabled, we try to set the num_buffers after
the virtqueue elem has been unmapped. This will lead several issues,
E.g a use after free when the descriptor has an address which belongs
to the non direct access region. In this case we
> On Sep 7, 2021, at 8:14 AM, Stefan Hajnoczi wrote:
>
> On Mon, Aug 16, 2021 at 09:42:44AM -0700, Elena Ufimtseva wrote:
>> From: John Johnson
>>
>> Signed-off-by: Elena Ufimtseva
>> Signed-off-by: John G Johnson
>> Signed-off-by: Jagannathan Raman
>> ---
>> hw/vfio/user-protocol.h | 25
On Wed, Sep 08, 2021 at 09:52:40AM -0500, Eric Blake wrote:
> On Wed, Sep 08, 2021 at 12:03:56PM +0200, Paolo Bonzini wrote:
> > From: Sean Christopherson
> >
> > Because SGX EPC is enumerated through CPUID, EPC "devices" need to be
> > realized prior to realizing the vCPUs themselves, i.e. long
From: Alistair Francis
Connect the SiFive PWM device and expose it via the device tree.
Signed-off-by: Alistair Francis
---
docs/system/riscv/sifive_u.rst | 1 +
include/hw/riscv/sifive_u.h| 14 -
hw/riscv/sifive_u.c| 55 +-
From: Alistair Francis
This series adds a the SiFive PWM device and connects it to the
sifive_u machine. This has been tested as a timer with seL4.
v3:
- Small fixups
v2:
- Address Bin's comments
- Expose PWM via the device tree
Alistair Francis (2):
hw/timer: Add SiFive PWM support
On Mon, Aug 30, 2021 at 3:51 AM Alexey Baturo wrote:
>
> Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu_bits.h | 96 +
> 1 file changed, 96 insertions(+)
>
> diff --git a/target/riscv/cpu_bits.h
> On Sep 7, 2021, at 7:31 AM, Stefan Hajnoczi wrote:
>
> On Mon, Aug 16, 2021 at 09:42:41AM -0700, Elena Ufimtseva wrote:
>> @@ -1514,6 +1515,16 @@ bool vfio_get_info_dma_avail(struct
>> vfio_iommu_type1_info *info,
>> return true;
>> }
>>
>> +static int
On Wed, Sep 8, 2021 at 1:46 PM Paolo Bonzini wrote:
>
> On 08/09/21 05:08, Jason Wang wrote:
> >
> > 在 2021/9/7 下午6:45, Paolo Bonzini 写道:
> >> eBPF files are being included in system emulators, which is useless
> >
> >
> > I think it should work since it's an independent feature. The current
> >
On Thu, Sep 9, 2021 at 11:55 AM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> This is the initial commit of the SiFive PWM timer. This is used by
> guest software as a timer and is included in the SiFive FU540 SoC.
>
> Signed-off-by: Justin Restivo
> Signed-off-by: Alexandra Clifford
> On Sep 7, 2021, at 6:21 AM, Stefan Hajnoczi wrote:
>
>
> This way the network communication code doesn't need to know how
> messages will by processed by the client or server. There is no need for
> if (isreply) { qemu_cond_signal(>cv); } else {
> proxy->request(proxy->reqarg, buf, ); }.
Le 30/08/2021 à 12:24, Mark Cave-Ayland a écrit :
> The PRAM contents are accessed using clock and data pins on q800 VIA1 port B
> and so can be moved to MOS6522Q800VIA1State.
>
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/misc/mac_via.c | 59 ---
>
Le 30/08/2021 à 12:24, Mark Cave-Ayland a écrit :
> Now that q800 VIA1 and VIA2 are completely separate devices there is no need
> to
> add a specific device prefix to ensure that the IRQ lines remain separate.
>
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/m68k/q800.c| 10 --
>
On Fri, 3 Sep 2021 13:06:42 +0200
Philippe Mathieu-Daudé wrote:
> acpi_data_len() returns an unsigned type, which might be bigger
> than 32-bit (although it is unlikely such value is returned).
> Hold the returned value in an 'unsigned' type to avoid unlikely
> size truncation.
>
>
Hi
On 9/7/21 2:58 PM, Peter Maydell wrote:
> On Sun, 22 Aug 2021 at 15:45, Marc Zyngier wrote:
>> Even when the VM is configured with highmem=off, the highest_gpa
>> field includes devices that are above the 4GiB limit, which is
>> what highmem=off is supposed to enforce. This leads to failures
On Sun, Sep 5, 2021 at 10:08 AM Guenter Roeck wrote:
>
> On 9/4/21 4:19 PM, Philippe Mathieu-Daudé wrote:
> > On 9/5/21 1:06 AM, Bin Meng wrote:
> >> On Sun, Sep 5, 2021 at 1:13 AM Guenter Roeck wrote:
> >>>
> >>> On 9/2/21 12:29 PM, Peter Maydell wrote:
> On Thu, 2 Sept 2021 at 17:09,
On 9/7/21 8:08 PM, Taylor Simpson wrote:
diff --git a/target/hexagon/idef-parser/parser-helpers.h
b/target/hexagon/idef-parser/parser-helpers.h
+#define OUT_IMPL(c, locp, x)\
+_Generic(*x,\
+char: str_print, \
Le 30/08/2021 à 12:24, Mark Cave-Ayland a écrit :
> These variables are already present in MOS6522Q800VIA1State and so it is just
> the VMStateDescription move that is needed.
>
> With this change the mac_via VMStateDescription is now empty and can be
> removed
> completely.
>
> Signed-off-by:
On Fri, 3 Sep 2021 13:06:43 +0200
Philippe Mathieu-Daudé wrote:
> Per
> https://discourse.gnome.org/t/port-your-module-from-g-memdup-to-g-memdup2-now/5538
>
> The old API took the size of the memory to duplicate as a guint,
> whereas most memory functions take memory sizes as a gsize.
On 07/09/21 11:51, Yang Zhong wrote:
Paolo, I have moved hmp and qmp codes to target/i386/monitor.c and also
fixed the issue with test tool(tests/qtest/test-hmp). This issue is caused
by 'machine none' test in the hmp, the previous patches only covered qmp
test in 'machine none'
On Tue, Aug 31, 2021 at 7:07 PM Anup Patel wrote:
>
> The RISC-V ACLINT is more modular and backward compatible with
> original SiFive CLINT so instead of duplicating the original
> SiFive CLINT implementation we upgrade the current SiFive CLINT
> implementation to RISC-V ACLINT implementation.
>
On 9/8/21 6:54 AM, Alistair Francis wrote:
From: Alistair Francis
Signed-off-by: Alistair Francis
---
target/riscv/translate.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index e356fc6c46..25670be435
On Wed, Sep 8, 2021 at 2:29 PM Bin Meng wrote:
>
> On Sun, Sep 5, 2021 at 10:08 AM Guenter Roeck wrote:
> >
> > On 9/4/21 4:19 PM, Philippe Mathieu-Daudé wrote:
> > > On 9/5/21 1:06 AM, Bin Meng wrote:
> > >> On Sun, Sep 5, 2021 at 1:13 AM Guenter Roeck wrote:
> > >>>
> > >>> On 9/2/21 12:29
Le 30/08/2021 à 12:24, Mark Cave-Ayland a écrit :
> Move the parent mos6522 objects from vmstate_mac_via into the new
> VMStateDescription
> structures to begin the process of splitting MacVIAState into separate VIA1
> and
> VIA2 devices.
>
> Signed-off-by: Mark Cave-Ayland
> ---
>
Le 30/08/2021 à 12:24, Mark Cave-Ayland a écrit :
> This variable is already present in MOS6522Q800VIA1State and can be moved
> immediately into the q800 VIA1 VMStateDescription.
>
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/misc/mac_via.c | 2 +-
> 1 file changed, 1 insertion(+), 1
On 9/8/21 6:54 AM, Alistair Francis wrote:
@@ -967,6 +967,16 @@ void riscv_cpu_do_interrupt(CPUState *cs)
write_tval = true;
tval = env->badaddr;
break;
+case RISCV_EXCP_ILLEGAL_INST:
+if (riscv_feature(env,
Le 30/08/2021 à 12:24, Mark Cave-Ayland a écrit :
> Remove the mac_via device and wire up both q800 VIA1 and VIA2 directly for the
> m68k q800 machine.
>
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/m68k/q800.c| 34 +
> hw/misc/mac_via.c | 78
Le 30/08/2021 à 12:24, Mark Cave-Ayland a écrit :
> These will soon be required to enable nubus devices to support interrupts.
>
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/misc/mac_via.c | 23 +++
> include/hw/misc/mac_via.h | 10 ++
> 2 files changed, 33
On Wed, 8 Sep 2021, Igor Mammedov wrote:
> On Wed, 8 Sep 2021 09:41:39 +0530
> Ani Sinha wrote:
>
> > Change caf108bc58790 ("hw/i386/acpi-build: Add ACPI PCI hot-plug methods to
> > Q35")
> > selects an IO address range for acpi based PCI hotplug for q35 arbitrarily.
> > It
> > starts at
On 9/8/21 7:47 AM, Paolo Bonzini wrote:
> On 07/09/21 20:19, Philippe Mathieu-Daudé wrote:
>> Fixes: 217f1b4a721 ("target-i386: Publish advised value of
>> MSR_IA32_FEATURE_CONTROL via fw_cfg")
>
> Yes, thanks.
Reviewed-by: Philippe Mathieu-Daudé
07.09.2021 23:51, Eric Blake wrote:
+def check_fail_to_connect(open_timeout):
+log(f'Check fail to connect with {open_timeout} seconds of timeout')
+
+start_t = time.time()
+qemu_io_log(*create_args(open_timeout))
+delta_t = time.time() - start_t
+
+max_delta = open_timeout +
On 07/09/21 15:40, Thomas Huth wrote:
we should maybe have a pointer to the information on
https://www.qemu.org/contribute/ instead?
Yes - right now contribute/ links to the old blog post for "Improve the
web site", but I guess it couuld just go to
On 07/09/21 13:08, Alexander Bulekov wrote:
-if [ "$GITLAB_CI" != "true" ]; then
+if [ -z ${GITLAB_CI+x} ]; then
I would slightly prefer to have "${GITLAB_CI+x}", since "test" in
general doesn't like parameters that go away:
$ [ = abc ]
bash: [: =: unary operator expected
What you wrote
Le 30/08/2021 à 12:24, Mark Cave-Ayland a écrit :
> The PRAM/RTC is accessed using clock and data pins on q800 VIA1 port B and so
> can be moved to MOS6522Q800VIA1State.
>
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/misc/mac_via.c | 135 +++---
>
Hi
On Wed, Sep 8, 2021 at 8:54 AM Markus Armbruster wrote:
> Markus Armbruster (5):
> qapi: Fix a botched type annotation
> qapi: Drop Indentation.__bool__()
> qapi: Bury some unused code in class Indentation
> tests/qapi-schema: Cover 'not' condition with empty argument
> qapi: Fix
Le 30/08/2021 à 12:24, Mark Cave-Ayland a écrit :
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/misc/mac_via.c | 86 ---
> 1 file changed, 44 insertions(+), 42 deletions(-)
>
Reviewed-by: Laurent Vivier
Hi Marc,
On 8/22/21 4:44 PM, Marc Zyngier wrote:
> Although we probe for the IPA limits imposed by KVM (and the hardware)
> when computing the memory map, we still use the old style '0' when
> creating a scratch VM in kvm_arm_create_scratch_host_vcpu().
>
> On systems that are severely IPA
On Wed, 8 Sep 2021 09:41:39 +0530
Ani Sinha wrote:
> Change caf108bc58790 ("hw/i386/acpi-build: Add ACPI PCI hot-plug methods to
> Q35")
> selects an IO address range for acpi based PCI hotplug for q35 arbitrarily. It
> starts at address 0x0cc4 and ends at 0x0cdb. It was assumed that this
Le 30/08/2021 à 12:24, Mark Cave-Ayland a écrit :
> The ADB is accessed using clock and data pins on q800 VIA1 port B and so can
> be
> moved to MOS6522Q800VIA1State.
>
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/m68k/q800.c| 6 +-
> hw/misc/mac_via.c | 169
Le 30/08/2021 à 12:24, Mark Cave-Ayland a écrit :
> After this change mac_via_reset() is now empty and can be removed.
>
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/misc/mac_via.c | 22 --
> 1 file changed, 8 insertions(+), 14 deletions(-)
Reviewed-by: Laurent Vivier
Le 30/08/2021 à 12:24, Mark Cave-Ayland a écrit :
> Also improve the alignment of the shifted constants.
>
> Signed-off-by: Mark Cave-Ayland
> ---
> include/hw/misc/mac_via.h | 22 +++---
> 1 file changed, 11 insertions(+), 11 deletions(-)
>
Reviewed-by: Laurent Vivier
* Jason Wang (jasow...@redhat.com) wrote:
> On Wed, Sep 8, 2021 at 2:32 AM Peter Xu wrote:
> >
> > On Thu, Sep 02, 2021 at 04:22:55AM -0300, Leonardo Bras Soares Passos wrote:
> > > > I don't think it is valid to unconditionally enable this feature due to
> > > > the
> > > > resource usage
On 9/8/21 10:19 AM, Yang Zhong wrote:
> Add the sgx_get_info() interface for hmp and QMP usage, which
> will get the SGX info from this API.
>
> Signed-off-by: Yang Zhong
> ---
> hw/i386/sgx.c | 21 +
> include/hw/i386/sgx.h | 11 +++
> target/i386/monitor.c
On 08/09/21 10:19, Yang Zhong wrote:
+if (sgx_enabled) {
+MachineState *ms = MACHINE(qdev_get_machine());
+X86MachineState *x86ms = X86_MACHINE(qdev_get_machine());
+
You can use object_dynamic_cast(ms, TYPE_PC_MACHINE), something like:
PCMachineState *pcms =
On Tue, Sep 07, 2021 at 06:20:33PM +0200, Philippe Mathieu-Daudé wrote:
> On 7/18/21 3:46 PM, Reinoud Zandijk wrote:
> > Userland targers will otherwise use a poisoned CONFIG_NVMM
>
> Typo "targets", but do you mean bsd-user or linux-user?
Since its on NetBSD, I guess its bsd-user :)
> But what
On Wed, 8 Sept 2021 at 03:50, Duo jia wrote:
> Also I want to know how to make a delay in qemu.
> For example, when I send a UART data, there is a certain time interval from
> setting the register to when the data is sent. Most of this time does not
> affect the simulation effect, but some
On Mon, Aug 16, 2021 at 09:42:47AM -0700, Elena Ufimtseva wrote:
> diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
> index 2c9fcb2fa9..29a874c066 100644
> --- a/hw/vfio/pci.c
> +++ b/hw/vfio/pci.c
> @@ -3406,11 +3406,72 @@ type_init(register_vfio_pci_dev_type)
> * vfio-user routines.
> */
>
>
On Mon, Sep 06, 2021 at 04:57:39PM +0200, Eric Auger wrote:
> Hi Jean,
>
> On 9/3/21 4:32 PM, Jean-Philippe Brucker wrote:
> > From: Eric Auger
> >
> > Add a hotplug handler for virtio-iommu on x86 and set the necessary
> > reserved region property. On x86, the [0xfee0, 0xfeef] DMA
> >
On Mon, Aug 16, 2021 at 09:42:48AM -0700, Elena Ufimtseva wrote:
> From: John Johnson
>
> Signed-off-by: Elena Ufimtseva
> Signed-off-by: John G Johnson
> Signed-off-by: Jagannathan Raman
> ---
> hw/vfio/user.h | 1 +
> hw/vfio/pci.c | 29 ++---
> hw/vfio/user.c |
The following changes since commit f9128631fbeb40a55f7bc145397981c963d40909:
Merge remote-tracking branch
'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2021-09-07
13:24:43 +0100)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git
From: Lara Lazier
APM2 requires that VMRUN and VMLOAD canonicalize (sign extend to 63
from 48/57) all base addresses in the segment registers that have been
respectively loaded.
Signed-off-by: Lara Lazier
Message-Id: <20210804113058.45186-1-laramglaz...@gmail.com>
Signed-off-by: Paolo Bonzini
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