Allow changes to the virt GTDT -- we are going to add the IRQ
entry for a new timer to it.
Signed-off-by: Peter Maydell
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
Armv8.1+ CPUs have the Virtual Host Extension (VHE) which adds
a non-secure EL2 virtual timer. We implemented the timer itself
in the CPU model, but never wired up its IRQ line to the GIC.
Wire up the IRQ line (this is always safe whether the CPU has the
interrupt or not, since it always creates
This patchset is an RFC that wires up the NS EL2 virtual timer IRQ on
the virt board, similarly to what
https://patchew.org/QEMU/20230913140610.214893-1-marcin.juszkiew...@linaro.org/
does for the sbsa-ref board.
Patches 1 and 3 are the usual dance to keep the ACPI unit tests happy
with the
Update the virt/GTDT golden reference file to be a
revision 3 table with space for the virtual EL2 timer.
Diffs from iasl:
@@ -1,32 +1,32 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64-bit version)
* Copyright (c) 2000 - 2020 Intel Corporation
*
-
This has been missing from the start. Assume it should match
with cxl/cxl-component-utils.c as both were part of early
postings from Ben.
Suggested-by: Philippe Mathieu-Daudé
Acked-by: Dave Jiang
Acked-by: Ira Weiny
Reviewed-by: Fan Ni
Signed-off-by: Jonathan Cameron
---
v2:
- Add similar
v2:
- Tag collection.
- Patch 2 discussion on appropriate license concluded that this should
have originally only been accepted on GPL-v2 and later. However, I've
left it as GPL-v2-only as that is what was used for other CXL files and
for the license to be usefully relaxed we need to do
From: Dmitry Frolov
According to cxl_interleave_ways_enc(), fw->num_targets is allowed to be up
to 16. This also corresponds to CXL r3.0 spec. So, the fw->target_hbs[]
array is iterated from 0 to 15. But it is statically declared of length 8.
Thus, out of bound array access may occur.
Fixes:
These crossed with the previous fix to get rid of examples
using aarch64 for which support is not yet upstream.
Reviewed-by: Fan Ni
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1892
Signed-off-by: Jonathan Cameron
---
docs/system/devices/cxl.rst | 4 ++--
1 file changed, 2
Same as with the x86 verison of this test, we relied on the contents of
all pages in RAM to be the same across the entire test range, which is
very fragile. Zero the first byte of each page before running the
increment loop to fix this.
Fixes: 5571dc824b ("tests/migration: Enable the migration
The migration qtest all the way up to this point used to work by sheer
luck relying on the contents of all pages from 1MiB to 100MiB to contain
the same one value in the first byte initially.
This easily breaks if we reduce the amount of RAM for the test instances
from 150MiB to e.g 110MiB since
This series fixes an issue where the outcome of the migration qtest
relies on the initial memory contents all being the same across the
first 100MiB of RAM, which is a very fragile invariant.
We fix this by making sure we zero the first byte of every testable page
in range beforehand.
Changes
So that we have less magic numbers to deal with. This also allows us to
reuse these in the following commits.
Signed-off-by: Daniil Tatianin
Reviewed-by: Peter Xu
---
tests/migration/i386/a-b-bootblock.S | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git
Am 18.09.2023 um 20:56 hat Stefan Hajnoczi geschrieben:
> Hi Kevin,
> I believe that my own commit "block-coroutine-wrapper: use
> qemu_get_current_aio_context()" breaks this test. The failure is
> non-deterministic (happens about 1 out of 4 runs).
>
> It seems the job hangs and the test times
The following changes since commit 13d6b1608160de40ec65ae4c32419e56714bbadf:
Merge tag 'pull-crypto-20230915' of https://gitlab.com/rth7680/qemu into
staging (2023-09-18 11:04:21 -0400)
are available in the Git repository at:
https://github.com/davidhildenbrand/qemu.git tags/mem-2023-09-19
Currently, when using a true R/O NVDIMM (ROM memory backend) with a label
area, the VM can easily crash QEMU by trying to write to the label area,
because the ROM memory is mmap'ed without PROT_WRITE.
[root@vm-0 ~]# ndctl disable-region region0
disabled 1 region
[root@vm-0 ~]# ndctl
Let's remap with the proper protection that we can derive from
RAM_READONLY.
Message-ID: <20230906120503.359863-5-da...@redhat.com>
Reviewed-by: Peter Xu
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: David Hildenbrand
---
softmmu/physmem.c | 10 ++
1 file changed, 6
It's easy to miss that memory-backend-file with "share=off" (default)
will always try opening the file R/W as default, and fail if we don't
have write permissions to the file.
In that case, the user has to explicit specify "readonly=on,rom=off" to
get usable RAM, for example, for VM templating.
For now, "share=off,readonly=on" would always result in us opening the
file R/O and mmap'ing the opened file MAP_PRIVATE R/O -- effectively
turning it into ROM.
Especially for VM templating, "share=off" is a common use case. However,
that use case is impossible with files that lack write
Currently, if a file does not exist yet, file_ram_open() will create new
empty file and open it writable. However, it even does that when
readonly=true was specified.
Specifying O_RDONLY instead to create a new readonly file would
theoretically work, however, ftruncate() will refuse to resize the
"-mem-path" corresponds to "memory-backend-file,share=off" and,
therefore, creates a private COW mapping of the file. For multi-proces
QEMU, we need proper shared file-backed memory.
Let's make that clearer.
Message-ID: <20230906120503.359863-9-da...@redhat.com>
Signed-off-by: David Hildenbrand
Let's add some details about VM templating, focusing on the VM memory
configuration only.
There is much more to VM templating (VM state? block devices?), but I leave
that as future work.
Message-ID: <20230906120503.359863-10-da...@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by:
For migration purposes, users might want to reuse the default RAM
backend id, but specify a different memory backend.
For example, to reuse "pc.ram" on q35, one has to set
-machine q35,memory-backend=pc.ram
Only then, can a memory backend with the id "pc.ram" be created
manually.
Let's
fallocate() will fail, let's print a nicer error message.
Message-ID: <20230906120503.359863-6-da...@redhat.com>
Suggested-by: Peter Xu
Reviewed-by: Peter Xu
Signed-off-by: David Hildenbrand
---
softmmu/physmem.c | 10 ++
1 file changed, 10 insertions(+)
diff --git
From: hongmianquan
When updating ioeventfds, we need to iterate all address spaces,
but some address spaces do not register eventfd_add|del call when
memory_listener_register() and they do nothing when updating ioeventfds.
So we can skip these AS in address_space_update_ioeventfds().
The
open() does not fail on directories when opening them readonly (O_RDONLY).
Currently, we succeed opening such directories and fail later during
mmap(), resulting in a misleading error message.
$ ./qemu-system-x86_64 \
-object memory-backend-file,id=ram0,mem-path=tmp,readonly=true,size=1g
There is a difference between how we open a file and how we mmap it,
and we want to support writable private mappings of readonly files. Let's
define RAM_READONLY and RAM_READONLY_FD flags, to replace the single
"readonly" parameter for file-related functions.
In memory_region_init_ram_from_fd()
On 15/9/23 18:11, Akihiko Odaki wrote:
On 2023/09/15 20:11, Huang Rui wrote:
From: Xenia Ragiadakou
When the memory region has a different life-cycle from that of her
parent,
could be automatically released, once has been unparent and once all
of her
references have gone away, via the
32-bit systems do not have a reserved memory for hole64 and memory hotplug is
not supported on those systems. Therefore, the maximum limit of the guest
physical address coincides with the end of "above 4G memory space" region.
Make sure that the end of "above 4G memory" is still addressible by the
On 2023/09/19 19:28, Xenia Ragiadakou wrote:
On 15/9/23 18:11, Akihiko Odaki wrote:
On 2023/09/15 20:11, Huang Rui wrote:
From: Xenia Ragiadakou
When the memory region has a different life-cycle from that of her
parent,
could be automatically released, once has been unparent and once all
When guest vm does S3, Qemu will reset and clear some things of virtio
devices, but guest can't aware that, so that may cause some problems.
For excample, Qemu calls virtio_reset->virtio_gpu_gl_reset, that will
destroy render resources of virtio-gpu. As a result, after guest resume,
the display
On 15.09.23 18:20, Andrey Drobyshev wrote:
When rebasing an image from one backing file to another, we need to
compare data from old and new backings. If the diff between that data
happens to be unaligned to the target cluster size, we might end up
doing partial writes, which would lead to
When we suspended guest VM, it called into Qemu to call
virtio_reset->__virtio_queue_reset, this cleared all virtqueue information
of virtgpu on Qemu end, but guest kernel still keep the virtqueus. As a
result, after guest resumed, if guest sent ctrl/cursor requests to Qemu
through virtqueue, but
On 9/7/23 07:32, Nicholas Piggin wrote:
On Wed Sep 6, 2023 at 2:33 PM AEST, Harsh Prateek Bora wrote:
This patch implements nested PAPR hcall H_GUEST_GET_CAPABILITIES and
also enables registration of nested PAPR hcalls whenever an L0 is
launched with cap-nested-papr=true. The common
Hi all,
This is the v5 of kernel patches and v5 makes below changes:
* Since this series patches add a new mechanism that let virtgpu and Qemu can
negotiate
their reset behavior, and other guys hope me can improve this mechanism to
virtio pci
level, so that other virtio devices can also
Am 18.09.2023 um 19:28 hat John Levon geschrieben:
>
> Observed with base of qemu 6.2.0, but from code inspection it looks to me like
> it's still current in upstream master. Apologies if I have missed a fix in
> this
> area.
>
> Symptom: run a UEFI-booted SATA CD Windows installer. When it
Hi
On Fri, Sep 15, 2023 at 3:14 PM Huang Rui wrote:
>
> From: Antonio Caggiano
>
> Add support for the Venus capset, which enables Vulkan support through
> the Venus Vulkan driver for virtio-gpu.
>
> Signed-off-by: Antonio Caggiano
> Signed-off-by: Huang Rui
> ---
>
> V4 -> V5:
> - Send
On 9/19/23 08:57, Harsh Prateek Bora wrote:
On 9/18/23 20:28, Cédric Le Goater wrote:
to fix :
../hw/ppc/pnv_psi.c: In function ‘pnv_psi_p9_mmio_write’:
../hw/ppc/pnv_psi.c:741:24: warning: declaration of ‘addr’ shadows a
parameter [-Wshadow=compatible-local]
741 |
Use the private peripheral interrupt definitions from bsa.h instead of
defining them locally. Refactor to use the INTIDs defined there instead
of the PPI# used previously.
Signed-off-by: Leif Lindholm
---
hw/arm/sbsa-ref.c | 20 +---
1 file changed, 9 insertions(+), 11
GIC Private Peripheral Interrupts (PPI) are defined as GIC INTID 16-31.
As in, PPI0 is INTID16 .. PPI15 is INTID31.
Arm's Base System Architecture specification (BSA) lists the mandated and
recommended private interrupt IDs by INTID, not by PPI index. But current
definitions in virt define them by
virt.h defines a number of IRQs that are ultimately described by Arm's
Base System Architecture specification. Move these to a dedicated header
so that they can be reused by other platforms that do the same.
Include that header from virt.h to minimise churn.
Signed-off-by: Leif Lindholm
---
This set reworks the handling of private peripheral interrupts in virt
to use INTIDs instead of PPI IDs, to make it easier to cross reference
against Arm's Base System Architecture specification.
It then breaks those definitions out into a separate header and switches
sbsa-ref to use the same
On Tue, Sep 19, 2023 at 1:13 PM David Hildenbrand wrote:
>
> On 19.09.23 08:18, Ani Sinha wrote:
> > On Tue, Sep 19, 2023 at 9:53 AM Ani Sinha wrote:
> >>
> >> On Tue, Sep 19, 2023 at 9:20 AM Ani Sinha wrote:
> >>>
> >>> On Mon, Sep 18, 2023 at 9:28 PM David Hildenbrand
> >>> wrote:
>
>
Philippe Mathieu-Daudé writes:
> Hi Andrei,
>
> On 5/9/23 11:18, Andrei Gudkov via wrote:
>> Currently query-dirty-rate uses QEMU_CLOCK_REALTIME as
>> the source for start-time field. This translates to
>> clock_gettime(CLOCK_MONOTONIC), i.e. number of seconds
>> since host boot. This is not
On 2023/9/6 17:16, Daniel Henrique Barboza wrote:
All generic CPUs call riscv_cpu_add_user_properties(). The 'max' CPU
calls riscv_init_max_cpu_extensions(). Both can be moved to a common
instance_post_init() callback, implemented in riscv_cpu_post_init(),
called by all CPUs. The call order
On 9/19/23 11:18, Hanna Czenczek wrote:
> On 15.09.23 18:20, Andrey Drobyshev wrote:
>> Since commit bb1c05973cf ("qemu-img: Use qemu_blockalign"), buffers for
>> the data read from the old and new backing files are aligned using
>> BlockDriverState (or BlockBackend later on) referring to the
On 14/9/23 19:44, Richard Henderson wrote:
Without this we can get see loops through cpu_io_recompile,
in which the cpu makes no progress.
Signed-off-by: Richard Henderson
---
accel/tcg/cpu-exec.c | 2 +-
accel/tcg/tb-maint.c | 6 --
2 files changed, 5 insertions(+), 3 deletions(-)
On 9/18/23 14:31, Philippe Mathieu-Daudé wrote:
Hi Mark, Artyom,
I'm looking at the CPU_FEATURE_FLOAT128 definition introduced
in commit 64a88d5d3a ("CPU feature selection support"). Any
clue how it was supposed to be used?
This should have a comment like
/*
* Qemu is emulating the linux
v3:
- Fix an odd spacing change that Fan Ni noticed in review.
- Picked up tags.
Suggested-by: Michael S. Tsirkin
Michael observed that the CXL code regularly went above the 80 character
recommendation and in many cases this was not necessary for readability.
This series is focused on tidying
On 9/18/23 20:00, Denis V. Lunev wrote:
This patch creates above mentioned helper and moves its usage to the
beginning of parallels_open(). This simplifies parallels_open() a bit.
The patch also ensures that we store prealloc_size on block driver state
always in sectors. This makes code cleaner
On 19.09.23 10:20, David Hildenbrand wrote:
On 11.09.23 09:45, David Hildenbrand wrote:
@MST, any comment on the vhost bits (mostly uncontroversial and only in
the memslot domain)?
I'm planning on queuing this myself (but will wait a bit more), unless
you want to take it.
I'm queuing this to
Bring this read function inline with the others that do
check for unexpected size values.
Also reduces line lengths to sub 80 chars.
Signed-off-by: Jonathan Cameron
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Fan Ni
---
hw/cxl/cxl-device-utils.c | 11 +++
1 file changed, 7
Establishing that only register accesses of size 4 and 8 can occur
using these functions requires looking at their callers. Make it
easier to see that by using switch statements.
Assertions are used to enforce that the register storage is of the
matching size, allowing fixed values to be used for
On 16/9/23 23:41, Richard Henderson wrote:
From: Anton Johansson
Changes tlb_*() functions to take CPUState instead of CPUArchState, as
they don't require the full CPUArchState. This makes it easier to
decouple target-(in)dependent code.
Signed-off-by: Anton Johansson
Message-Id:
On 9/19/23 10:40, Daniel P. Berrangé wrote:
> On Mon, Sep 18, 2023 at 09:36:10PM +0200, Ilya Maximets wrote:
>> On 9/14/23 10:13, Daniel P. Berrangé wrote:
>>> On Wed, Sep 13, 2023 at 08:46:42PM +0200, Ilya Maximets wrote:
On 9/8/23 16:15, Daniel P. Berrangé wrote:
> On Fri, Sep 08, 2023
On 9/18/23 20:00, Denis V. Lunev wrote:
* Discarding with backing stores is not supported by the format.
* There is no buffering/queueing of the discard operation.
* Only operations aligned to the cluster are supported.
Signed-off-by: Denis V. Lunev
---
block/parallels.c | 46
Vladimir Sementsov-Ogievskiy writes:
> For now we only log the vhost device error, when virtqueue is actually
> stopped. Let's add a QAPI event, which makes possible:
>
> - collect statistics of such errors
> - make immediate actions: take core dumps or do some other debugging
> - inform the
On Tue, Sep 19, 2023 at 11:14:52AM +0200, Markus Armbruster wrote:
> Philippe Mathieu-Daudé writes:
>
> > Hi Andrei,
> >
> > On 5/9/23 11:18, Andrei Gudkov via wrote:
> >> Currently query-dirty-rate uses QEMU_CLOCK_REALTIME as
> >> the source for start-time field. This translates to
> >>
On 9/7/23 07:19, Nicholas Piggin wrote:
On Wed Sep 6, 2023 at 2:33 PM AEST, Harsh Prateek Bora wrote:
This patch introduces a new cmd line option cap-nested-papr to enable
support for nested PAPR API by setting the nested.api version accordingly.
It requires the user to launch the L0 Qemu in
On 2023/9/6 17:16, Daniel Henrique Barboza wrote:
riscv_cpu_realize_tcg() was added to allow TCG cpus to have a different
realize() path during the common riscv_cpu_realize(), making it a good
choice to start moving TCG exclusive code to tcg-cpu.c.
Rename it to tcg_cpu_realizefn() and assign
On 9/18/23 20:00, Denis V. Lunev wrote:
This patch contains test which minimally tests discard and new cluster
allocation logic.
The following checks are added:
* write 2 clusters, discard the first allocated
* write another cluster, check that the hole is filled
* write 2 clusters, discard the
On Tue, Sep 19, 2023 at 11:39:31AM +0200, Ilya Maximets wrote:
> On 9/19/23 10:40, Daniel P. Berrangé wrote:
> > On Mon, Sep 18, 2023 at 09:36:10PM +0200, Ilya Maximets wrote:
> >> Thanks! That worked. Though I wasn't able to test much anyway as
> >> this thing burned through all my free compute
Hi!
Thanks for the review
On 9/12/23 21:29, Vladimir Sementsov-Ogievskiy wrote:
On 04.09.23 11:31, Andrey Zhadchenko wrote:
Unlike other transaction commands, bitmap operations do not drain target
bds. If we have an IOThread, this may result in some inconsistencies, as
bitmap content may
Hi
On Fri, Sep 15, 2023 at 3:14 PM Huang Rui wrote:
>
> From: Antonio Caggiano
>
> Enable resource UUID feature and implement command resource assign UUID.
> This is done by introducing a hash table to map resource IDs to their
> UUIDs.
>
> Signed-off-by: Antonio Caggiano
> Signed-off-by:
On Mon, 18 Sep 2023 16:48:45 +
Fan Ni wrote:
> On Fri, Sep 15, 2023 at 06:04:18PM +0100, Jonathan Cameron wrote:
> > Michael Tsirkin observed that there were some unnecessarily
> > long lines in the CXL code in a recent review.
> > This patch is intended to rectify that where it does not
> >
On 9/19/23 10:38, Richard Henderson wrote:
On 9/19/23 10:26, Michael Tokarev wrote:
19.09.2023 11:00, Helge Deller wrote:
..
Probably the right solution is to use qemu_abort() (and qemu_assert() etc),
and maybe #define abort(x) qemu_abort(x). Even if some way to redefine
abort like the above
On Tue, Sep 19, 2023 at 3:43 PM Himanshu Chauhan
wrote:
>
>
>
> > On 19-Sep-2023, at 10:51 AM, Alistair Francis wrote:
> >
> > On Tue, Sep 19, 2023 at 3:08 PM Chang Alvin wrote:
> >>
> >>> -Original Message-
> >>
> >>> From: Alistair Francis
> >>
> >>> Sent: Tuesday, September 19, 2023
On 9/18/23 20:00, Denis V. Lunev wrote:
We should free opts allocated through qemu_opts_create() at the end.
Signed-off-by: Denis V. Lunev
---
block/parallels.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/block/parallels.c b/block/parallels.c
index 428f72de1c..af7be427c9 100644
---
Done to reduce line lengths where this is used.
Ext seems sufficiently obvious that it need not be spelt out
fully.
Signed-off-by: Jonathan Cameron
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Fan Ni
---
include/hw/cxl/cxl_pci.h | 6 ++---
hw/cxl/cxl-component-utils.c | 49
On Mon, 18 Sep 2023 18:38:10 +0100
Peter Maydell wrote:
> On Mon, 18 Sept 2023 at 18:26, Dave Jiang wrote:
> >
> >
> >
> > On 9/18/23 10:00, Jonathan Cameron wrote:
> > > On Mon, 18 Sep 2023 17:31:38 +0100
> > > Peter Maydell wrote:
> > >
> > >> On Mon, 18 Sept 2023 at 16:04, Jonathan
Michael Tsirkin observed that there were some unnecessarily
long lines in the CXL code in a recent review.
This patch is intended to rectify that where it does not
hurt readability.
Reviewed-by: Michael Tokarev
Signed-off-by: Jonathan Cameron
---
v3: Put removed space back in and rewrap some
On 14/9/23 19:44, Richard Henderson wrote:
Require i/o as the last insn of a TranslationBlock always,
not only with icount. This is required for i/o that alters
the address space, such as a pci config space write.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1866
Signed-off-by:
On 16/9/23 23:40, Richard Henderson wrote:
Replace the single use within env_tlb() and remove.
Reviewed-by: Anton Johansson
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 13 +
1 file changed, 1 insertion(+), 12 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
Am 19.09.2023 um 07:48 hat Markus Armbruster geschrieben:
> Kevin Wolf writes:
>
> > Am 31.08.2023 um 15:25 hat Markus Armbruster geschrieben:
> >> Local variables shadowing other local variables or parameters make the
> >> code needlessly hard to understand. Tracked down with -Wshadow=local.
>
On 16/9/23 23:41, Richard Henderson wrote:
From: Anton Johansson
The function is no longer used to access the TLB,
and has been replaced by cpu->neg.tlb.
Signed-off-by: Anton Johansson
Message-Id: <20230912153428.17816-9-a...@rev.ng>
Reviewed-by: Richard Henderson
[rth: Merge comment update
Xiaoyao Li writes:
> From: Isaku Yamahata
>
> Add a new property "private" to memory backends. When it's set to true,
> it indicates the RAMblock of the backend also requires kvm gmem.
Can you add a brief explanation why you need the property?
> Signed-off-by: Isaku Yamahata
> Signed-off-by:
On 2023/9/6 17:16, Daniel Henrique Barboza wrote:
target/riscv/cpu.c needs to handle all possible accelerators (TCG and
KVM at this moment) during both init() and realize() time. This forces
us to resort to a lot of "if tcg" and "if kvm" throughout the code,
which isn't wrong, but can get
On Tue, 19 Sep 2023 09:47:06 +0100
Daniel P. Berrangé wrote:
> On Mon, Sep 18, 2023 at 02:14:40PM -0700, Ira Weiny wrote:
> > Jonathan Cameron wrote:
> > > On Mon, 18 Sep 2023 17:31:38 +0100
> > > Peter Maydell wrote:
> > >
> > > > On Mon, 18 Sept 2023 at 16:04, Jonathan Cameron
> > > >
On 15.09.23 18:20, Andrey Drobyshev wrote:
The test cases considered so far:
314 (new test suite):
1. Check that compression mode isn't compatible with "-f raw" (raw
format doesn't support compression).
2. Check that rebasing an image onto no backing file preserves the data
and writes
On 9/19/23 10:29, Harsh Prateek Bora wrote:
On 9/18/23 20:28, Cédric Le Goater wrote:
Remove extra 'drc_index' variable to avoid this warning :
../hw/ppc/spapr_drc.c: In function ‘rtas_ibm_configure_connector’:
../hw/ppc/spapr_drc.c:1240:26: warning: declaration of ‘drc_index’ shadows
On 9/19/23 10:38, Harsh Prateek Bora wrote:
On 9/18/23 20:28, Cédric Le Goater wrote:
Rename SysBusDevice variable to avoid this warning :
../hw/ppc/spapr_pci.c: In function ‘spapr_phb_realize’:
../hw/ppc/spapr_pci.c:1872:24: warning: declaration of ‘s’ shadows a
previous local
Hi Mikhail Golubev-Ciuchea,
I have improved this implementation to the virtio pci level. Could you please
try my patches and see if them are useful in your scene?
My new series:
V5 of Qemu patch:
https://lore.kernel.org/qemu-devel/20230919110225.2282914-1-jiqian.c...@amd.com/T/#t
V5 of kernel
On 9/19/23 10:48, Harsh Prateek Bora wrote:
On 9/18/23 20:28, Cédric Le Goater wrote:
Rename 'name' variable to avoid this warning :
../hw/ppc/spapr_drc.c: In function ‘prop_get_fdt’:
../hw/ppc/spapr_drc.c:344:21: warning: declaration of ‘name’ shadows a
parameter
Hi Jiqian,
> From: Jiqian Chen
> Sent: Tuesday, September 19, 2023 5:13 PM
>
> When guest vm does S3, Qemu will reset and clear some things of virtio
> devices, but guest can't aware that, so that may cause some problems.
It is not true that guest VM is not aware of it.
As you show in your
On Tue, Sep 19, 2023 at 07:42:42PM +0800, Jiqian Chen wrote:
> When guest vm does S3, Qemu will reset and clear some things of virtio
> devices, but guest can't aware that, so that may cause some problems.
> For excample, Qemu calls virtio_reset->virtio_gpu_gl_reset when guest
> resume, that
On 3/2/23 15:55, Philippe Mathieu-Daudé wrote:
Since v1:
- Addressed Markus & Zoltan review comments
- Introduce/use qdev_unrealize_and_unref()
These patches are extracted from a QOM/QDev refactor series,
so they are preliminary cleanups noticed while working on it:
- Use correct type when
On 19.09.23 13:52, Ani Sinha wrote:
On Tue, Sep 19, 2023 at 4:08 PM Ani Sinha wrote:
32-bit systems do not have a reserved memory for hole64 and memory hotplug is
not supported on those systems. Therefore, the maximum limit of the guest
physical address coincides with the end of "above 4G
On 9/18/23 15:51, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
For now, pixman is mandatory, but we set config_host.h and Kconfig.
Once compilation is fixed, "pixman" will become actually optional.
Signed-off-by: Marc-André Lureau
---
meson.build | 10
On Tue, Sep 19, 2023 at 6:10 PM David Hildenbrand wrote:
>
> On 19.09.23 13:52, Ani Sinha wrote:
> > On Tue, Sep 19, 2023 at 4:08 PM Ani Sinha wrote:
> >>
> >> 32-bit systems do not have a reserved memory for hole64 and memory hotplug
> >> is
> >> not supported on those systems. Therefore, the
Nina Schoetterl-Glausch writes:
> From: Pierre Morel
>
> S390 adds two new SMP levels, drawers and books to the CPU
> topology.
> S390 CPUs have specific topology features like dedication and
> entitlement. These indicate to the guest information on host
> vCPU scheduling and help the guest
Hi
On Thu, Sep 7, 2023 at 5:15 PM wrote:
>
> From: Marc-André Lureau
>
> Hi,
>
> This is a follow-up of the previous patch "[PATCH] virtio-gpu: block migration
> of VMs with blob=true". Now that migration support is implemented, we can
> decide
> to drop the migration blocker patch, or apply
Daniel P. Berrangé writes:
> On Tue, Sep 19, 2023 at 12:49:46PM -0400, Peter Xu wrote:
>> On Mon, Sep 18, 2023 at 04:41:14PM +0200, Markus Armbruster wrote:
>> > Oh dear, where to start. There's so much wrong, and in pretty obvious
>> > ways. This code should never have passed review. I'm
From: Helge Deller
Wire up the hppa diag instruction to support Block-TLBs
when called with the 0x100 value.
The diag_btlb() helper function does all necessary steps
to emulate the PDC BTLB firmware function, which includes
providing BTLB info, adding a new BTLB, deleting a BTLB
and removing
From: Helge Deller
Report the new number of TLB entries (without BTLBs) to the
guest and drop reporting of BTLB entries which weren't used at all.
Clear all BTLB and TLB entries at machine reset.
Signed-off-by: Helge Deller
---
hw/hppa/machine.c | 10 +-
1 file changed, 5
From: Helge Deller
Reserve 16 out of the 256 TLB entries for Block-TLBs.
Signed-off-by: Helge Deller
---
target/hppa/cpu.h | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index fa13694dab..23852d89b2 100644
---
Am 3. April 2023 12:27:14 UTC schrieb Jason Andryuk :
>On Mon, Apr 3, 2023 at 5:33 AM Anthony PERARD
>wrote:
>>
>> On Sat, Apr 01, 2023 at 10:36:45PM +, Bernhard Beschow wrote:
>> >
>> >
>> > Am 30. März 2023 13:00:25 UTC schrieb Anthony PERARD
>> > :
>> > >On Sun, Mar 12, 2023 at
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any
user-visible changes.
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From: Hao Wu
This patch implements the basic registers of GMAC device. Actual network
communications are not supported yet.
Signed-off-by: Hao Wu
include/hw: Fix type problem in NPCMGMACState
- Fix type problem in NPCMGMACState
- Fix Register Initalization which was breaking boot-up in
From: Hao Wu
The PCS exists in NPCM8XX's GMAC1 and is used to control the SGMII
PHY. This implementation contains all the default registers and
the soft reset feature that are required to load the Linux kernel
driver. Further features have not been implemented yet.
Signed-off-by: Hao Wu
---
From: Nabih Estefan Diaz
- Implementation of Transmit function for packets
- Implementation for reading and writing from and to descriptors in
memory for Tx
NOTE: This function implements the steps detailed in the datasheet for
transmitting messages from the GMAC.
Signed-off-by: Nabih
On 2023-09-14 20:13, Nicholas Piggin wrote:
On Wed Sep 13, 2023 at 6:24 AM AEST, Glenn Miles wrote:
Add support for the clrbhrb and mfbhrbe instructions.
Since neither instruction is believed to be critical to
performance, both instructions were implemented using helper
functions.
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