/npcm7xx_watchdog_timer-test.c:243
> >
> > Reported-by: Euler Robot
> > Signed-off-by: Chen Qun
>
> Reviewed-by: Havard Skinnemoen
>
> Reviewed-by: Hao Wu
> > ---
> > tests/qtest/npcm7xx_watchdog_timer-test.c | 6 --
> > 1 file changed,
On Wed, Jan 13, 2021 at 8:03 AM Peter Maydell
wrote:
> On Tue, 12 Jan 2021 at 16:58, Peter Maydell
> wrote:
> >
> > From: Hao Wu
> >
> > The PWM module is part of NPCM7XX module. Each NPCM7XX module has two
> > identical PWM modules. Each module contains
Reviewed-by: Hao Wu
On Thu, May 13, 2021 at 9:39 AM Philippe Mathieu-Daudé
wrote:
> The TYPE_NPCM7XX_SMBUS device model exposes an SMBus, but
> this isn't advertised with proper Kconfig symbol, leading
> to an early build failure when building NPCM7XX machines
> standalone:
>
&g
mplains about the possible array overrun at various callsites.
> >
> > Fixes: Coverity CID 1442340, 1442341, 1442343, 1442344, 1442345, 1442346
> > Signed-off-by: Peter Maydell
>
> Reviewed-by: Havard Skinnemoen
>
Reviewed-by: Hao Wu
I don't see this error. It could be some error in the clock that the timer
module does not get a correct clock input.
How do you reproduce this?
On Thu, Feb 4, 2021 at 1:39 AM Philippe Mathieu-Daudé
wrote:
> Hi,
>
> On Tue, Jan 12, 2021 at 6:20 PM Peter Maydell
> wrote:
> >
On Tue, Feb 9, 2021 at 5:21 AM Peter Maydell
wrote:
> Use the new clock_ns_to_ticks() function in npcm7xx_timer where
> appropriate.
>
> Signed-off-by: Peter Maydell
>
Reviewed-by: Hao Wu
Thanks!
> ---
> hw/timer/npcm7xx_timer.c | 4 ++--
> 1 file changed, 2 in
On Tue, Feb 9, 2021 at 5:24 AM Peter Maydell
wrote:
> The Clock framework allows users to specify a callback which is
> called after the clock's period has been updated. Some users need to
> also have a callback which is called before the clock period is
> updated.
>
> As the first step in
Thanks. I'll take patch 1 out of the next version.
On Mon, Feb 8, 2021 at 9:01 AM Peter Maydell
wrote:
> On Fri, 29 Jan 2021 at 01:04, Hao Wu wrote:
> >
> > This patch set implements the System manager bus (SMBus) module in
> NPCM7XX
> > SoC. Basically, it emulat
have a free running counter register whose value can
> be calculated when it is read.
>
> Signed-off-by: Peter Maydell
>
Reviewed-by: Hao Wu
> ---
> I have made the overflow behaviour here be "wrap", with justification
> as per the comment; but I'm not 100% set o
On Mon, Feb 8, 2021 at 8:59 AM Peter Maydell
wrote:
> On Fri, 29 Jan 2021 at 01:04, Hao Wu wrote:
> >
> > This patch implements the FIFO mode of the SMBus module. In FIFO, the
> > user transmits or receives at most 16 bytes at a time. The FIFO mode
> > allows the modu
On Tue, Feb 9, 2021 at 5:21 AM Peter Maydell
wrote:
> Add a new callback event type ClockPreUpdate, which is called on
> period changes before the period is updated.
>
> Signed-off-by: Peter Maydell
>
Reviewed-by: Hao Wu
> ---
> docs/devel/clocks.rst | 9 -
Hi, Cedric and Corey
When I'm implementing KCS device for nuvoton BMC boards, one of the
feedback Corey gave me was to refactor the existing device like
ipmi-bmc-extern so that we can reuse some of the common stuff there. I'm in
the process of doing that. I'll probably send that as an RFC first
This patch adds the recently implemented MFT device to the NPCM7XX
SoC file.
Reviewed-by: Doug Evans
Reviewed-by: Tyrone Ting
Signed-off-by: Hao Wu
---
docs/system/arm/nuvoton.rst | 2 +-
hw/arm/npcm7xx.c| 45 ++---
include/hw/arm/npcm7xx.h| 2
This patch adds testing of PWM fan RPMs in the existing npcm7xx pwm
test. It tests whether the MFT module can measure correct fan values
for a PWM fan in NPCM7XX boards.
Reviewed-by: Doug Evans
Reviewed-by: Tyrone Ting
Signed-off-by: Hao Wu
Reviewed-by: Peter Maydell
---
tests/qtest
-pwm-fan.c
Reviewed-by: Doug Evans
Reviewed-by: Tyrone Ting
Signed-off-by: Hao Wu
---
hw/misc/meson.build | 1 +
hw/misc/npcm7xx_mft.c | 540 ++
hw/misc/trace-events | 8 +
include/hw/misc/npcm7xx_mft.h | 70 +
4 files changed
:
- Split implementation of device and addition to board file to separate patches
- Adapt to new Clock API and address conflicts
- Use the new clock_ns_to_ticks API to calculate tachometer counts
Hao Wu (5):
hw/misc: Add GPIOs for duty in NPCM7xx PWM
hw/misc: Add NPCM7XX MFT Module
hw/arm
instances in MFT.
Reviewed-by: Doug Evans
Reviewed-by: Tyrone Ting
Signed-off-by: Hao Wu
Reviewed-by: Peter Maydell
---
hw/misc/npcm7xx_pwm.c | 4
include/hw/misc/npcm7xx_pwm.h | 4 +++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/hw/misc/npcm7xx_pwm.c b/hw/misc
according their specific device trees.
Reviewed-by: Doug Evans
Reviewed-by: Tyrone Ting
Signed-off-by: Hao Wu
Reviewed-by: Peter Maydell
---
hw/arm/npcm7xx_boards.c | 99
include/hw/arm/npcm7xx.h | 11 -
2 files changed, 109 insertions(+), 1 deletion
On Sun, Feb 28, 2021 at 2:50 PM Philippe Mathieu-Daudé
wrote:
> The STATUS register will be reset to IDLE in
> cnpcm7xx_smbus_enter_reset(), no need to preset
> it in instance_init().
>
> Signed-off-by: Philippe Mathieu-Daudé
>
Reviewed-by: Hao Wu
> ---
> hw/i2c/np
the function defined in patch 5 to add the EEPROM and other
I2C devices for Quanta GBS board.
Patch 7 modifies the Quanta GSJ board to use the new function defined in
patch 5.
Hao Wu (6):
hw/i2c: Clear ACK bit in NPCM7xx SMBus module
hw/i2c: Read FIFO during RXF_CTL change in NPCM7XX SMBus
numbers for each eeproms in each board. This avoids conflict
in providing multiple eeprom contents with the same address.
We add an auxiliary function in the at24c eeprom module for this.
This allows it to easily add at24c eeprom to non-nuvoton boards
like aspeed as well.
Signed-off-by: Hao Wu
The ACK bit in NPCM7XX SMBus module should be cleared each time it
sends out a NACK signal. This patch fixes the bug that it fails to
do so.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
---
hw/i2c/npcm7xx_smbus.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i2c
Originally we read in from SMBus when RXF_STS is cleared. However,
the driver clears RXF_STS before setting RXF_CTL, causing the SM bus
module to read incorrect amount of bytes in FIFO mode when the number
of bytes read changed. This patch fixes this issue.
Signed-off-by: Hao Wu
Reviewed
Use unique unit numbers in quanta-gsj eeprom files.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
---
hw/arm/npcm7xx_boards.c | 15 ++-
1 file changed, 2 insertions(+), 13 deletions(-)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index 54cf9785ec..be6c81b29d
From: Patrick Venture
Adds supported i2c devices to the quanta-gbc-bmc board.
Signed-off-by: Patrick Venture
Reviewed-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 79 +++--
1 file changed, 45 insertions(+), 34 deletions(-)
diff --git a/hw/arm/npcm7xx_boards.c
The correct bit for the CONV bit in NPCM7XX ADC is bit 13. This patch
fixes that in the module, and also lower the IRQ when the guest
is done handling an interrupt event from the ADC module.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
---
hw/adc/npcm7xx_adc.c | 2 +-
tests
Our sensor test requires both reading and writing from a sensor's
QOM property. So we need to make the input of ADC module R/W instead
of read only for that to work.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
---
hw/adc/npcm7xx_adc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
From: Shengtan Mao
Signed-off-by: Shengtan Mao
Reviewed-by: Hao Wu
Reviewed-by: Chris Rauer
Reviewed-by: Tyrone Ting
---
tests/qtest/libqos/meson.build | 1 +
tests/qtest/libqos/sdhci-cmd.c | 116 +
tests/qtest/libqos/sdhci-cmd.h | 70
From: Shengtan Mao
Signed-off-by: Shengtan Mao
Reviewed-by: Hao Wu
Reviewed-by: Tyrone Ting
---
hw/arm/npcm7xx_boards.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index e5a3243995..7205483280 100644
--- a/hw
This patch set implements the Nuvoton MMC device
for NPCM7XX boards.
The MMC device is compatible with the SDHCI interface
in QEMU. It allows the user to attach an SD card image
to it.
Shengtan Mao (4):
tests/qtest/libqos: add SDHCI commands
hw/sd: add nuvoton MMC
hw/arm: Attach MMC to
From: Shengtan Mao
Signed-off-by: Shengtan Mao
Reviewed-by: Hao Wu
Reviewed-by: Chris Rauer
Reviewed-by: Tyrone Ting
---
tests/qtest/meson.build | 1 +
tests/qtest/npcm7xx_sdhci-test.c | 201 +++
2 files changed, 202 insertions(+)
create mode 100644
From: Shengtan Mao
Signed-off-by: Shengtan Mao
Reviewed-by: Hao Wu
Reviewed-by: Chris Rauer
Reviewed-by: Tyrone Ting
---
hw/arm/npcm7xx.c | 12 +++-
hw/sd/meson.build | 1 +
hw/sd/npcm7xx_sdhci.c | 131 ++
include/hw/arm
From: Havard Skinnemoen
This document is an attempt to briefly document the existing IPMI
emulation support on the main processor. It provides the necessary
background for the BMC-side IPMI emulation proposed by the next patch.
Signed-off-by: Havard Skinnemoen
Signed-off-by: Hao Wu
---
docs
, in READ_STATE, ipmi_kcs.c (core
side emulation) reads a message from BMC while npcm7xx_kcs.c
(BMC-side emulation) sends a message to the core.
Signed-off-by: Hao Wu
Reviewed-by: Tyrone Ting
---
docs/system/arm/nuvoton.rst | 1 -
hw/arm/npcm7xx.c | 10 +-
hw/ipmi/meson.build
From: Havard Skinnemoen
Signed-off-by: Havard Skinnemoen
Signed-off-by: Hao Wu
---
docs/conf.py | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/docs/conf.py b/docs/conf.py
index ff6e92c6e2..ecd0be66a5 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -71,7 +71,11
.
Basically most of the message transaction are moved. The stuff remained
are basically hardware operations like handle_reset and handle_hw_op.
These stuff have different behaviors in core-side and BMC-side
emulation.
Signed-off-by: Hao Wu
---
hw/ipmi/ipmi_bmc_extern.c | 420
e side and
BMC side emulation.
Signed-off-by: Hao Wu
---
hw/ipmi/ipmi.c| 15 +++---
hw/ipmi/ipmi_bmc_extern.c | 37 +--
hw/ipmi/ipmi_bmc_sim.c| 41 ++-
hw/ipmi/ipmi_bt.c | 2 +-
hw/ipmi/ipmi
Move the function handle_command to IPMICoreClass. This function is
shared between BMC-side emulation and Host-side emulation.
Signed-off-by: Hao Wu
---
hw/ipmi/ipmi_bmc_extern.c | 4 ++--
hw/ipmi/ipmi_bmc_sim.c| 6 +++---
hw/ipmi/ipmi_bt.c | 4 ++--
hw/ipmi/ipmi_extern.c
ipmi-host-extern which represents
BMC-side emulation that is similar to the current
ipmi-bmc-extern.
Patch 8 implements the KCS device in NPCM7XX boards. It
works as a backend to the ipmi-host-extern device. Since
the direction is different we can't directly use ipmi-kcs.c
for BMC emulation.
Hao Wu
-by: Havard Skinnemoen
Signed-off-by: Hao Wu
---
docs/specs/ipmi.rst | 70 +
1 file changed, 70 insertions(+)
diff --git a/docs/specs/ipmi.rst b/docs/specs/ipmi.rst
index adb098b53d..b5fe362043 100644
--- a/docs/specs/ipmi.rst
+++ b/docs/specs/ipmi.rst
with device ipmi-bmc-extern.
For more details of IPMI host device in BMC emulation, see
docs/specs/ipmi.rst.
Signed-off-by: Hao Wu
---
configs/devices/arm-softmmu/default.mak | 2 +
hw/ipmi/Kconfig | 5 +
hw/ipmi/ipmi_extern.c | 18 ++-
hw/ipmi
data sheet from AMD and Linux
kernel driver.
Reference:
Linux kernel driver:
https://lkml.org/lkml/2020/12/11/968
Register Map:
https://developer.amd.com/wp-content/resources/56255_3_03.PDF
(Chapter 6)
Signed-off-by: Hao Wu
Reviewed-by: Doug Evans
---
hw/sensor/Kconfig| 4 +
hw
From: Shengtan Mao
Signed-off-by: Shengtan Mao
Reviewed-by: Hao Wu
Reviewed-by: Chris Rauer
Reviewed-by: Tyrone Ting
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx.c | 12 +++-
include/hw/arm/npcm7xx.h | 2 ++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/hw/arm
This patch set implements the Nuvoton MMC device
for NPCM7XX boards.
The MMC device is compatible with the SDHCI interface
in QEMU. It allows the user to attach an SD card image
to it.
Changes since v1:
1. Rearrange the "add SDHCI commands" to just before when it's
actually used.
2. Add
From: Shengtan Mao
Signed-off-by: Shengtan Mao
Reviewed-by: Hao Wu
Reviewed-by: Tyrone Ting
Signed-off-by: Hao Wu
Reviewed-by: Peter Maydell
---
hw/arm/npcm7xx_boards.c | 20
1 file changed, 20 insertions(+)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm
From: Shengtan Mao
Signed-off-by: Shengtan Mao
Reviewed-by: Hao Wu
Reviewed-by: Chris Rauer
Reviewed-by: Tyrone Ting
Signed-off-by: Hao Wu
---
hw/sd/meson.build | 1 +
hw/sd/npcm7xx_sdhci.c | 182 ++
include/hw/sd/npcm7xx_sdhci.h | 65
From: Shengtan Mao
Signed-off-by: Shengtan Mao
Reviewed-by: Hao Wu
Reviewed-by: Chris Rauer
Reviewed-by: Tyrone Ting
Signed-off-by: Hao Wu
---
tests/qtest/libqos/meson.build | 1 +
tests/qtest/libqos/sdhci-cmd.c | 116 +
tests/qtest/libqos/sdhci-cmd.h
From: Shengtan Mao
Signed-off-by: Shengtan Mao
Reviewed-by: Hao Wu
Reviewed-by: Chris Rauer
Reviewed-by: Tyrone Ting
Signed-off-by: Hao Wu
---
tests/qtest/meson.build | 1 +
tests/qtest/npcm7xx_sdhci-test.c | 209 +++
2 files changed, 210 insertions
From: Patrick Venture
Adds supported i2c devices to the quanta-gbc-bmc board.
Signed-off-by: Patrick Venture
Reviewed-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 82 -
1 file changed, 49 insertions(+), 33 deletions(-)
diff --git a/hw/arm/npcm7xx_boards.c
The correct bit for the CONV bit in NPCM7XX ADC is bit 13. This patch
fixes that in the module, and also lower the IRQ when the guest
is done handling an interrupt event from the ADC module.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
---
hw/adc/npcm7xx_adc.c | 2 +-
tests
The ID can be used to indicate SMBus modules when adding
dynamic devices to them.
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index 2ab0080e0b..72953d65ef 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
The ACK bit in NPCM7XX SMBus module should be cleared each time it
sends out a NACK signal. This patch fixes the bug that it fails to
do so.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
---
hw/i2c/npcm7xx_smbus.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i2c
with the same unit number,
the following error will occur: `Device with id 'none85' exists`.
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index a656169f61
Originally we read in from SMBus when RXF_STS is cleared. However,
the driver clears RXF_STS before setting RXF_CTL, causing the SM bus
module to read incorrect amount of bytes in FIFO mode when the number
of bytes read changed. This patch fixes this issue.
Signed-off-by: Hao Wu
Reviewed
dify patch 6 to adapt to the changes and QEMU comment style.
3. Squash patch 7 into patch 5 to make it compile.
4. Add a new patch 7.
Hao Wu (6):
hw/i2c: Clear ACK bit in NPCM7xx SMBus module
hw/i2c: Read FIFO during RXF_CTL change in NPCM7XX SMBus
hw/adc: Fix CONV bit in NPCM7XX ADC CON reg
Our sensor test requires both reading and writing from a sensor's
QOM property. So we need to make the input of ADC module R/W instead
of read only for that to work.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
---
hw/adc/npcm7xx_adc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
*/
> >257 case 0x02:
> >258 retval = 0xf0;
> >259 break;
> >
> > For QEMU the AER915 is a very simple sensor model.
> >
> > [*] https://www.bealecorner.org/best/measure/z2/index.html
> >
> > Signed-off-by: Philippe Mat
_abort);
> > }
> >
> > -static void sdhci_attach_drive(SDHCIState *sdhci)
> > +static void sdhci_attach_drive(SDHCIState *sdhci, int unit)
> > {
> > -DriveInfo *di = drive_get_next(IF_SD);
> > +DriveInfo *di =
Is this reply to a wrong thread? I thought it was applied a long time ago.
Thanks,
On Mon, Nov 1, 2021 at 10:33 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On Thu, 11 Mar 2021 at 13:11, Hao Wu wrote:
> >
> > This patch set implements the Tachometer (a
On Mon, Nov 1, 2021 at 10:41 AM Peter Maydell
wrote:
> On Thu, 21 Oct 2021 at 19:40, Hao Wu wrote:
> >
> > We made 3 changes to the at24c_eeprom_init function in
> > npcm7xx_boards.c:
> >
> > 1. We allow the function to take a I2CBus* as parameter. This all
I was trying to allow attaching a device using "-device xxx,bus=smbus[0]"
Maybe there's a better way to allow that?
I guess I can drop this one from the patch set.
On Mon, Nov 1, 2021 at 10:33 AM Peter Maydell
wrote:
> On Thu, 21 Oct 2021 at 19:40, Hao Wu wrote:
> >
>
.
3. Squash patch 7 into patch 5 to make it compile.
4. Add a new patch 7.
Hao Wu (5):
hw/i2c: Clear ACK bit in NPCM7xx SMBus module
hw/i2c: Read FIFO during RXF_CTL change in NPCM7XX SMBus
hw/adc: Fix CONV bit in NPCM7XX ADC CON register
hw/adc: Make adci[*] R/W in NPCM7XX ADC
hw/nvram
The ACK bit in NPCM7XX SMBus module should be cleared each time it
sends out a NACK signal. This patch fixes the bug that it fails to
do so.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
---
hw/i2c/npcm7xx_smbus.c | 2 +-
1 file changed, 1 insertion(+), 1
with the same unit number,
the following error will occur: `Device with id 'none85' exists`.
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index a656169f61
Our sensor test requires both reading and writing from a sensor's
QOM property. So we need to make the input of ADC module R/W instead
of write only for that to work.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
---
hw/adc/npcm7xx_adc.c | 2 +-
1 file changed
From: Patrick Venture
Adds supported i2c devices to the quanta-gbc-bmc board.
Signed-off-by: Patrick Venture
Reviewed-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 82 -
1 file changed, 49 insertions(+), 33 deletions(-)
diff --git a/hw/arm/npcm7xx_boards.c
Originally we read in from SMBus when RXF_STS is cleared. However,
the driver clears RXF_STS before setting RXF_CTL, causing the SM bus
module to read incorrect amount of bytes in FIFO mode when the number
of bytes read changed. This patch fixes this issue.
Signed-off-by: Hao Wu
Reviewed
The correct bit for the CONV bit in NPCM7XX ADC is bit 13. This patch
fixes that in the module, and also lower the IRQ when the guest
is done handling an interrupt event from the ADC module.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
Reviewed-by: Peter Maydell
---
hw/adc/npcm7xx_adc.c
From: Shengtan Mao
Signed-off-by: Shengtan Mao
Reviewed-by: Hao Wu
Reviewed-by: Chris Rauer
Reviewed-by: Tyrone Ting
Signed-off-by: Hao Wu
Reviewed-by: Peter Maydell
---
tests/qtest/libqos/meson.build | 1 +
tests/qtest/libqos/sdhci-cmd.c | 116 +
tests
From: Shengtan Mao
Signed-off-by: Shengtan Mao
Reviewed-by: Hao Wu
Reviewed-by: Chris Rauer
Reviewed-by: Tyrone Ting
Signed-off-by: Hao Wu
Reviewed-by: Peter Maydell
---
hw/sd/meson.build | 1 +
hw/sd/npcm7xx_sdhci.c | 182 ++
include
From: Shengtan Mao
Signed-off-by: Shengtan Mao
Reviewed-by: Hao Wu
Reviewed-by: Chris Rauer
Reviewed-by: Tyrone Ting
Signed-off-by: Hao Wu
Reviewed-by: Peter Maydell
---
tests/qtest/meson.build | 1 +
tests/qtest/npcm7xx_sdhci-test.c | 209 +++
2
From: Shengtan Mao
Signed-off-by: Shengtan Mao
Reviewed-by: Hao Wu
Reviewed-by: Tyrone Ting
Signed-off-by: Hao Wu
Reviewed-by: Peter Maydell
---
hw/arm/npcm7xx_boards.c | 20
1 file changed, 20 insertions(+)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm
From: Shengtan Mao
Signed-off-by: Shengtan Mao
Reviewed-by: Hao Wu
Reviewed-by: Chris Rauer
Reviewed-by: Tyrone Ting
Signed-off-by: Hao Wu
Reviewed-by: Peter Maydell
---
hw/arm/npcm7xx.c | 12 +++-
include/hw/arm/npcm7xx.h | 2 ++
2 files changed, 13 insertions(+), 1
Hi,
I've sent a new patch set which uses memcpy here. Thank you!
On Tue, Nov 2, 2021 at 11:25 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> From: Shengtan Mao
>
> Signed-off-by: Shengtan Mao
> Signed-off-by: Hao Wu
> Reviewed-by: Hao Wu
>
This patch set implements the Nuvoton MMC device
for NPCM7XX boards.
The MMC device is compatible with the SDHCI interface
in QEMU. It allows the user to attach an SD card image
to it.
Changes since v2:
1. Fix an error use of strcmp in qtest.
Changes since v1:
1. Rearrange the "add SDHCI
with the same unit number,
the following error will occur: `Device with id 'none85' exists`.
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index dec7d16ae5
:
> On 01/11/2021 18.47, Hao Wu wrote:
> >
> >
> > On Mon, Nov 1, 2021 at 10:41 AM Peter Maydell > <mailto:peter.mayd...@linaro.org>> wrote:
> >
> > On Thu, 21 Oct 2021 at 19:40, Hao Wu > <mailto:wuhao...@google.com>> wrote:
> &g
Originally we read in from SMBus when RXF_STS is cleared. However,
the driver clears RXF_STS before setting RXF_CTL, causing the SM bus
module to read incorrect amount of bytes in FIFO mode when the number
of bytes read changed. This patch fixes this issue.
Signed-off-by: Hao Wu
Reviewed
The correct bit for the CONV bit in NPCM7XX ADC is bit 13. This patch
fixes that in the module, and also lower the IRQ when the guest
is done handling an interrupt event from the ADC module.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
Reviewed-by: Peter Maydell
---
hw/adc/npcm7xx_adc.c
The ACK bit in NPCM7XX SMBus module should be cleared each time it
sends out a NACK signal. This patch fixes the bug that it fails to
do so.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
---
hw/i2c/npcm7xx_smbus.c | 2 +-
1 file changed, 1 insertion(+), 1
the function in NPCM7xx board file instead
of the EEPROM device file.
2. Slightly modify patch 6 to adapt to the changes and QEMU comment style.
3. Squash patch 7 into patch 5 to make it compile.
4. Add a new patch 7.
Hao Wu (6):
hw/i2c: Clear ACK bit in NPCM7xx SMBus module
hw/i2c: Read FIFO
From: Patrick Venture
Adds supported i2c devices to the quanta-gbc-bmc board.
Signed-off-by: Patrick Venture
Reviewed-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 82 -
1 file changed, 49 insertions(+), 33 deletions(-)
diff --git a/hw/arm/npcm7xx_boards.c
Our sensor test requires both reading and writing from a sensor's
QOM property. So we need to make the input of ADC module R/W instead
of write only for that to work.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
---
hw/adc/npcm7xx_adc.c | 2 +-
1 file changed
This type is used to represent block devs that are not suitable to
be represented by other existing types.
Signed-of-by: Hao Wu
---
blockdev.c| 3 ++-
include/sysemu/blockdev.h | 1 +
meson | 2 +-
3 files changed, 4 insertions(+), 2 deletions(-)
diff --git
gt; > (Detected with the clang leak sanitizer.)
> >
> > Signed-off-by: Peter Maydell
> > ---
> > hw/misc/npcm7xx_clk.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
>
> Reviewed-by: Richard Henderson
>
> Reviewed-by: Hao Wu
> r~
>
>
issue.
On Tue, Feb 22, 2022 at 5:28 PM Patrick Venture wrote:
>
>
> On Mon, Feb 21, 2022 at 5:30 AM Peter Maydell
> wrote:
>
>> On Wed, 16 Feb 2022 at 17:30, Peter Maydell
>> wrote:
>> >
>> > On Tue, 8 Feb 2022 at 18:18, Patrick Venture
>> wro
From: Shengtan Mao
Reviewed-by: Hao Wu
Reviewed-by: Chris Rauer
Signed-off-by: Shengtan Mao
Signed-off-by: Patrick Venture
Signed-off-by: Hao Wu
---
v4:
* use strncmp to compare fixed length strings
v3:
* fixup compilation from missing macro value
v2:
* update copyright year
* check
From: Shengtan Mao
Reviewed-by: Hao Wu
Reviewed-by: Chris Rauer
Signed-off-by: Shengtan Mao
Signed-off-by: Patrick Venture
---
v5
* use memcmp to compare whether strings are expected
v4
* use strncmp instead of strcmp
v3:
* fixup compilation from missing macro value
v2:
* update
I have sent an updated version that uses memcmp()
On Fri, Feb 25, 2022 at 3:44 AM Peter Maydell
wrote:
> On Thu, 24 Feb 2022 at 19:03, Hao Wu wrote:
> >
> > From: Shengtan Mao
> >
> > Reviewed-by: Hao Wu
> > Reviewed-by: Chris Rauer
> > Sign
On Thu, Jan 27, 2022 at 6:55 AM Corey Minyard wrote:
> On Wed, Jan 26, 2022 at 04:09:03PM -0800, Hao Wu wrote:
> > Hi,
> >
> > Sorry for the late reply. I'm not sure what "auto-increment" means here.
>
> The question is: When a value is read, does the ad
ing PMBus devices or devices which need GPIO lines to be
> connected).
>
> Signed-off-by: Peter Maydell
>
Reviewed-by: Hao Wu
> ---
> Feel free to suggest other i2c devices that should be marked
> as in the group; as I say, I erred on the side of not putting
> devi
On Tue, Feb 8, 2022 at 9:23 AM Peter Maydell
wrote:
> For arm boards with an i2c bus which a user could reasonably
> want to plug arbitrary devices, add 'imply I2C_DEVICES' to the
> Kconfig stanza.
>
> Signed-off-by: Peter Maydell
>
Reviewed-by: Hao Wu
> ---
> A
AM Patrick Venture wrote:
>
>
> On Mon, Jan 17, 2022 at 6:05 AM Corey Minyard wrote:
>
>> On Sun, Jan 09, 2022 at 06:17:34PM -0800, Patrick Venture wrote:
>> > On Fri, Jan 7, 2022 at 7:04 PM Patrick Venture
>> wrote:
>> >
>> > > From: Hao Wu
&g
Signed-off-by: Hao Wu
Reviwed-by: Patrick Venture
---
hw/arm/meson.build | 2 +-
hw/arm/npcm8xx_boards.c | 257 +++
include/hw/arm/npcm8xx.h | 20 +++
3 files changed, 278 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/npcm8xx_boards.c
The NPCM8xx GCR device can be accessed with 64-bit memory operations.
This patch supports that.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
---
hw/misc/npcm_gcr.c | 98 +---
hw/misc/trace-events | 4 +-
2 files changed, 77 insertions(+), 25
.
Implementation of these clocks might be required when implementing
these modules.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
---
hw/misc/meson.build | 2 +-
hw/misc/{npcm7xx_clk.c => npcm_clk.c} | 238 ++
hw/misc/trace-eve
The file contains a basic NPCM8XX SOC file. It's forked
from the NPCM7XX SOC with some changes.
Signed-off-by: Hao Wu
Reviwed-by: Patrick Venture
Reviwed-by: Titus Rwantare
---
configs/devices/aarch64-softmmu/default.mak | 1 +
hw/arm/Kconfig | 11 +
hw/arm
be found at:
https://github.com/Nuvoton-Israel/openbmc/tree/npcm-v2.10/meta-evb/meta-evb-nuvoton/meta-evb-npcm845
The patch set can boot the evaluation board image built from the source
above to login prompt.
Hao Wu (11):
docs/system/arm: Add Description for NPCM8XX SoC
hw/ssi: Make flash size
This allows different FIUs to have different flash sizes, useful
in NPCM8XX which has multiple different sized FIU modules.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
---
hw/arm/npcm7xx.c | 6 ++
hw/ssi/npcm7xx_fiu.c | 6 ++
include/hw/ssi/npcm7xx_fiu.h | 1
NPCM8XX has a different set of global control registers than 7XX.
This patch supports that.
Signed-off-by: Hao Wu
Reviwed-by: Titus Rwantare
---
MAINTAINERS | 9 +-
hw/misc/meson.build | 2 +-
hw/misc/npcm7xx_gcr.c
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