This is a collection of patches that make minor fixes to
the models for various ARM devices.
--Mark Langsdorf
Calxeda, Inc.
From: juha.riihim...@nokia.com
Conflicts:
target-arm/cpu.h
target-arm/helper.c
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
target-arm/cpu.h |4 +
target-arm/helper.c | 556
+-
target-arm/machine.c
From: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
hw/arm_gic.c | 10 --
1 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index 9b52119
From: Rob Herring rob.herr...@calxeda.com
Use AHCIState instead of AHCIPCIState so the function can be used for
non-PCI based AHCI controllers.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
hw/ide/ahci.c | 14
From: Rob Herring rob.herr...@calxeda.com
Add support for ahci on sysbus.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
hw/ide/ahci.c | 35 +++
1 files changed, 35 insertions(+), 0 deletions
From: Rob Herring rob.herr...@calxeda.com
This is just a dummy device for ARM L2 cache controllers.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Makefile.target |2 +-
hw/arm_l2x0.c | 109
This adds very basic support for xgmac block. Missing things include:
- statistics counters
- WoL support
- rx checksum offload
- chained descriptors (only linear descriptor ring)
- broadcast and multicast handling
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf
Use qdev properties to allow board modelers to set the frequencies
for the sp804 timer. Each of the sp804's timers can have an
individual frequency or they share the frequency by default.
The timers default to 1MHz.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
hw/arm_timer.c
From: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
Conflicts:
target-arm/cpu.h
target-arm/helper.c
---
target-arm/cpu.h|1 +
target-arm/helper.c |7 +++
2 files
From: Rob Herring rob.herr...@calxeda.com
Add power control and non-secure access ctrl registers
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
hw/a9mpcore.c | 26 --
1 files changed, 24 insertions(+), 2
the security extensions.
I'm not sure what changes you want made here. I can resubmit with
the comment. But I don't know how qemu piggybacks the v7M NVIC so I
don't understand what you want done.
--Mark Langsdorf
Calxeda, Inc.
On 12/20/2011 01:48 PM, Peter Maydell wrote:
On 20 December 2011 19:10, Mark Langsdorf mark.langsd...@calxeda.com wrote:
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 816c4c4..37110bc 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2197,6 +2197,13 @@ uint32_t
On 12/20/2011 02:24 PM, Peter Maydell wrote:
On 20 December 2011 19:15, Mark Langsdorf mark.langsd...@calxeda.com wrote:
This adds very basic support for xgmac block. Missing things include:
- statistics counters
- WoL support
- rx checksum offload
- chained descriptors (only linear
From: Rob Herring rob.herr...@calxeda.com
Implement handling for the RAZ/WI gic security registers.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v1
Moved handling back inside the 0-0x100 block
Added
Use qdev properties to allow board modelers to set the frequencies
for the sp804 timer. Each of the sp804's timers can have an
individual frequency. The timers default to 1MHz.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v1
Simplified multiple timer frequency
This is a collection of fixes and additions to the models for various ARM
devices. These changes are needed to support the forthcoming Calxeda
Highbank SoC model.
Makefile.target |2 +
hw/a9mpcore.c | 36 -
hw/arm_gic.c|6 +
hw/arm_l2x0.c | 173
From: Rob Herring rob.herr...@calxeda.com
Add support for ahci on sysbus.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
hw/ide/ahci.c | 35 +++
1 files changed, 35 insertions(+), 0 deletions
...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v1
Reformated most lines to fit within 80 columns
Removed a bunch of unused variables in the state structures
Got rid of some camelcase structure names
Added vmstate support
From: Rob Herring rob.herr...@calxeda.com
Add power control and non-secure access ctrl registers
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v1:
Added VMState support
Checked alignment of writes
From: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
hw/a9mpcore.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/hw/a9mpcore.c b/hw/a9mpcore.c
index 875ae98..93b0498
Add a cp15 config_base_register that currently defaults to 0.
After the QOM CPU support is added, the value will be properly
set to the periphal base value.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v1
renamed the register
added comments about how
From: Rob Herring rob.herr...@calxeda.com
Use AHCIState instead of AHCIPCIState so the function can be used for
non-PCI based AHCI controllers.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
hw/ide/ahci.c | 14 +++---
hw
From: Rob Herring rob.herr...@calxeda.com
This is just a dummy device for ARM L2 cache controllers, based on the
pl310. The cache type parameter can be defined by a property value
and has a meaningful default.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf
This is a collection of fixes and additions to the models for various ARM
devices. These changes are needed to support the forthcoming Calxeda
Highbank SoC model.
Makefile.target |2 +
hw/a9mpcore.c | 45 +-
hw/arm11mpcore.c|2 +-
hw/arm_gic.c| 46 ---
Add a cp15 config_base_register that currently defaults to 0.
After the QOM CPU support is added, the value will be properly
set to the periphal base value.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v2
Added test against op2
hanges from v1
renamed
From: Rob Herring rob.herr...@calxeda.com
Add support for ahci on sysbus.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v1, v2
Corrected indentation of PlatAHCIState members
Made plat_ahci_info
From: Rob Herring rob.herr...@calxeda.com
Implement handling for the RAZ/WI gic security registers.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
Changes from v2
None
Increase the maximum number of GIC interrupts for a9mp to 192, and
create a configurable property defaulting to 96 so that device
modelers can set the value appropriately for their SoC.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v2
Skipped
Changes from v1
From: Rob Herring rob.herr...@calxeda.com
This is just a dummy device for ARM L2 cache controllers, based on the
pl310. The cache type parameter can be defined by a property value
and has a meaningful default.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf
From: Rob Herring rob.herr...@calxeda.com
Add power control register to a9mpcore
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v2:
Better handling of byte and halfword writes to the power register
Use qdev properties to allow board modelers to set the frequencies
for the sp804 timer. Each of the sp804's timers can have an
individual frequency. The timers default to 1MHz.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v2
Comment correctly describes
From: Rob Herring rob.herr...@calxeda.com
Use AHCIState instead of AHCIPCIState so the function can be used for
non-PCI based AHCI controllers.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v1, v2
None
hw
...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v2
None
Changes from v1
Reformated most lines to fit within 80 columns
Removed a bunch of unused variables in the state structures
Got rid of some camelcase structure names
Added
On 12/27/2011 03:59 PM, Peter Maydell wrote:
On 27 December 2011 20:13, Mark Langsdorf mark.langsd...@calxeda.com wrote:
Increase the maximum number of GIC interrupts for a9mp to 192, and
create a configurable property defaulting to 96 so that device
modelers can set the value appropriately
On 12/27/2011 04:54 PM, Peter Maydell wrote:
On 27 December 2011 20:13, Mark Langsdorf mark.langsd...@calxeda.com wrote:
From: Rob Herring rob.herr...@calxeda.com
Use AHCIState instead of AHCIPCIState so the function can be used for
non-PCI based AHCI controllers.
Signed-off-by: Rob Herring
This is a collection of fixes and additions to the models for various
ARM devices. These changes are needed to support the forthcoming
Calxeda Highbank SoC model.
Makefile.target |2 +
hw/a9mpcore.c | 43 +-
hw/arm11mpcore.c| 14 +-
hw/arm_gic.c| 63 +---
From: Rob Herring rob.herr...@calxeda.com
Add power control register to a9mpcore
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
Changes from v3
None
Changes from v2
appropriately.
Set the maximum theoretically number of GIC interrupts to 1020 and
update the save/restore code to only use the appropriate number for
each SoC.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v3
Increase maximum number of GIC interrupts to 1020
From: Rob Herring rob.herr...@calxeda.com
Implement handling for the RAZ/WI gic security registers.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
Changes from v2, v3
None
Use qdev properties to allow board modelers to set the frequencies
for the sp804 timer. Each of the sp804's timers can have an
individual frequency. The timers default to 1MHz.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
Changes
...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v3
Added debug macro and cleaned up some debug code
Refitted all lines to fit within 80 columns
Changes from v2
None
Changes from v1
Reformated most lines to fit within 80 columns
From: Rob Herring rob.herr...@calxeda.com
This is just a dummy device for ARM L2 cache controllers, based on the
pl310. The cache type parameter can be defined by a property value
and has a meaningful default.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf
Add a cp15 config_base_register that currently defaults to 0.
After the QOM CPU support is added, the value will be properly
set to the periphal base value.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
Changes from v3
Use qdev properties to allow board modelers to set the frequencies
for the sp804 timer. Each of the sp804's timers can have an
individual frequency. The timers default to 1MHz.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
Reviewed
appropriately.
Set the maximum theoretically number of GIC interrupts to 1020 and
update the save/restore code to only use the appropriate number for
each SoC.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v4
None
Changes from v3
Increase maximum number of GIC
From: Rob Herring rob.herr...@calxeda.com
Implement handling for the RAZ/WI gic security registers.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
Changes from v2, v3, v4
...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v4
None
Changes from v3
Added debug macro and cleaned up some debug code
Refitted all lines to fit within 80 columns
Changes from v2
None
Changes from v1
Reformated most lines to fit
From: Rob Herring rob.herr...@calxeda.com
Add power control register to a9mpcore
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
Changes from v3, v4
None
Changes from v2
This is a collection of fixes and additions to the models for various
ARM devices. These changes are needed to support the forthcoming
Calxeda Highbank SoC model.
Makefile.target |2 +
hw/a9mpcore.c | 43 +-
hw/arm11mpcore.c| 14 +-
hw/arm_gic.c| 63 +---
Add a cp15 config_base_register that currently defaults to 0.
After the QOM CPU support is added, the value will be properly
set to the periphal base value.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
Changes from v3, v4
From: Rob Herring rob.herr...@calxeda.com
This is just a dummy device for ARM L2 cache controllers, based on the
pl310. The cache type parameter can be defined by a property value
and has a meaningful default.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf
On 01/04/2012 08:32 AM, Peter Maydell wrote:
On 29 December 2011 16:19, Mark Langsdorf mark.langsd...@calxeda.com wrote:
Add a cp15 config_base_register that currently defaults to 0.
After the QOM CPU support is added, the value will be properly
set to the periphal base value.
Signed-off
Add dummy register support for the cp15, CRn=c15 registers.
config_base_register and power_control_register currently
default to 0, but may have improved support after the QOM
CPU patches are finished.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v5
Added
On 01/04/2012 11:50 AM, Peter Maydell wrote:
On 4 January 2012 16:53, Mark Langsdorf mark.langsd...@calxeda.com wrote:
+} else if ((op1 == 0) (op2 == 0)) {
+/* power_control should be set to maximum latency. Again,
+ default to 0 and set
Add dummy register support for the cp15, CRn=c15 registers.
config_base_register and power_control_register currently
default to 0, but may have improved support after the QOM
CPU patches are finished.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v6
Added
Add dummy register support for the cp15, CRn=c15 registers and
for c1 SCR.
config_base_register and power_control_register currently
default to 0, but may have improved support after the QOM
CPU patches are finished.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v7
On 01/04/2012 06:22 PM, Peter Maydell wrote:
On 5 January 2012 00:14, Mark Langsdorf mark.langsd...@calxeda.com wrote:
Add dummy register support for the cp15, CRn=c15 registers and
for c1 SCR.
Can you drop the SCR code, please? This needs to be done properly
as part of trustzone support
Add dummy register support for the cp15, CRn=c15 registers.
config_base_register and power_control_register currently
default to 0, but may have improved support after the QOM
CPU patches are finished.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v8
Removed
From: Rob Herring rob.herr...@calxeda.com
Add support for ahci on sysbus.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v1, v2
Corrected indentation of PlatAHCIState members
Made plat_ahci_info
From: Rob Herring rob.herr...@calxeda.com
Use AHCIState instead of AHCIPCIState so the function can be used for
non-PCI based AHCI controllers.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v1, v2
None
hw
On 01/05/2012 08:26 AM, Alexander Graf wrote:
On 05.01.2012, at 15:16, Andreas Färber wrote:
Am 05.01.2012 14:52, schrieb Mark Langsdorf:
From: Rob Herring rob.herr...@calxeda.com
Add support for ahci on sysbus.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark
On 01/05/2012 09:33 AM, Peter Maydell wrote:
On 5 January 2012 13:16, Mark Langsdorf mark.langsd...@calxeda.com wrote:
Add dummy register support for the cp15, CRn=c15 registers.
config_base_register and power_control_register currently
default to 0, but may have improved support after
is part of
Trustzone. I may have missed something, though.
--Mark Langsdorf
Calxeda, Inc.
This patch series adds support for the Calxeda Highbank SoC.
It depends on my previous patch series various ARM fixes for
Calxeda Highbank and ahci: convert ahci_reset to use AHCIState.
Some of the patches are carried voer from Various ARM fixes
for Calxeda Highbank and were reviewed but not
From: Rob Herring rob.herr...@calxeda.com
Add support for ahci on sysbus.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v3
Renamed plat-ahci to sysbus-ahci
Changes from v1, v2
Corrected indentation
...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v4
None
Changes from v3
Added debug macro and cleaned up some debug code
Refitted all lines to fit within 80 columns
Changes from v2
None
Changes from v1
Reformated most lines to fit
From: Rob Herring rob.herr...@calxeda.com
Adds support for Calxeda's Highbank SoC.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Makefile.target |1 +
hw/highbank.c | 227
appropriately.
Set the maximum theoretically number of GIC interrupts to 1020 and
update the save/restore code to only use the appropriate number for
each SoC.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v4, v5
None
Changes from v3
Increase maximum number
From: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
target-arm/cpu.h |3 ++-
target-arm/helper.c |9 +
target-arm/machine.c |2 ++
3 files changed, 13 insertions(+), 1
On 01/06/2012 10:29 AM, Peter Maydell wrote:
On 5 January 2012 20:02, Mark Langsdorf mark.langsd...@calxeda.com wrote:
From: Rob Herring rob.herr...@calxeda.com
Adds support for Calxeda's Highbank SoC.
Is there a test kernel image/etc we can use to confirm that this all works?
The 3.2
On 01/06/2012 11:04 AM, Peter Maydell wrote:
On 6 January 2012 16:58, Mark Langsdorf mark.langsd...@calxeda.com wrote:
On 01/06/2012 10:29 AM, Peter Maydell wrote:
+sysram = g_new(MemoryRegion, 1);
+memory_region_init_ram(sysram, highbank.sysram, 0x8000
On 01/06/2012 10:29 AM, Peter Maydell wrote:
On 5 January 2012 20:02, Mark Langsdorf mark.langsd...@calxeda.com wrote:
+static void hb_regs_write(void *opaque, target_phys_addr_t offset,
+ uint64_t value, unsigned size)
+{
+uint32_t *regs = opaque
This patch series adds support for the Calxeda Highbank SoC.
It depends on my previous patch series various ARM fixes for
Calxeda Highbank and ahci: convert ahci_reset to use AHCIState.
Some of the patches are carried voer from Various ARM fixes
for Calxeda Highbank and were reviewed but not
From: Rob Herring rob.herr...@calxeda.com
Add support for ahci on sysbus.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v3
Renamed plat-ahci to sysbus-ahci
Changes from v1, v2
Corrected indentation
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
hw/arm_timer.c |3 ---
1 files changed, 0 insertions(+), 3 deletions(-)
diff --git a/hw/arm_timer.c b/hw/arm_timer.c
index 60e1c63..15d493f 100644
--- a/hw/arm_timer.c
+++ b/hw/arm_timer.c
@@ -272,11 +272,8 @@ static int sp804_init
From: Rob Herring rob.herr...@calxeda.com
Adds support for Calxeda's Highbank SoC.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v1
Restructed the loading of sysram.bin and made it more clearly optional
From: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
target-arm/cpu.h |3 ++-
target-arm/helper.c |9 +
target-arm/machine.c |2 ++
3 files changed, 13 insertions(+), 1
...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v4
None
Changes from v3
Added debug macro and cleaned up some debug code
Refitted all lines to fit within 80 columns
Changes from v2
None
Changes from v1
Reformated most lines to fit
appropriately.
Set the maximum theoretically number of GIC interrupts to 1020 and
update the save/restore code to only use the appropriate number for
each SoC.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v5
Clarify the commit message
Rename GIC_NIRQ
From: Rob Herring rob.herr...@calxeda.com
Add support for ahci on sysbus.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
Reviewed-by: Andreas Färber afaer...@suse.de
---
Changes from v7
None
Changes from v5, v6
Skipped
From: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
Changes from v7
None
Changes from v1, v2, v3, v4, v5, v6
Skipped
target
...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v7
None
Changes from v6
Skipped
Changes from v5
removed c_phyaddr
Changes from v4
None
Changes from v3
Added debug macro and cleaned up some debug code
Refitted all lines
From: Rob Herring rob.herr...@calxeda.com
Adds support for Calxeda's Highbank SoC.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v7
None
Changes from v3, v4, v5, v6
Skipped
Changes from v2
The current comment says that the arm_timers are restricted to between
32 KHz and 1 MHz, but sp804 TRM does not specify those limits.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
Reviewed-by: Andreas Färber afaer...@suse.de
---
Changes from v7
None
Changes from v2, v3, v4, v5
This patch series adds support for the Calxeda Highbank SoC.
It depends on my previous patch series various ARM fixes for
Calxeda Highbank and ahci: convert ahci_reset to use AHCIState.
Some of the patches are carried voer from Various ARM fixes
for Calxeda Highbank and were reviewed but not
appropriately.
Set the maximum theoretically number of GIC interrupts to 1020 and
update the save/restore code to only use the appropriate number for
each SoC.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v7
Removed unnecessary vmstate_register
Changes from v6
appropriately.
Set the maximum theoretically number of GIC interrupts to 1020 and
update the save/restore code to only use the appropriate number for
each SoC.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v5
Clarify the commit message
Rename GIC_NIRQ
From: Rob Herring rob.herr...@calxeda.com
Add support for ahci on sysbus.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v4
replaced all references to Plat|plat_ with sysbus_
made the number of ports
The current comment says that the arm_timers are restricted to between
32 KHz and 1 MHz, but sp804 TRM does not specify those limits.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
Reviewed-by: Andreas Färber afaer...@suse.de
---
Changes from v7, v8
None
Changes from v2, v3, v4
From: Rob Herring rob.herr...@calxeda.com
Add support for ahci on sysbus.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
Reviewed-by: Andreas Färber afaer...@suse.de
---
Changes from v7, v8
None
Changes from v5, v6
From: Rob Herring rob.herr...@calxeda.com
Adds support for Calxeda's Highbank SoC.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v1
Restructed the loading of sysram.bin and made it more clearly optional
From: Rob Herring rob.herr...@calxeda.com
Adds support for Calxeda's Highbank SoC.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
Changes from v7, v8
None
Changes from v3
appropriately.
Set the maximum theoretical number of GIC interrupts to 1020 and
update the save/restore code to only use the appropriate number for
each SoC.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
Reviewed-by: Andreas Färber afaer...@suse.de
---
Changes from v8
Removed comments
From: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
target-arm/cpu.h |3 ++-
target-arm/helper.c |9 +
target-arm/machine.c |2 ++
3 files changed, 13 insertions(+), 1
appropriately.
Set the maximum theoretical number of GIC interrupts to 1020 and
update the save/restore code to only use the appropriate number for
each SoC.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v6
Removed trailing whitespace
armv7m_nvic uses num_irq
...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v4
None
Changes from v3
Added debug macro and cleaned up some debug code
Refitted all lines to fit within 80 columns
Changes from v2
None
Changes from v1
Reformated most lines to fit
The current comment says that the arm_timers are restricted to between
32 KHz and 1 MHz, but sp804 TRM does not specify those limits.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
Reviewed-by: Andreas Färber afaer...@suse.de
---
Changes from v2, v3, v4, v5, v6
Skipped
Changes
...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v6
Skipped
Changes from v5
removed c_phyaddr
Changes from v4
None
Changes from v3
Added debug macro and cleaned up some debug code
Refitted all lines to fit within 80 columns
Changes
From: Rob Herring rob.herr...@calxeda.com
Adds support for Calxeda's Highbank SoC.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v3, v4, v5, v6
Skipped
Changes from v2
Created a reset function
From: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
Changes from v7, v8
None
Changes from v1, v2, v3, v4, v5, v6
Skipped
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