Re: [Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support

2018-02-02 Thread Michael Clark
On Mon, Jan 29, 2018 at 12:33 PM, Jim Wilson wrote: > On Wed, Jan 24, 2018 at 3:47 PM, Richard Henderson > wrote: > > On 01/24/2018 10:58 AM, Jim Wilson wrote: > >> Although, looking at this again, I see another statement in a > >> different place that says: > >> > >> Except when otherwise state

Re: [Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support

2018-01-29 Thread Jim Wilson
On Wed, Jan 24, 2018 at 3:47 PM, Richard Henderson wrote: > On 01/24/2018 10:58 AM, Jim Wilson wrote: >> Although, looking at this again, I see another statement in a >> different place that says: >> >> Except when otherwise stated, if the result of a floating-point operation is >> NaN, it is the

Re: [Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support

2018-01-24 Thread Richard Henderson
On 01/24/2018 10:58 AM, Jim Wilson wrote: > I think that qemu is correct here, and that you want to use float32_chs. Ok. > Although, looking at this again, I see another statement in a > different place that says: > > Except when otherwise stated, if the result of a floating-point operation is >

Re: [Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support

2018-01-24 Thread Jim Wilson
On Tue, Jan 23, 2018 at 4:15 PM, Richard Henderson wrote: > Ok. Now it depends on what result you care about for madd specifically. > > If, like x86 and Power, fmsub returns the (silenced) original input NaN, you > want the float_muladd_* flags. > > If, like ARM, fmsub returns the (silenced) nega

Re: [Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support

2018-01-24 Thread Michael Clark
On Wed, Jan 24, 2018 at 8:16 AM, Richard Henderson < richard.hender...@linaro.org> wrote: > On 01/23/2018 05:31 PM, Michael Clark wrote: > > For the meantime we've greatly simplified cpu_mmu_index to just return > the > > processor mode as well as adding the processor mode to > cpu_get_tb_cpu_stat

Re: [Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support

2018-01-24 Thread Richard Henderson
On 01/23/2018 05:31 PM, Michael Clark wrote: > For the meantime we've greatly simplified cpu_mmu_index to just return the > processor mode as well as adding the processor mode to cpu_get_tb_cpu_state > flags. cpu_mmu_index previously returned a permutation of env->priv > (containing > processer mo

Re: [Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support

2018-01-23 Thread Jim Wilson
On Tue, Jan 23, 2018 at 3:35 PM, Michael Clark wrote: > We want minimum number (minnum). It's been added to the draft spec and will > be in riscv-spec-v2.3.pdf In the preface of the draft, it says • Defined the signed-zero behavior of FMIN.fmt and FMAX.fmt, and changed their behavior on signaling

Re: [Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support

2018-01-23 Thread Michael Clark
On Tue, Jan 23, 2018 at 4:01 PM, Richard Henderson < richard.hender...@linaro.org> wrote: > On 01/23/2018 01:37 PM, Michael Clark wrote: > > > > > > On Wed, Jan 3, 2018 at 12:10 PM, Richard Henderson > > mailto:richard.hender...@linaro.org>> > wrote: > > > > On 01/02/2018 04:44 PM, Michael Cla

Re: [Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support

2018-01-23 Thread Richard Henderson
On 01/23/2018 03:15 PM, Michael Clark wrote: > > +uint64_t helper_fmsub_s(CPURISCVState *env, uint64_t frs1, uint64_t > frs2, > > +                        uint64_t frs3, uint64_t rm) > > +{ > > +    require_fp; > > +    set_float_rounding_mode(RM, &env->fp_status); > > +   

Re: [Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support

2018-01-23 Thread Richard Henderson
On 01/23/2018 01:37 PM, Michael Clark wrote: > > > On Wed, Jan 3, 2018 at 12:10 PM, Richard Henderson > mailto:richard.hender...@linaro.org>> wrote: > > On 01/02/2018 04:44 PM, Michael Clark wrote: > > +/* convert RISC-V rounding mode to IEEE library numbers */ > > +unsigned int ieee

Re: [Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support

2018-01-23 Thread Michael Clark
On Tue, Jan 23, 2018 at 3:15 PM, Michael Clark wrote: > > > On Wed, Jan 3, 2018 at 12:10 PM, Richard Henderson < > richard.hender...@linaro.org> wrote: > >> On 01/02/2018 04:44 PM, Michael Clark wrote: >> > +/* convert RISC-V rounding mode to IEEE library numbers */ >> > +unsigned int ieee_rm[] =

Re: [Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support

2018-01-23 Thread Michael Clark
On Wed, Jan 3, 2018 at 12:10 PM, Richard Henderson < richard.hender...@linaro.org> wrote: > On 01/02/2018 04:44 PM, Michael Clark wrote: > > +/* convert RISC-V rounding mode to IEEE library numbers */ > > +unsigned int ieee_rm[] = { > > static const. > > > +/* obtain rm value to use in computation

Re: [Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support

2018-01-23 Thread Michael Clark
On Wed, Jan 3, 2018 at 12:10 PM, Richard Henderson < richard.hender...@linaro.org> wrote: > On 01/02/2018 04:44 PM, Michael Clark wrote: > > +/* convert RISC-V rounding mode to IEEE library numbers */ > > +unsigned int ieee_rm[] = { > > static const. Done. > +/* obtain rm value to use in comput

Re: [Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support

2018-01-03 Thread Richard Henderson
On 01/02/2018 04:44 PM, Michael Clark wrote: > +/* convert RISC-V rounding mode to IEEE library numbers */ > +unsigned int ieee_rm[] = { static const. > +/* obtain rm value to use in computation > + * as the last step, convert rm codes to what the softfloat library expects > + * Adapted from Spik