On Wed, Nov 27, 2019 at 08:09:18AM +0100, Gerd Hoffmann wrote:
> On Mon, Nov 25, 2019 at 07:26:17PM -0800, Your Real Name wrote:
> > From 9ca6590769692b99e98acf48acc3ce700238e451 Mon Sep 17 00:00:00 2001
> > From: gaobin
> > Date: Thu, 19 Sep 2019 22:47:43 -0700
> &g
On Wed, Nov 27, 2019 at 08:03:44AM +0100, Gerd Hoffmann wrote:
> On Mon, Nov 25, 2019 at 07:20:46PM -0800, Your Real Name wrote:
> ^^
> Please fix your git config.
Will fix this in my next revision. Thanks.
>
> c
On Wed, Nov 27, 2019 at 08:08:23AM +0100, Gerd Hoffmann wrote:
> On Mon, Nov 25, 2019 at 07:25:26PM -0800, Your Real Name wrote:
> > From 3bf91481863ec504d113aa6b94827bf92840e291 Mon Sep 17 00:00:00 2001
> > From: gaobin
> > Date: Thu, 19 Sep 2019 11:23:04 -0700
> &g
On Wed, Nov 27, 2019 at 08:37:38AM +0100, Gerd Hoffmann wrote:
> Hi,
>
> > Some Intel PCHs integrate pci uarts which are used for serial
> > port debugging. For compatibility purpose, BIOS implementation
> > may assign 0x3f8 to the pci uart's io bar at PEI stage, later
> > during DXE stage the
On Tue, Nov 26, 2019 at 11:29:09AM +0100, Paul Menzel wrote:
> Dear gaobin,
>
>
> Thank you for your changes. Some nit picks:
>
> Please configure git with `git config --global user.name "…"` to use
> your real name. You can also use `git send-email` to send t
On Tue, Dec 03, 2019 at 11:27:39AM +0100, Gerd Hoffmann wrote:
> > > > As a result, we can't use the hard coded IO port 0x3f8
> > > > in SeaBIOS for debugging. Instead, we need read the port base
> > > > address from the pci uart's BAR, either an IO BAR, or a 32bit
> > > > memory BAR.
> > >
> > >
On Tue, Dec 03, 2019 at 10:55:27AM +0100, Gerd Hoffmann wrote:
> Hi,
>
> > > > +// On real hardware especially server platforms, the bus number
> > > > +// could run up to the top value, i.e. 0xff
> > > > +if (CONFIG_CSM)
> > > > +extraroots = 0xff;
> > >
> > > What exactly
On Tue, Dec 03, 2019 at 11:07:36AM +0100, Gerd Hoffmann wrote:
> > > > +static int rom_instance;
> > > > +
> > >
> > > What is this? Not used anywhere in the patch ...
> >
> > This is required on calling getRomPriority().
> > Please check below lines in the patch.
> >
On Thu, Dec 05, 2019 at 06:52:46AM +0100, Gerd Hoffmann wrote:
> Hi,
>
> > I'm ok to use Base-Class/Sub-Class = 0x07/0x00 to filter out the PCI serial
> > devices and choose the first one as the debug port. However, debug port
> > needs
> > to be enabled early, before seabios scans PCI bus. I
On Thu, Dec 05, 2019 at 07:06:37AM +0100, Gerd Hoffmann wrote:
> Hi,
>
> > The priority value(the last argument we pass to boot_add_bev()) will affect
> > the order of the boot list. The getRomPriority() will calculate the final
> > priority based on the system provided BBS, etc. This is even
On Mon, Dec 09, 2019 at 01:09:11PM +0100, Gerd Hoffmann wrote:
> On Fri, Dec 06, 2019 at 08:17:04PM -0800, Your Real Name wrote:
> > On Thu, Dec 05, 2019 at 07:06:37AM +0100, Gerd Hoffmann wrote:
> > > Hi,
> > >
> > > > The priority value(th
On Mon, Dec 09, 2019 at 01:18:52PM +0100, Gerd Hoffmann wrote:
> On Fri, Dec 06, 2019 at 08:05:22PM -0800, Your Real Name wrote:
> > On Thu, Dec 05, 2019 at 06:52:46AM +0100, Gerd Hoffmann wrote:
> > > Hi,
> > >
> > > > I'm ok to use Base-Class/Sub-
>From 7dd0e8b98c71254148180b3cc432de1c4936526c Mon Sep 17 00:00:00 2001
From: gaobin
Date: Thu, 19 Sep 2019 11:17:46 -0700
Subject: [PATCH 1/4] csm: Call pci_probe_devices() late until PrepareToBoot is
invoked by UEFI
On real hardware, some PCI devices are not detectable when UEFI
BIOS invokes
>From 3bf91481863ec504d113aa6b94827bf92840e291 Mon Sep 17 00:00:00 2001
From: gaobin
Date: Thu, 19 Sep 2019 11:23:04 -0700
Subject: [PATCH 2/4] pci: Allow scanning pci bus number up to 255 in CSM mode
On real hardware especially server platforms, there are many pci
devices, bridges, either SoC
>From 9ca6590769692b99e98acf48acc3ce700238e451 Mon Sep 17 00:00:00 2001
From: gaobin
Date: Thu, 19 Sep 2019 22:47:43 -0700
Subject: [PATCH 3/4] csm: Enable boot from pci option rom
In csm mode, the bev pointer of the pci option rom was not
added to the bootentry list, resulting in failure to
>From f65c435b8e3caf7249a3fb25150e7055898ccc12 Mon Sep 17 00:00:00 2001
From: gaobin
Date: Fri, 18 Oct 2019 23:00:21 -0700
Subject: [PATCH 4/4] serialio: Support for pci serial ports
Some Intel PCHs integrate pci uarts which are used for serial
port debugging. For compatibility purpose, BIOS
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