Re: [SeaBIOS] [RFC v2 0/3] Support multiple pci domains in pci_device

Hi Kevin, On 08/28/2018 08:02 PM, Kevin O'Connor wrote: On Tue, Aug 28, 2018 at 12:14:58PM +0200, Gerd Hoffmann wrote: Hi, Where is the pxb-pcie device? :$somewhere? Or $domain:00:00.0? :$somewhere (On PCI domain 0) Cool, so we don't have an chicken-and-egg issue. If we

Re: [SeaBIOS] [RFC v2 0/3] Support multiple pci domains in pci_device

Hi Gerd, On 08/28/2018 09:07 AM, Gerd Hoffmann wrote: Hi, Since we will not use all 256 buses of an extra PCI domain, I think this space will allow us to support more PCI domains. Depends on the use case I guess. If you just need many pcie devices this probably doesn't help. If you want

Re: [SeaBIOS] [RFC v2 0/3] Support multiple pci domains in pci_device

Hi Gerd On 08/28/2018 07:12 AM, Zihan Yang wrote: Gerd Hoffmann 于2018年8月27日周一 上午7:04写道： Hi, However, QEMU only binds port 0xcf8 and 0xcfc to bus pcie.0. To avoid bus confliction, we should use other port pairs for busses under new domains. I would skip support for IO based

Re: [SeaBIOS] [PATCH v3 3/3] pci: recognize RH PCI legacy bridge resource reservation capability

On 08/27/2018 05:22 AM, Liu, Jing2 wrote: Hi Marcel, On 8/25/2018 11:59 PM, Marcel Apfelbaum wrote: On 08/24/2018 11:53 AM, Jing Liu wrote: Enable the firmware recognizing RedHat legacy PCI bridge device ID, so QEMU can reserve additional PCI bridge resource capability. Change the debug

Re: [SeaBIOS] [RFC v2 2/3] pci_device: Add pci domain support

On 08/09/2018 08:43 AM, Zihan Yang wrote: Most part of seabios assume only PCI domain 0. This patch adds support for multiple domain in pci devices, which involves some API changes. For compatibility, interfaces such as pci_config_read[b|w|l] still exist so that existing domain 0 devices

Re: [SeaBIOS] [RFC v2 0/3] Support multiple pci domains in pci_device

Hi, On 08/09/2018 08:43 AM, Zihan Yang wrote: Currently seabios assumes there is only one pci domain(0), and almost everything operates on pci domain 0 by default. This patch aims to add multiple pci domain support for pci_device, while reserve the original API for compatibility. This is a

Re: [SeaBIOS] [PATCH v3 3/3] pci: recognize RH PCI legacy bridge resource reservation capability

On 08/24/2018 11:53 AM, Jing Liu wrote: Enable the firmware recognizing RedHat legacy PCI bridge device ID, so QEMU can reserve additional PCI bridge resource capability. Change the debug level lower to 3 when it is non-QEMU bridge. Signed-off-by: Jing Liu --- src/fw/pciinit.c | 50

Re: [SeaBIOS] [PATCH v2 2/3] pci: clean up the debug message for pci capability found

.\n"); return 0; } } Reviewed-by: Marcel Apfelbaum Thanks, Marcel ___ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios

Re: [SeaBIOS] [PATCH v2 1/3] pci: fix the return value for truncated capability

return 0; } } return cap; Reviewed-by: Marcel Apfelbaum Thanks, Marcel ___ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios

Re: [SeaBIOS] [PATCH] pci: fix 'io hints' capability for RedHat PCI bridges

Hi, I forgot to CC Kevin and Aleksandr (the original committer). Thanks, Marcel On 11/01/2018 22:15, Marcel Apfelbaum wrote: Commit ec6cb17f (pci: enable RedHat PCI bridges to reserve additional resources on PCI init) added a new vendor specific PCI capability for RedHat PCI

[SeaBIOS] [PATCH] pci: fix 'io hints' capability for RedHat PCI bridges

uot; which appears if the 'IO hints' capability is not present. Signed-off-by: Marcel Apfelbaum <mar...@redhat.com> --- src/fw/pciinit.c | 14 +- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index 7f0e439..3a2f747 100644 --- a/

Re: [SeaBIOS] [Qemu-devel] [PATCH v7 1/4] hw/pci: introduce pcie-pci-bridge device

On 20/09/2017 16:57, Eduardo Habkost wrote: On Wed, Sep 20, 2017 at 09:52:01AM +, Aleksandr Bezzubikov wrote: ср, 20 сент. 2017 г. в 10:13, Marcel Apfelbaum <mar...@redhat.com>: On 19/09/2017 23:34, Eduardo Habkost wrote: On Fri, Aug 18, 2017 at 02:36:47AM +0300, Aleksandr Bezz

Re: [SeaBIOS] [Qemu-devel] [PATCH v7 1/4] hw/pci: introduce pcie-pci-bridge device

On 20/09/2017 12:52, Aleksandr Bezzubikov wrote: ср, 20 сент. 2017 г. в 10:13, Marcel Apfelbaum <mar...@redhat.com <mailto:mar...@redhat.com>>: On 19/09/2017 23:34, Eduardo Habkost wrote: > On Fri, Aug 18, 2017 at 02:36:47AM +0300, Aleksandr Bezzubikov wrote: >

Re: [SeaBIOS] [Qemu-devel] [PATCH v7 1/4] hw/pci: introduce pcie-pci-bridge device

-to-PCI Bridge. Signed-off-by: Aleksandr Bezzubikov <zuban...@gmail.com> Reviewed-by: Marcel Apfelbaum <mar...@redhat.com> It's possible to crash QEMU by instantiating this device, with; $ qemu-system-ppc64 -machine prep -device pcie-pci-bridge qemu-system-ppc64: qemu/m

Re: [SeaBIOS] [PATCH RESEND v7 0/3] Red Hat PCI bridge resource reserve capability

On 10/09/2017 21:34, Aleksandr Bezzubikov wrote: пт, 18 авг. 2017 г. в 2:33, Aleksandr Bezzubikov >: Now PCI bridges get a bus range number on a system init, basing on currently plugged devices. That's why when one wants to hotplug

Re: [SeaBIOS] [PATCH v7 0/4] Generic PCIE-PCI Bridge

On 18/08/2017 2:36, Aleksandr Bezzubikov wrote: This series introduces a new device - Generic PCI Express to PCI bridge, and also makes all necessary changes to enable hotplug of the bridge itself and any device into the bridge. Hi, Series Tested-by: Marcel Apfelbaum <mar...@redhat.

Re: [SeaBIOS] [PATCH v6 0/4] Generic PCIE-PCI Bridge

On 13/08/2017 18:49, Aleksandr Bezzubikov wrote: This series introduces a new device - Generic PCI Express to PCI bridge, and also makes all necessary changes to enable hotplug of the bridge itself and any device into the bridge. Hi Aleksandr, Thanks for all the effort you put in this series.

Re: [SeaBIOS] [PATCH v6 0/3] Red Hat PCI bridge resource reserve capability

+ src/hw/pci.h| 1 + src/hw/pci_ids.h| 3 ++ src/hw/pcidevice.c | 24 - src/hw/pcidevice.h | 1 - src/hw/virtio-pci.c | 6 ++-- 8 files changed, 181 insertions(+), 33 deletions(-) create mode 100644 src/fw/dev-pci.h Hi, Series Test

Re: [SeaBIOS] [PATCH v6 3/3] pci: enable RedHat PCI bridges to reserve additional resource on PCI init

gt;r[type], s->bus_dev, type); // entry->bar is -1 if the entry represents a bridge region diff --git a/src/hw/pci_ids.h b/src/hw/pci_ids.h index 4ac73b4..38fa2ca 100644 --- a/src/hw/pci_ids.h +++ b/src/hw/pci_ids.h @@ -2263,6 +2263,9 @@ #define PCI_DEVICE_I

Re: [SeaBIOS] [PATCH v6 2/3] pci: add QEMU-specific PCI capability structure

Hat PCI bridges, i.e. QEMU cooperation. Reviewed-by: Marcel Apfelbaum <mar...@redhat.com> Thanks, Marcel Signed-off-by: Aleksandr Bezzubikov <zuban...@gmail.com> --- src/fw/dev-pci.h | 53 + 1 file changed, 53 insertions(+)

Re: [SeaBIOS] [PATCH v5 3/3] pci: enable RedHat PCI bridges to reserve additional resource on PCI init

On 11/08/2017 2:21, Aleksandr Bezzubikov wrote: In case of Red Hat Generic PCIE Root Port reserve additional buses and/or IO/MEM/PREF space, which values are provided in a vendor-specific capability. Signed-off-by: Aleksandr Bezzubikov --- src/fw/dev-pci.h | 2 +-

Re: [SeaBIOS] [PATCH v5 3/3] pci: enable RedHat PCI bridges to reserve additional resource on PCI init

On 11/08/2017 2:21, Aleksandr Bezzubikov wrote: In case of Red Hat Generic PCIE Root Port reserve additional buses and/or IO/MEM/PREF space, which values are provided in a vendor-specific capability. Hi Aleksandr, Signed-off-by: Aleksandr Bezzubikov ---

Re: [SeaBIOS] [PATCH v5 4/4] docs: update documentation considering PCIE-PCI bridge

After addressing my and Laszlo's comments: Reviewed-by: Marcel Apfelbaum <mar...@redhat.com> Thanks, Marcel ___ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios

Re: [SeaBIOS] [PATCH v5 2/4] hw/pci: introduce bridge-only vendor-specific capability to provide some hints to firmware

than that it looks OK to me. Signed-off-by: Aleksandr Bezzubikov <zuban...@gmail.com> Reviewed-by: Marcel Apfelbaum <mar...@redhat.com> --- hw/pci/pci_bridge.c | 54 + include/hw/pci/pci_bridge.h | 24 2 files

Re: [SeaBIOS] [PATCH v5 1/4] hw/pci: introduce pcie-pci-bridge device

dex e598b09..b33a34f 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -98,6 +98,7 @@ #define PCI_DEVICE_ID_REDHAT_PXB_PCIE0x000b #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c #define PCI_DEVICE_ID_REDHAT_XHCI0x000d +#define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e

Re: [SeaBIOS] [Qemu-devel] >256 Virtio-net-pci hotplug Devices

am using Seabios by default. I took all the measures from the Kernel time reported in syslog. As Seabios wasn't exhibiting any obvious scaling problem. Ray K -Original Message- From: Marcel Apfelbaum [mailto:mar...@redhat.com] Sent: Wednesday, August 2, 2017 5:43 AM To: Kinsella, Ray

Re: [SeaBIOS] [PATCH v4 2/5] hw/pci: introduce pcie-pci-bridge device

On 07/08/2017 19:42, Alexander Bezzubikov wrote: 2017-08-07 19:39 GMT+03:00 Marcel Apfelbaum <mar...@redhat.com>: On 05/08/2017 23:27, Aleksandr Bezzubikov wrote: Introduce a new PCIExpress-to-PCI Bridge device, which is a hot-pluggable PCI Express device and supports devices ho

Re: [SeaBIOS] [PATCH v4 3/5] hw/pci: introduce bridge-only vendor-specific capability to provide some hints to firmware

uint64_t pref_mem_reserve, + Error **errp); + #endif /* QEMU_PCI_BRIDGE_H */ With the name change, the layout looks good to me: Reviewed-by: Marcel Apfelbaum <mar...@redhat.com> Thanks, Marcel _

Re: [SeaBIOS] [PATCH v4 2/5] hw/pci: introduce pcie-pci-bridge device

On 05/08/2017 23:27, Aleksandr Bezzubikov wrote: Introduce a new PCIExpress-to-PCI Bridge device, which is a hot-pluggable PCI Express device and supports devices hot-plug with SHPC. Hi Aleksandr, This device is intended to replace the DMI-to-PCI Bridge in an overwhelming majority of

Re: [SeaBIOS] [PATCH v4 2/3] pci: add QEMU-specific PCI capability structure

On 07/08/2017 19:02, Alexander Bezzubikov wrote: 2017-08-07 18:52 GMT+03:00 Marcel Apfelbaum <mar...@redhat.com>: On 05/08/2017 23:29, Aleksandr Bezzubikov wrote: On PCI init PCI bridge devices may need some extra info about bus number to reserve, IO, memory and prefetchable memory

Re: [SeaBIOS] [PATCH v4 3/3] pci: enable RedHat PCI bridges to reserve additional buses on PCI init

On 05/08/2017 23:29, Aleksandr Bezzubikov wrote: In case of Red Hat Generic PCIE Root Port reserve additional buses, which number is provided in a vendor-specific capability. Hi Aleksandr, It seems the subject/commit description does not cover all that the patch does, not it also deals with

Re: [SeaBIOS] [PATCH v4 2/3] pci: add QEMU-specific PCI capability structure

On 05/08/2017 23:29, Aleksandr Bezzubikov wrote: On PCI init PCI bridge devices may need some extra info about bus number to reserve, IO, memory and prefetchable memory limits. QEMU can provide this with special vendor-specific PCI capability. This capability is intended to be used only for Red

Re: [SeaBIOS] [PATCH v3 2/3] pci: add QEMU-specific PCI capability structure

On 04/08/2017 23:47, Alexander Bezzubikov wrote: 2017-08-04 23:28 GMT+03:00 Laszlo Ersek <ler...@redhat.com>: On 08/04/17 20:59, Alexander Bezzubikov wrote: 2017-08-01 20:28 GMT+03:00 Alexander Bezzubikov <zuban...@gmail.com>: 2017-08-01 16:38 GMT+03:00 Marcel Apfelbaum <ma

Re: [SeaBIOS] [Qemu-devel] [PATCH v3 5/5] docs: update documentation considering PCIE-PCI bridge

On 03/08/2017 16:58, Laine Stump wrote: On 08/03/2017 06:29 AM, Marcel Apfelbaum wrote: On 03/08/2017 5:41, Laine Stump wrote: On 08/02/2017 01:58 PM, Marcel Apfelbaum wrote: On 02/08/2017 19:26, Michael S. Tsirkin wrote: On Wed, Aug 02, 2017 at 06:36:29PM +0300, Marcel Apfelbaum wrote: Can

Re: [SeaBIOS] [PATCH v3 1/5] hw/i386: allow SHPC for Q35 machine

On 03/08/2017 15:52, Michael S. Tsirkin wrote: On Sat, Jul 29, 2017 at 02:37:49AM +0300, Aleksandr Bezzubikov wrote: Unmask previously masked SHPC feature in _OSC method. Signed-off-by: Aleksandr Bezzubikov Hi Michael, This does not do what the subject says - it

Re: [SeaBIOS] [Qemu-devel] [PATCH v3 5/5] docs: update documentation considering PCIE-PCI bridge

On 03/08/2017 5:41, Laine Stump wrote: On 08/02/2017 01:58 PM, Marcel Apfelbaum wrote: On 02/08/2017 19:26, Michael S. Tsirkin wrote: On Wed, Aug 02, 2017 at 06:36:29PM +0300, Marcel Apfelbaum wrote: Can dmi-pci support shpc? why doesn't it? For compatibility? I don't know why, but the fact

Re: [SeaBIOS] [Qemu-devel] [PATCH v3 5/5] docs: update documentation considering PCIE-PCI bridge

On 02/08/2017 19:26, Michael S. Tsirkin wrote: On Wed, Aug 02, 2017 at 06:36:29PM +0300, Marcel Apfelbaum wrote: Can dmi-pci support shpc? why doesn't it? For compatibility? I don't know why, but the fact that it doesn't is the reason libvirt settled on auto-creating a dmi-pci bridge

Re: [SeaBIOS] [Qemu-devel] [PATCH v3 5/5] docs: update documentation considering PCIE-PCI bridge

On 02/08/2017 17:21, Marcel Apfelbaum wrote: On 02/08/2017 17:16, Laszlo Ersek wrote: On 08/02/17 15:47, Michael S. Tsirkin wrote: On Wed, Aug 02, 2017 at 12:23:46AM +0200, Laszlo Ersek wrote: On 08/01/17 23:39, Michael S. Tsirkin wrote: On Wed, Aug 02, 2017 at 12:33:12AM +0300, Alexander

Re: [SeaBIOS] [Qemu-devel] [PATCH v3 5/5] docs: update documentation considering PCIE-PCI bridge

On 02/08/2017 17:16, Laszlo Ersek wrote: On 08/02/17 15:47, Michael S. Tsirkin wrote: On Wed, Aug 02, 2017 at 12:23:46AM +0200, Laszlo Ersek wrote: On 08/01/17 23:39, Michael S. Tsirkin wrote: On Wed, Aug 02, 2017 at 12:33:12AM +0300, Alexander Bezzubikov wrote: 2017-08-01 23:31 GMT+03:00

Re: [SeaBIOS] [Qemu-devel] >256 Virtio-net-pci hotplug Devices

On 25/07/2017 21:00, Kinsella, Ray wrote: Hi Marcel, Hi Ray, On 24/07/2017 00:14, Marcel Apfelbaum wrote: On 24/07/2017 7:53, Kinsella, Ray wrote: Even if I am not aware of how much time would take to init a bare-metal PCIe Root Port, it seems too much. So I repeated the testing

Re: [SeaBIOS] [Qemu-devel] [PATCH v3 5/5] docs: update documentation considering PCIE-PCI bridge

On 02/08/2017 1:23, Laszlo Ersek wrote: On 08/01/17 23:39, Michael S. Tsirkin wrote: On Wed, Aug 02, 2017 at 12:33:12AM +0300, Alexander Bezzubikov wrote: 2017-08-01 23:31 GMT+03:00 Laszlo Ersek : (Whenever my comments conflict with Michael's or Marcel's, I defer to them.)

Re: [SeaBIOS] [PATCH v3 2/5] hw/pci: introduce pcie-pci-bridge device

On 01/08/2017 18:51, Michael S. Tsirkin wrote: On Tue, Aug 01, 2017 at 06:45:13PM +0300, Marcel Apfelbaum wrote: On 01/08/2017 18:32, Michael S. Tsirkin wrote: On Mon, Jul 31, 2017 at 09:40:41PM +0300, Alexander Bezzubikov wrote: +typedef struct PCIEPCIBridge { +/*< priv

Re: [SeaBIOS] [PATCH v3 2/5] hw/pci: introduce pcie-pci-bridge device

On 01/08/2017 18:32, Michael S. Tsirkin wrote: On Mon, Jul 31, 2017 at 09:40:41PM +0300, Alexander Bezzubikov wrote: +typedef struct PCIEPCIBridge { +/*< private >*/ +PCIBridge parent_obj; + +bool msi_enable; Please rename the msi_enable property to "msi" in order to be aligned

Re: [SeaBIOS] [PATCH v3 2/3] pci: add QEMU-specific PCI capability structure

On 31/07/2017 22:01, Alexander Bezzubikov wrote: 2017-07-31 21:57 GMT+03:00 Michael S. Tsirkin <m...@redhat.com>: On Mon, Jul 31, 2017 at 09:54:55PM +0300, Alexander Bezzubikov wrote: 2017-07-31 17:09 GMT+03:00 Marcel Apfelbaum <mar...@redhat.com>: On 31/07/2017 17:00, Michae

Re: [SeaBIOS] [PATCH v3 2/3] pci: add QEMU-specific PCI capability structure

On 31/07/2017 17:00, Michael S. Tsirkin wrote: On Sat, Jul 29, 2017 at 02:34:31AM +0300, Aleksandr Bezzubikov wrote: On PCI init PCI bridge devices may need some extra info about bus number to reserve, IO, memory and prefetchable memory limits. QEMU can provide this with special vendor-specific

Re: [SeaBIOS] [PATCH v3 5/5] docs: update documentation considering PCIE-PCI bridge

On 29/07/2017 2:37, Aleksandr Bezzubikov wrote: Signed-off-by: Aleksandr Bezzubikov --- docs/pcie.txt| 46 ++ docs/pcie_pci_bridge.txt | 121 +++ 2 files changed, 147 insertions(+), 20 deletions(-)

Re: [SeaBIOS] [PATCH v3 4/5] hw/pci: add QEMU-specific PCI capability to Generic PCI Express Root Port

On 29/07/2017 2:37, Aleksandr Bezzubikov wrote: From: Aleksandr Bezzubikov To enable hotplugging of a newly created pcie-pci-bridge, we need to tell firmware (SeaBIOS in this case) Not only SeaBIOS, also OVMF - so all guest firmware to reserve additional buses for

Re: [SeaBIOS] [PATCH v3 3/5] hw/pci: introduce bridge-only vendor-specific capability to provide some hints to firmware

On 29/07/2017 2:37, Aleksandr Bezzubikov wrote: On PCI init PCI bridges may need some extra info about bus number to reserve, IO, memory and prefetchable memory limits. QEMU can provide this with a special vendor-specific PCI capability. Signed-off-by: Aleksandr Bezzubikov

Re: [SeaBIOS] [PATCH v3 1/5] hw/i386: allow SHPC for Q35 machine

viewed-by: Marcel Apfelbaum <mar...@redhat.com> Thanks, Marcel ___ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios

Re: [SeaBIOS] [PATCH v3 3/3] pci: enable RedHat PCI bridges to reserve additional buses on PCI init

On 29/07/2017 2:34, Aleksandr Bezzubikov wrote: In case of Red Hat Generic PCIE Root Port reserve additional buses, which number is provided in a vendor-specific capability. Signed-off-by: Aleksandr Bezzubikov --- src/fw/pciinit.c | 37

Re: [SeaBIOS] [PATCH v3 2/3] pci: add QEMU-specific PCI capability structure

On 29/07/2017 2:34, Aleksandr Bezzubikov wrote: On PCI init PCI bridge devices may need some extra info about bus number to reserve, IO, memory and prefetchable memory limits. QEMU can provide this with special vendor-specific PCI capability. This capability is intended to be used only for Red

Re: [SeaBIOS] [RFC PATCH v2 4/6] hw/pci: introduce bridge-only vendor-specific capability to provide some hints to firmware

On 29/07/2017 2:12, Michael S. Tsirkin wrote: On Thu, Jul 27, 2017 at 12:39:54PM +0300, Marcel Apfelbaum wrote: On 27/07/2017 2:28, Michael S. Tsirkin wrote: On Thu, Jul 27, 2017 at 12:54:07AM +0300, Alexander Bezzubikov wrote: 2017-07-26 22:43 GMT+03:00 Michael S. Tsirkin <m...@redhat.

Re: [SeaBIOS] [RFC PATCH v2 0/4] Allow RedHat PCI bridges reserve more buses than necessary during init

On 26/07/2017 21:49, Michael S. Tsirkin wrote: On Wed, Jul 26, 2017 at 07:22:42PM +0300, Marcel Apfelbaum wrote: On 26/07/2017 18:20, Laszlo Ersek wrote: On 07/26/17 08:48, Marcel Apfelbaum wrote: On 25/07/2017 18:46, Laszlo Ersek wrote: [snip] (2) Bus range reservation, and hotplugging

Re: [SeaBIOS] [RFC PATCH v2 0/4] Allow RedHat PCI bridges reserve more buses than necessary during init

On 26/07/2017 21:31, Laszlo Ersek wrote: On 07/26/17 18:22, Marcel Apfelbaum wrote: On 26/07/2017 18:20, Laszlo Ersek wrote: [snip] However, what does the hot-pluggability of the PCIe-PCI bridge buy us? In other words, what does it buy us when we do not add the PCIe-PCI bridge immediately

Re: [SeaBIOS] [RFC PATCH v2 4/6] hw/pci: introduce bridge-only vendor-specific capability to provide some hints to firmware

On 27/07/2017 2:28, Michael S. Tsirkin wrote: On Thu, Jul 27, 2017 at 12:54:07AM +0300, Alexander Bezzubikov wrote: 2017-07-26 22:43 GMT+03:00 Michael S. Tsirkin : On Sun, Jul 23, 2017 at 01:15:41AM +0300, Aleksandr Bezzubikov wrote: On PCI init PCI bridges may need some

Re: [SeaBIOS] [RFC PATCH v2 0/4] Allow RedHat PCI bridges reserve more buses than necessary during init

On 26/07/2017 18:20, Laszlo Ersek wrote: On 07/26/17 08:48, Marcel Apfelbaum wrote: On 25/07/2017 18:46, Laszlo Ersek wrote: [snip] (2) Bus range reservation, and hotplugging bridges. What's the motivation? Our recommendations in "docs/pcie.txt" suggest flat hierarchies. It re

Re: [SeaBIOS] [RFC PATCH v2 0/4] Allow RedHat PCI bridges reserve more buses than necessary during init

On 25/07/2017 18:46, Laszlo Ersek wrote: On 07/23/17 00:11, Aleksandr Bezzubikov wrote: Now PCI bridges get a bus range number on a system init, basing on currently plugged devices. That's why when one wants to hotplug another bridge, it needs his child bus, which the parent is unable to

Re: [SeaBIOS] [RFC PATCH v2 5/6] hw/pci: add bus_reserve property to pcie-root-port

On 25/07/2017 20:11, Alexander Bezzubikov wrote: вт, 25 июля 2017 г. в 19:10, Marcel Apfelbaum <mar...@redhat.com <mailto:mar...@redhat.com>>: On 25/07/2017 17:09, Alexander Bezzubikov wrote: > 2017-07-25 16:53 GMT+03:00 Michael S. Tsirkin <m...@redhat

Re: [SeaBIOS] [RFC PATCH v2 5/6] hw/pci: add bus_reserve property to pcie-root-port

3:11PM +0300, Marcel Apfelbaum wrote: On 23/07/2017 15:22, Michael S. Tsirkin wrote: On Sun, Jul 23, 2017 at 01:15:42AM +0300, Aleksandr Bezzubikov wrote: To enable hotplugging of a newly created pcie-pci-bridge, we need to tell firmware (SeaBIOS in this case) Hi Michael, Presumably, EF

Re: [SeaBIOS] [RFC PATCH v2 6/6] hw/pci: add hint capabilty for additional bus reservation to pcie-root-port

On 25/07/2017 0:43, Alexander Bezzubikov wrote: 2017-07-24 23:43 GMT+03:00 Michael S. Tsirkin : On Sun, Jul 23, 2017 at 01:15:43AM +0300, Aleksandr Bezzubikov wrote: Signed-off-by: Aleksandr Bezzubikov --- hw/pci-bridge/pcie_root_port.c | 5 + 1

Re: [SeaBIOS] [RFC PATCH v2 5/6] hw/pci: add bus_reserve property to pcie-root-port

On 25/07/2017 0:58, Michael S. Tsirkin wrote: On Tue, Jul 25, 2017 at 12:41:12AM +0300, Alexander Bezzubikov wrote: 2017-07-24 23:46 GMT+03:00 Michael S. Tsirkin <m...@redhat.com>: On Sun, Jul 23, 2017 at 05:13:11PM +0300, Marcel Apfelbaum wrote: On 23/07/2017 15:22, Michael S. Tsirkin

Re: [SeaBIOS] [RFC PATCH v2 4/4] pci: enable RedHat PCI bridges to reserve additional buses on PCI init

On 24/07/2017 17:39, Alexander Bezzubikov wrote: 2017-07-24 12:42 GMT+03:00 Gerd Hoffmann >: On Sun, 2017-07-23 at 22:44 +0300, Alexander Bezzubikov wrote: > By the way, any ideas on how to avoid 'bus overstealing' would > be greatly

Re: [SeaBIOS] >256 Virtio-net-pci hotplug Devices

Apfelbaum <mar...@redhat.com>; Kinsella, Ray <ray.kinse...@intel.com> Cc: qemu-de...@nongnu.org; seabios@seabios.org; Gerd Hoffmann <kra...@redhat.com>; Michael Tsirkin <m...@redhat.com> Subject: Re: >256 Virtio-net-pci hotplug Devices On Sun, Jul 23, 2017 at 07:28:01PM +0

Re: [SeaBIOS] >256 Virtio-net-pci hotplug Devices

On 22/07/2017 2:57, Kinsella, Ray wrote: Hi Marcel Hi Ray, On 21/07/2017 01:33, Marcel Apfelbaum wrote: On 20/07/2017 3:44, Kinsella, Ray wrote: That's strange. Please ensure the virtio devices are working in virtio 1.0 mode (disable-modern=0,disable-legacy=1). Let us know any problems

Re: [SeaBIOS] [RFC PATCH v2 4/6] hw/pci: introduce bridge-only vendor-specific capability to provide some hints to firmware

On 23/07/2017 19:19, Alexander Bezzubikov wrote: 2017-07-23 18:57 GMT+03:00 Marcel Apfelbaum <mar...@redhat.com <mailto:mar...@redhat.com>>: On 23/07/2017 1:15, Aleksandr Bezzubikov wrote: On PCI init PCI bridges may need some extra info about bus number to

Re: [SeaBIOS] [RFC PATCH v2 2/4] pci: add RedHat vendor ID

On 23/07/2017 1:11, Aleksandr Bezzubikov wrote: Signed-off-by: Aleksandr Bezzubikov --- src/hw/pci_ids.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/hw/pci_ids.h b/src/hw/pci_ids.h index 4ac73b4..db2e694 100644 --- a/src/hw/pci_ids.h +++ b/src/hw/pci_ids.h

Re: [SeaBIOS] [RFC PATCH v2 1/4] pci: refactor pci_find_capapibilty to get bdf as the first argument instead of the whole pci_device

than that: Reviewed-by: Marcel Apfelbaum <mar...@redhat.com> Thanks, Marcel Signed-off-by: Aleksandr Bezzubikov <zuban...@gmail.com> --- src/fw/pciinit.c| 4 ++-- src/hw/pcidevice.c | 12 ++-- src/hw/pcidevice.h | 2 +- src/hw/virtio-pci.c | 4 ++-- 4 files

Re: [SeaBIOS] [RFC PATCH v2 2/6] hw/i386: allow SHPC for Q35 machine

On 23/07/2017 1:15, Aleksandr Bezzubikov wrote: Unmask previously masked SHPC feature in _OSC method. Signed-off-by: Aleksandr Bezzubikov --- hw/i386/acpi-build.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i386/acpi-build.c

Re: [SeaBIOS] [RFC PATCH v2 4/6] hw/pci: introduce bridge-only vendor-specific capability to provide some hints to firmware

On 23/07/2017 1:15, Aleksandr Bezzubikov wrote: On PCI init PCI bridges may need some extra info about bus number to reserve, IO, memory and prefetchable memory limits. QEMU can provide this with special vendor-specific PCI capability. Sizes of limits match ones from PCI Type 1 Configuration

Re: [SeaBIOS] [RFC PATCH v2 5/6] hw/pci: add bus_reserve property to pcie-root-port

On 23/07/2017 15:22, Michael S. Tsirkin wrote: On Sun, Jul 23, 2017 at 01:15:42AM +0300, Aleksandr Bezzubikov wrote: To enable hotplugging of a newly created pcie-pci-bridge, we need to tell firmware (SeaBIOS in this case) Hi Michael, Presumably, EFI would need to support this too?

Re: [SeaBIOS] [RFC PATCH 0/2] Allow RedHat PCI bridges reserve more buses than necessary during init

On 21/07/2017 20:28, Kevin O'Connor wrote: On Fri, Jul 21, 2017 at 03:15:46PM +0300, Marcel Apfelbaum wrote: On 21/07/2017 13:04, Gerd Hoffmann wrote: I'd prefer to have a single vendor capability for all resource allocation hints provided by qemu. Sure, the capability looking something like

Re: [SeaBIOS] [RFC PATCH 0/2] Allow RedHat PCI bridges reserve more buses than necessary during init

On 21/07/2017 15:42, Gerd Hoffmann wrote: On Fri, 2017-07-21 at 15:15 +0300, Marcel Apfelbaum wrote: On 21/07/2017 13:04, Gerd Hoffmann wrote: Hi, What about window sizes? IIRC there was a plan to provide allocation hints for them too ... Yes, is in my TODO list, however not as part

Re: [SeaBIOS] [RFC PATCH 0/2] Allow RedHat PCI bridges reserve more buses than necessary during init

On 21/07/2017 13:04, Gerd Hoffmann wrote: Hi, What about window sizes? IIRC there was a plan to provide allocation hints for them too ... Yes, is in my TODO list, however not as part of Aleksandr's series which aims to provide PCIe-PCI bridge hotplug support. I'd prefer to have a

Re: [SeaBIOS] [Qemu-devel] Fwd: [RFC PATCH 0/2] Allow RedHat PCI bridges reserve more buses than necessary during init

On 19/07/2017 21:56, Konrad Rzeszutek Wilk wrote: On Wed, Jul 19, 2017 at 09:38:50PM +0300, Alexander Bezzubikov wrote: 2017-07-19 21:18 GMT+03:00 Konrad Rzeszutek Wilk : On Wed, Jul 19, 2017 at 05:14:41PM +, Alexander Bezzubikov wrote: ср, 19 июля 2017 г. в

Re: [SeaBIOS] [Qemu-devel] [RFC PATCH 2/2] pci: enable RedHat pci bridges to reserve more buses

On 19/07/2017 16:56, Konrad Rzeszutek Wilk wrote: On Wed, Jul 19, 2017 at 04:20:14PM +0300, Aleksandr Bezzubikov wrote: In case of RedHat PCI bridges reserve additional buses, which number is provided It is "Red Hat" in a vendor-specific capability. And perhaps also a #define ? Right,

Re: [SeaBIOS] [RFC PATCH 1/2] pci: add support for direct usage of bdf for capability lookup

On 19/07/2017 16:20, Aleksandr Bezzubikov wrote: Add a capability lookup function which gets bdf instead of pci_device as its first argument. It may be useful when we have bdf, but don't have the whole pci_device structure. Signed-off-by: Aleksandr Bezzubikov ---

Re: [SeaBIOS] [PATCH] pci: don't map virtio 1.0 storage devices above 4G

On 09/12/2016 06:46 AM, Michael S. Tsirkin wrote: On Sun, Sep 11, 2016 at 08:23:34PM +0300, Marcel Apfelbaum wrote: Otherwise SeaBIOS can't access virtio's modern BAR. Signed-off-by: Marcel Apfelbaum <mar...@redhat.com> --- Hi, If there is no room to map all MMIO BARs into the 32-b

[SeaBIOS] [PATCH] pci: don't map virtio 1.0 storage devices above 4G

Otherwise SeaBIOS can't access virtio's modern BAR. Signed-off-by: Marcel Apfelbaum <mar...@redhat.com> --- Hi, If there is no room to map all MMIO BARs into the 32-bit PCI window, SeaBIOS will re-allocate all 64-bit MMIO BARs into over-4G space. Virtio 1.0 block devices (virtio-blk/

[SeaBIOS] [PATCH V2] fw/pci: add Q35 S3 support

Following the i440fx example, save the LPC, SMBUS and PCIEXBAR bdfs between OS sleeps and use them to re-configure the corresponding registers. Tested-by: Gal Hammer <gham...@redhat.com> Signed-off-by: Marcel Apfelbaum <mar...@redhat.com> --- Hi, v1 -> v2: - made ICH9SmbusBDF

Re: [SeaBIOS] [PATCH] fw/pci: add Q35 S3 support

On 03/01/2016 03:22 PM, Laszlo Ersek wrote: On 02/29/16 21:13, Marcel Apfelbaum wrote: Following the i440fx example, save the LPC, SMBUS and PCIEXBAR bdfs between OS sleeps and use them to re-configure the corresponding registers. Signed-off-by: Marcel Apfelbaum <mar...@redhat.com> -

[SeaBIOS] [PATCH] fw/pci: add Q35 S3 support

Following the i440fx example, save the LPC, SMBUS and PCIEXBAR bdfs between OS sleeps and use them to re-configure the corresponding registers. Signed-off-by: Marcel Apfelbaum <mar...@redhat.com> --- Hi, The patch was tested with Win7 and Fedora 23 guests. Any comments are welcomed.

Re: [SeaBIOS] [PATCH] pci: panic when out of bus numbers

On 01/04/2016 01:43 PM, Marcel Apfelbaum wrote: Currently the bios goes into an endless loop if more than 255 PCI buses are requested. Hi, This is the reproducing script: cli=" -M q35 " while [ ${i:=0} -lt ${1:-0} ] do dstreamId=$((i)) ustreamId=$((dstreamId/32))

[SeaBIOS] [PATCH] pci: panic when out of bus numbers

Currently the bios goes into an endless loop if more than 255 PCI buses are requested. Change that to panic which is preferred in this case. Signed-off-by: Marcel Apfelbaum <mar...@redhat.com> --- Hi, I am well aware that this is not a common scenario, but the bug was found and

Re: [SeaBIOS] [PATCH] pci: panic when out of bus numbers

On 01/04/2016 02:19 PM, Gerd Hoffmann wrote: On Mo, 2016-01-04 at 13:43 +0200, Marcel Apfelbaum wrote: Currently the bios goes into an endless loop if more than 255 PCI buses are requested. Hi Gerd, Thanks for looking into this. Given the bus number register is 8bit I'm wondering whenever

Re: [SeaBIOS] [Qemu-devel] [PATCH 6/6] q35: skip q35-acpi-dsdt.aml load if not needed

(!has_acpi_build) { +/* only machine types 1.7 & older need this */ Actually 1.6 and older, right? (I might be wrong) +pc_acpi_init("q35-acpi-dsdt.aml"); +} kvmclock_create(); It looks OK to me. Reviewed-by: Marcel Apfelbaum <m

Re: [SeaBIOS] [PATCH] fw/pci: do not automatically allocate IO region for PCIe bridges

On 12/07/2015 11:46 AM, Gerd Hoffmann wrote: Hi, However, PCIe devices can work without IO, so there is no need to allocate IO space for hotplug. Makes sense. diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index 7b8aab7..4b37792 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@

[SeaBIOS] [PATCH V2] fw/pci: do not automatically allocate IO region for PCIe bridges

to allocate IO space for hotplug. Signed-off-by: Marcel Apfelbaum <mar...@redhat.com> --- v1 -> v2: - Addressed Gerd's comments: - move pci_find_capability out of the loop and call it only once. - more descriptive names for variables Notes: - This patch fixes a 15 PCIe R

Re: [SeaBIOS] [PATCH v7 10/10] hw/pci-bridge: format special OFW unit address for PXB host

is dynamically taken from the main host bridge, similarly to sysbus_get_fw_dev_path(). Cc: Kevin O'Connor ke...@koconnor.net Cc: Michael S. Tsirkin m...@redhat.com Cc: Marcel Apfelbaum mar...@redhat.com Signed-off-by: Laszlo Ersek ler...@redhat.com --- Notes: v7: - implement the format that both

Re: [SeaBIOS] [Qemu-devel] [PATCH V2] pci: fixes to allow booting from extra root pci buses.

On 06/12/2015 09:00 AM, Gerd Hoffmann wrote: Hi, On each boot, coreboot might decide to assign a different bus id to the extra roots (for example, if a device with a PCI bridge is inserted and it's bus allocation causes bus ids to shift). Technically, coreboot could even change the order

Re: [SeaBIOS] [PATCH V2] pci: fixes to allow booting from extra root pci buses.

On 06/11/2015 05:24 PM, Kevin O'Connor wrote: On Thu, Jun 11, 2015 at 05:12:33PM +0300, Marcel Apfelbaum wrote: On 06/11/2015 04:58 PM, Kevin O'Connor wrote: On Thu, Jun 11, 2015 at 04:37:08PM +0300, Marcel Apfelbaum wrote: The fixes solves the following issue: The PXB device exposes a new

[SeaBIOS] [PATCH] pci: fixes to allow booting from extra root pci buses.

-off-by: Marcel Apfelbaum mar...@redhat.com --- Laszlo worked on supporting pxb for OVMF and discovered that there is a problem when booting devices from a PXB. This is a link to the latest QEMU series: https://www.mail-archive.com/qemu-devel@nongnu.org/msg302493.html Thanks, Marcel src/boot.c

Re: [SeaBIOS] [PATCH] pci: fixes to allow booting from extra root pci buses.

On 06/11/2015 03:45 PM, Michael S. Tsirkin wrote: On Thu, Jun 11, 2015 at 03:41:35PM +0300, Marcel Apfelbaum wrote: The PXB device exposes a new pci root bridge with the fw path: /pci-root@4/..., in which 4 is the root bus number. Before this patch the fw path was wrongly computed: /pci

Re: [SeaBIOS] [Qemu-devel] [PATCH v5 for-2.3 28/28] docs: Add PXB documentation

On 03/10/2015 07:42 PM, Michael S. Tsirkin wrote: On Tue, Mar 10, 2015 at 06:21:14PM +0200, Marcel Apfelbaum wrote: On 03/10/2015 05:47 PM, Michael S. Tsirkin wrote: On Tue, Mar 10, 2015 at 05:32:14PM +0200, Marcel Apfelbaum wrote: Signed-off-by: Marcel Apfelbaum mar...@redhat.com --- docs

Re: [SeaBIOS] [Qemu-devel] [PATCH v5 for-2.3 28/28] docs: Add PXB documentation

On 03/16/2015 05:28 PM, Michael S. Tsirkin wrote: On Mon, Mar 16, 2015 at 02:16:40PM +0200, Marcel Apfelbaum wrote: On 03/10/2015 07:42 PM, Michael S. Tsirkin wrote: On Tue, Mar 10, 2015 at 06:21:14PM +0200, Marcel Apfelbaum wrote: On 03/10/2015 05:47 PM, Michael S. Tsirkin wrote: On Tue

Re: [SeaBIOS] [Qemu-devel] [PATCH v5 for-2.3 02/28] acpi: add aml_or() term

On 03/11/2015 03:17 AM, Shannon Zhao wrote: On 2015/3/10 23:31, Marcel Apfelbaum wrote: Add encoding for ACPI DefOr Opcode. Reviewed-by: Shannon Zhao zhaoshengl...@huawei.com Reviewed-by: Igor Mammedov imamm...@redhat.com Signed-off-by: Marcel Apfelbaum mar...@redhat.com --- hw/acpi/aml

Re: [SeaBIOS] [Qemu-devel] [PATCH v5 for-2.3 00/28] hw/pc: implement multiple primary busses for pc machines

On 03/11/2015 03:32 PM, Gerd Hoffmann wrote: Hi, v4-v5: - Rebased on pci branch, tree: git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git Have again trouble applying this. Which commit hash? Or do you have a git tree somewhere with this? Yes, it is changing too fast :( This version

Re: [SeaBIOS] [Qemu-devel] [PATCH v5 for-2.3 00/28] hw/pc: implement multiple primary busses for pc machines

On 03/11/2015 03:51 PM, Gerd Hoffmann wrote: On Mi, 2015-03-11 at 15:44 +0200, Marcel Apfelbaum wrote: On 03/11/2015 03:32 PM, Gerd Hoffmann wrote: Hi, v4-v5: - Rebased on pci branch, tree: git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git Have again trouble applying this. Which

Re: [SeaBIOS] [Qemu-devel] [PATCH v5 for-2.3 00/28] hw/pc: implement multiple primary busses for pc machines

On 03/11/2015 04:12 PM, Gerd Hoffmann wrote: On Di, 2015-03-10 at 17:31 +0200, Marcel Apfelbaum wrote: v4-v5: - Rebased on pci branch, tree: git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git - Added PXB documentation (patch 28/28) - Addressed Gerd Hoffmann's review: - fix PXB

Re: [SeaBIOS] [Qemu-ppc] [Qemu-devel] [PATCH v4 for-2.3 00/25] hw/pc: implement multiple primary busses for pc machines

On 03/10/2015 08:23 AM, Alexey Kardashevskiy wrote: On 03/10/2015 06:21 AM, Marcel Apfelbaum wrote: On 03/09/2015 06:55 PM, Gerd Hoffmann wrote: On Mo, 2015-03-09 at 18:26 +0200, Marcel Apfelbaum wrote: On 03/09/2015 04:19 PM, Gerd Hoffmann wrote: Hi, My series is based on commit

Re: [SeaBIOS] [Qemu-devel] [PATCH v5 for-2.3 28/28] docs: Add PXB documentation

On 03/10/2015 05:47 PM, Michael S. Tsirkin wrote: On Tue, Mar 10, 2015 at 05:32:14PM +0200, Marcel Apfelbaum wrote: Signed-off-by: Marcel Apfelbaum mar...@redhat.com --- docs/pci_expander_bridge.txt | 52 1 file changed, 52 insertions(+) create

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