Hi all,
Apologies for using the -devel mailing list - I'm aware it should be used for
development, but I simply don't know where else to try.
The first questions I've already posted here:
https://electronics.stackexchange.com/questions/426287/range-for-raw-analog-import-in-pulseview-sigrok
Hi @Soeren, all,
Many, many thanks for the answers - they were immensely helpful for me!
The range of the data type you use (0..255 for u8) is mapped to the
voltage range of -0.5V and +0.5V, as you noticed. That is not done
within PulseView, it's a property of the input module raw_analog.
See
Hi all,
I hope that I'll be able to get a bit of help here - roughly, my question is
this:
* If I establish a setup in PulseView, that uses analog channels, conversion to
logic, and protocol decoding; and save this as an .sr file; - can I then use
sigrok-cli to browse the decoded data in the
igrok\PulseView\pulseview.exe" from cmd.exe
command prompt, simply exits and there are no printouts; however, running it from MSYS2
(or MINGW64) bash, does show the prints from Python protocol decoders in standard output.
Thanks again,
Cheers!
On 4/2/2019 11:43 PM, Soeren Apel wrote:
H
Hi all,
Basically, I made a capture of a serial-type signal with Saleae Logic, digital
mode, 5 MS/s. Exported this to .vcd, imported into Pulseview (PulseView
0.5.0-git-58cd5b5)
Then I use a custom protocol decoder in Python; where I have something like
this:
def decode(self):
if
Hi,
I am trying to find the source code for attenload.
The link to source seems to be broken from
http://sdaaubckp.sourceforge.net/attenload/
I am trying to make an interface from sigrok to my ATTEN ADS2202 DSO.
This is a project unrelated to sigrok-devel, so I doubt you could get much
a
Typically, in a Python protocol decoder plugin for sigrok, we can find where a
signal transition happened, by using self.wait, e.g:
```
# let's say our signal 0 is in "HIGH" level/state now, and self.samplenum is 0
# we want to find transition to low, so we use self.wait:
(mysig,) = self.wait({
Hi all,
Apologies in advance if I'm in the wrong forum for asking this - if so, please
let me know where I can ask this instead.
I have seen https://sigrok.org/wiki/File_format:Csv - and from the example
called:
Mixed signal data in arbitrary order. Timestamps and automatic samplerate.
...
1
Ch7: 0
cli: Received SR_DF_END.
sr: [00:00.031000] hwdriver: Cleaning up all drivers.
```
On Fri, Oct 16, 2020 at 12:46 PM sdbbs wrote:
Hi all,
Apologies in advance if I'm in the wrong forum for asking this - if so,
please let me know where I can ask this instead.
I
realizing I'm in error of understanding: that PulseView cannot really interpret "absolute" timestamps "with
gaps" in .csv at this time).
Anyways - good to have this finally clarified!
On 2020-10-16 2:28 PM, sdbbs wrote:
Many thanks again, Michael,
The above line i
o.vcd files in this gist:
https://gist.github.com/sdbbs/1b7b4e91cae563f1f5de565d05d11515
I also tried opening the .vcd in sigrok-cli with the intent of exporting .sr
from there - log messages indicate that the .vcd file is parsed by sigrok-cli,
however the output .sr file is never created.
Hi Gerhard,
Many thanks for the response!
The previous implementation was flawed in the case of analog-only
data. Total absence of logic data resulted in a division by zero.
This got fixed in libsigrok 2cb4204c6f31. Will be part of the
next nightly build.
Fantastic - that explains it, thank
Hi all,
I was always needing a way to combine/merge PulseView/sigrok sessions - and
finally, I came up with a test case and code that does it. It is documented
here:
https://github.com/sdbbs/sigrok_pulseview_combine_merge
It's kind of a mess, given I made a lot of wrong turns before fi
Hi all,
I was trying to build sigrok/PulseView on MINGW64 on Windows 10, via
https://sigrok.org/gitweb/?p=sigrok-util.git;a=blob;f=cross-compile/msys2/sigrok-native-msys2
... - and I got stuck at this part:
...
checking for libusb_os_handle... no
checking for zip_discard... yes
configure:
PS: Here is a more verbose log with the same error at end, from a couple of
days ago:
https://github.com/sdbbs/sigrok_pulseview_combine_merge/blob/master/msys2_mingw64_sigrok_build_log.md
On 2020-10-28 12:35 PM, sdbbs wrote:
Hi all,
I was trying to build sigrok/PulseView on MINGW64 on
try
to comment that part `if test -z "$NEED_USB_TRUE"; then :`, see if stuff
compiles with it ...
Cheers!
Regards,
-Soeren
On Wed, 2020-10-28 at 12:35 +0100, sdbbs wrote:
Hi all,
I was trying to build sigrok/PulseView on MINGW64 on Windows 10, via
https://sigrok.or
d PulseView (though it is - as expected - not
fully working) - but it is good enough for me for the moment: I see a GUI, I
can open .sr files and run decoders; I've posted notes related to that here:
https://github.com/sdbbs/sigrok_pulseview_combine_merge/blob/master/2020_10_28_pu
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