> On Dec 25, 2015, at 2:21 AM, Bob Supnik wrote:
>
> It's worse than that. The detailed logic is shown on 227-5631-0 pp 188ff. The
> decode chart for each decode switch (DSW) is:
>
> DSW 0
> DSW 10001
> DSW 20010
> DSW 3X011
> DSW 4
>So either no core is selected or multiple cores are selected.
> Now what happens?
The unanswered question here is "What are the conditions for setting MAR
CHECK"?
If an invalid digit in the MAR sets MAR CHECK, then the decoding is
irrelevant.
Bob
P.S. Merry Christmas, guys!
Bob A is right. I found the MAR checking logic on pp 292-3 of 227-5631-0.
For the low four digits of MAR, there are two circuits: a C-bit checker
and an invalid digit checker.
C-bit checker is: (b4 xor b2) xor (b1 xor b8) xor C
invalid digit checker is: (b4 or b2) and b8 - which picks up
> an invalid digit in MAR generates MAR ERROR, lights the MAR
>CHK LAMP, and stops the system.
I thought that might be the case. Thanks for researching it.
BTW, I was wrong about the check stop switch bypassing the MAR CHECK - I
found several references in the manual that make it clear
> On Dec 23, 2015, at 4:30 PM, Bob Supnik wrote:
>
> There's nothing conditional about the user documentation. The 1965 reference
> manual says, "MARS (Memory Address Register Storage) Check Light. This light
> is turned on when a digit in MARS has a parity error or an
It's worse than that. The detailed logic is shown on 227-5631-0 pp
188ff. The decode chart for each decode switch (DSW) is:
DSW 0
DSW 10001
DSW 20010
DSW 3X011
DSW 4X100
DSW 5X101
DSW 6X110
DSW 7X111
DSW 81XX0
DSW 9
>Is the RM and possibly Group Mark valid in a P or Q address and if so, what
>would be the
>value in the address? Could the RM be a 0 and the GM () be a 5 using
>modulo 10.
My guess would be that an RM (or any other invalid digit) does nothing
special when entered into the MARS,