CVS commit: src/sys/arch/amd64/amd64

2018-03-17 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sat Mar 17 17:12:39 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: machdep.c Log Message: Add missing opt_svs.h. To generate a diff of this commit: cvs rdiff -u -r1.301 -r1.302 src/sys/arch/amd64/amd64/machdep.c Please note

CVS commit: src/sys/arch/amd64/amd64

2018-03-17 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sat Mar 17 17:12:39 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: machdep.c Log Message: Add missing opt_svs.h. To generate a diff of this commit: cvs rdiff -u -r1.301 -r1.302 src/sys/arch/amd64/amd64/machdep.c Please note

CVS commit: src/sys/arch/amd64/include

2018-03-16 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Fri Mar 16 12:21:50 UTC 2018 Modified Files: src/sys/arch/amd64/include: cpu.h Log Message: Remove the prototypes for cpu_uarea_*, I removed these functions two minutes ago. To generate a diff of this commit: cvs rdiff -u -r1.61

CVS commit: src/sys/arch/amd64/include

2018-03-16 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Fri Mar 16 12:21:50 UTC 2018 Modified Files: src/sys/arch/amd64/include: cpu.h Log Message: Remove the prototypes for cpu_uarea_*, I removed these functions two minutes ago. To generate a diff of this commit: cvs rdiff -u -r1.61

CVS commit: src/sys/arch/amd64/amd64

2018-03-16 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Fri Mar 16 08:48:34 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: db_machdep.c vector.S Log Message: Rename "handle_" -> "Xhandle_", and add the function names (introduced by SVS) in db_machdep.c. Should fix the DDB part of

CVS commit: src/sys/arch/amd64/amd64

2018-03-16 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Fri Mar 16 08:48:34 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: db_machdep.c vector.S Log Message: Rename "handle_" -> "Xhandle_", and add the function names (introduced by SVS) in db_machdep.c. Should fix the DDB part of

CVS commit: src/sys/arch/amd64/include

2018-03-16 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Fri Mar 16 08:21:56 UTC 2018 Modified Files: src/sys/arch/amd64/include: param.h Log Message: Add one more page for the stack, to compensate for the fact that SVS's stack switching mechanism consumes approximately one page. To

CVS commit: src/sys/arch/amd64/include

2018-03-16 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Fri Mar 16 08:21:56 UTC 2018 Modified Files: src/sys/arch/amd64/include: param.h Log Message: Add one more page for the stack, to compensate for the fact that SVS's stack switching mechanism consumes approximately one page. To

Re: CVS commit: src/sys/arch/amd64/conf

2018-03-15 Thread Joerg Sonnenberger
On Tue, Mar 13, 2018 at 06:02:54PM +0100, Maxime Villard wrote: > Le 11/03/2018 à 22:30, Joerg Sonnenberger a écrit : > > Haswell, using VTx. It seems to hit a triple fault in db_panic according > > to the vbox.log. > > At which stage of the boot procedure does it happen? Does it happen right >

Re: CVS commit: src/sys/arch/amd64/conf

2018-03-13 Thread Maxime Villard
Le 11/03/2018 à 22:30, Joerg Sonnenberger a écrit : On Sat, Mar 10, 2018 at 06:58:39PM +0100, Maxime Villard wrote: Le 09/03/2018 à 20:33, Joerg Sonnenberger a écrit : On Fri, Mar 09, 2018 at 06:36:45PM +0100, Maxime Villard wrote: Le 09/03/2018 à 18:14, Joerg Sonnenberger a écrit : On Mon,

Re: CVS commit: src/sys/arch/amd64/conf

2018-03-11 Thread Joerg Sonnenberger
On Sat, Mar 10, 2018 at 06:58:39PM +0100, Maxime Villard wrote: > Le 09/03/2018 à 20:33, Joerg Sonnenberger a écrit : > > On Fri, Mar 09, 2018 at 06:36:45PM +0100, Maxime Villard wrote: > > > Le 09/03/2018 à 18:14, Joerg Sonnenberger a écrit : > > > > On Mon, Feb 26, 2018 at 05:52:50AM +,

Re: CVS commit: src/sys/arch/amd64/conf

2018-03-11 Thread Martin Husemann
On Sat, Mar 10, 2018 at 06:58:39PM +0100, Maxime Villard wrote: > hardware-assisted or not? I use hardware-assisted, 4.x and 5.x. I guess also the host CPU will matter (at least in virtualbox). Martin

Re: CVS commit: src/sys/arch/amd64/conf

2018-03-10 Thread Maxime Villard
Le 09/03/2018 à 20:33, Joerg Sonnenberger a écrit : On Fri, Mar 09, 2018 at 06:36:45PM +0100, Maxime Villard wrote: Le 09/03/2018 à 18:14, Joerg Sonnenberger a écrit : On Mon, Feb 26, 2018 at 05:52:50AM +, Maxime Villard wrote: Module Name:src Committed By: maxv Date: Mon

Re: CVS commit: src/sys/arch/amd64/conf

2018-03-09 Thread Joerg Sonnenberger
On Fri, Mar 09, 2018 at 06:36:45PM +0100, Maxime Villard wrote: > Le 09/03/2018 à 18:14, Joerg Sonnenberger a écrit : > > On Mon, Feb 26, 2018 at 05:52:50AM +, Maxime Villard wrote: > > > Module Name: src > > > Committed By: maxv > > > Date: Mon Feb 26 05:52:50 UTC 2018 >

Re: CVS commit: src/sys/arch/amd64/conf

2018-03-09 Thread Maxime Villard
Le 09/03/2018 à 18:36, Maxime Villard a écrit : Le 09/03/2018 à 18:14, Joerg Sonnenberger a écrit : On Mon, Feb 26, 2018 at 05:52:50AM +, Maxime Villard wrote: Module Name:src Committed By:maxv Date:Mon Feb 26 05:52:50 UTC 2018 Modified Files: src/sys/arch/amd64/conf:

Re: CVS commit: src/sys/arch/amd64/conf

2018-03-09 Thread Maxime Villard
Le 09/03/2018 à 18:14, Joerg Sonnenberger a écrit : On Mon, Feb 26, 2018 at 05:52:50AM +, Maxime Villard wrote: Module Name:src Committed By: maxv Date: Mon Feb 26 05:52:50 UTC 2018 Modified Files: src/sys/arch/amd64/conf: GENERIC Log Message: Enable SVS by

Re: CVS commit: src/sys/arch/amd64/conf

2018-03-09 Thread Joerg Sonnenberger
On Mon, Feb 26, 2018 at 05:52:50AM +, Maxime Villard wrote: > Module Name: src > Committed By: maxv > Date: Mon Feb 26 05:52:50 UTC 2018 > > Modified Files: > src/sys/arch/amd64/conf: GENERIC > > Log Message: > Enable SVS by default. This broke using VirtualBox and I wouldn't

CVS commit: src/sys/arch/amd64/conf

2018-02-25 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Mon Feb 26 05:52:50 UTC 2018 Modified Files: src/sys/arch/amd64/conf: GENERIC Log Message: Enable SVS by default. To generate a diff of this commit: cvs rdiff -u -r1.484 -r1.485 src/sys/arch/amd64/conf/GENERIC Please note that

CVS commit: src/sys/arch/amd64/conf

2018-02-25 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Mon Feb 26 05:52:50 UTC 2018 Modified Files: src/sys/arch/amd64/conf: GENERIC Log Message: Enable SVS by default. To generate a diff of this commit: cvs rdiff -u -r1.484 -r1.485 src/sys/arch/amd64/conf/GENERIC Please note that

CVS commit: src/sys/arch/amd64/include

2018-02-25 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sun Feb 25 13:14:27 UTC 2018 Modified Files: src/sys/arch/amd64/include: frameasm.h Log Message: Remove INTRENTRY_L, it's not used anymore. To generate a diff of this commit: cvs rdiff -u -r1.36 -r1.37

CVS commit: src/sys/arch/amd64/include

2018-02-25 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sun Feb 25 13:14:27 UTC 2018 Modified Files: src/sys/arch/amd64/include: frameasm.h Log Message: Remove INTRENTRY_L, it's not used anymore. To generate a diff of this commit: cvs rdiff -u -r1.36 -r1.37

CVS commit: src/sys/arch/amd64/amd64

2018-02-25 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sun Feb 25 13:09:34 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: trap.c Log Message: Mmh. We shouldn't read %cr2 here. %cr2 is initialized by the CPU only during page faults (T_PAGEFLT), so here we're reading a value that

CVS commit: src/sys/arch/amd64/amd64

2018-02-25 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sun Feb 25 13:09:34 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: trap.c Log Message: Mmh. We shouldn't read %cr2 here. %cr2 is initialized by the CPU only during page faults (T_PAGEFLT), so here we're reading a value that

CVS commit: src/sys/arch/amd64/amd64

2018-02-25 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sun Feb 25 12:37:16 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: amd64_trap.S locore.S trap.c Log Message: Fix handling of segment register faults when running with SVS. The behavior is changed also in the non-SVS case. I've

CVS commit: src/sys/arch/amd64/amd64

2018-02-25 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sun Feb 25 12:37:16 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: amd64_trap.S locore.S trap.c Log Message: Fix handling of segment register faults when running with SVS. The behavior is changed also in the non-SVS case. I've

CVS commit: src/sys/arch/amd64/amd64

2018-02-25 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sun Feb 25 11:57:44 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: amd64_trap.S Log Message: Ah. Don't use NENTRY() to declare check_swapgs, use LABEL() instead. NENTRY puts the code in the .text section, so the effect of

CVS commit: src/sys/arch/amd64/amd64

2018-02-25 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sun Feb 25 11:57:44 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: amd64_trap.S Log Message: Ah. Don't use NENTRY() to declare check_swapgs, use LABEL() instead. NENTRY puts the code in the .text section, so the effect of

CVS commit: src/sys/arch/amd64/amd64

2018-02-25 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sun Feb 25 08:28:55 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: amd64_trap.S Log Message: Replace %rax -> %rdi, so that check_swapgs clobbers only one register. To generate a diff of this commit: cvs rdiff -u -r1.34 -r1.35

CVS commit: src/sys/arch/amd64/amd64

2018-02-25 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sun Feb 25 08:28:55 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: amd64_trap.S Log Message: Replace %rax -> %rdi, so that check_swapgs clobbers only one register. To generate a diff of this commit: cvs rdiff -u -r1.34 -r1.35

CVS commit: src/sys/arch/amd64/amd64

2018-02-25 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sun Feb 25 08:09:07 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: amd64_trap.S Log Message: There are two places where we reload %gs: * In setusergs. Here we can't fault. So we don't need to handle this case. * In

CVS commit: src/sys/arch/amd64/amd64

2018-02-25 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sun Feb 25 08:09:07 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: amd64_trap.S Log Message: There are two places where we reload %gs: * In setusergs. Here we can't fault. So we don't need to handle this case. * In

Re: CVS commit: src/sys/arch/amd64/amd64

2018-02-24 Thread Maxime Villard
Le 24/02/2018 à 17:30, Christos Zoulas a écrit : In article <18bc2a5a-f82d-91ba-5e52-b262c907b...@m00nbsd.net>, Maxime Villard wrote: Le 24/02/2018 à 11:54, Martin Husemann a écrit : On Sat, Feb 24, 2018 at 11:37:11AM +0100, Maxime Villard wrote: If the macro was defined

CVS commit: src/sys/arch/amd64/amd64

2018-02-24 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sat Feb 24 17:12:10 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: locore.S Log Message: Use %rax instead of %r15 in the non-SVS case, to reduce the diff against SVS. In SVS we use %rax instead of %r15 because the following

CVS commit: src/sys/arch/amd64/amd64

2018-02-24 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sat Feb 24 17:12:10 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: locore.S Log Message: Use %rax instead of %r15 in the non-SVS case, to reduce the diff against SVS. In SVS we use %rax instead of %r15 because the following

Re: CVS commit: src/sys/arch/amd64/amd64

2018-02-24 Thread Christos Zoulas
In article <18bc2a5a-f82d-91ba-5e52-b262c907b...@m00nbsd.net>, Maxime Villard wrote: >Le 24/02/2018 à 11:54, Martin Husemann a écrit : >> On Sat, Feb 24, 2018 at 11:37:11AM +0100, Maxime Villard wrote: >>> If the macro was defined as #if, you would need to do something like:

Re: CVS commit: src/sys/arch/amd64/amd64

2018-02-24 Thread Maxime Villard
Le 24/02/2018 à 11:54, Martin Husemann a écrit : On Sat, Feb 24, 2018 at 11:37:11AM +0100, Maxime Villard wrote: If the macro was defined as #if, you would need to do something like: SYSCALL_ENTRY(syscall) #define SYSCALL_ENTRY_SVS SYSCALL_ENTRY(syscall_svs)

Re: CVS commit: src/sys/arch/amd64/amd64

2018-02-24 Thread Martin Husemann
On Sat, Feb 24, 2018 at 11:37:11AM +0100, Maxime Villard wrote: > If the macro was defined as #if, you would need to do something like: > > SYSCALL_ENTRY(syscall) > #define SYSCALL_ENTRY_SVS > SYSCALL_ENTRY(syscall_svs) > #undef SYSCALL_ENTRY_SVS > > Where SYSCALL_ENTRY

Re: CVS commit: src/sys/arch/amd64/amd64

2018-02-24 Thread Maxime Villard
Le 24/02/2018 à 11:14, Martin Husemann a écrit : On Fri, Feb 23, 2018 at 08:09:09AM +0100, Maxime Villard wrote: ... And? There is only one place where we use .if instead of #if, because there is a good reason for doing so. Which reason is that? Well, look at the code. We want to control

Re: CVS commit: src/sys/arch/amd64/amd64

2018-02-24 Thread Martin Husemann
On Fri, Feb 23, 2018 at 08:09:09AM +0100, Maxime Villard wrote: > ... And? There is only one place where we use .if instead of #if, because > there > is a good reason for doing so. Which reason is that? Martin

Re: CVS commit: src/sys/arch/amd64/amd64

2018-02-24 Thread Maxime Villard
Le 22/02/2018 à 17:31, Christos Zoulas a écrit : In article <7f4de63c-e782-14e6-5554-9b9d23471...@m00nbsd.net>, Maxime Villard wrote: Le 22/02/2018 à 15:54, Christos Zoulas a écrit : In article <20180222140848.70e95f...@cvs.netbsd.org>, Martin Husemann

Re: CVS commit: src/sys/arch/amd64/amd64

2018-02-23 Thread Christos Zoulas
On Feb 23, 8:09am, m...@m00nbsd.net (Maxime Villard) wrote: -- Subject: Re: CVS commit: src/sys/arch/amd64/amd64 | > The question is do we want to keep using both cpp and assembly macros. | | Why wouldn't we? I don't see the problem. Because it adds complexity. | ... And? There is only

Re: CVS commit: src/sys/arch/amd64/amd64

2018-02-22 Thread Christos Zoulas
In article <7f4de63c-e782-14e6-5554-9b9d23471...@m00nbsd.net>, Maxime Villard wrote: >Le 22/02/2018 à 15:54, Christos Zoulas a écrit : >> In article <20180222140848.70e95f...@cvs.netbsd.org>, >> Martin Husemann wrote: >>> -=-=-=-=-=- >>> >>>

Re: CVS commit: src/sys/arch/amd64/amd64

2018-02-22 Thread Maxime Villard
Le 22/02/2018 à 15:54, Christos Zoulas a écrit : In article <20180222140848.70e95f...@cvs.netbsd.org>, Martin Husemann wrote: -=-=-=-=-=- Module Name:src Committed By: martin Date: Thu Feb 22 14:08:48 UTC 2018 Modified Files:

CVS commit: src/sys/arch/amd64/amd64

2018-02-22 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Thu Feb 22 14:57:11 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: locore.S Log Message: Adapt previous; put #ifdef SVS around the declaration directly. To generate a diff of this commit: cvs rdiff -u -r1.154 -r1.155

CVS commit: src/sys/arch/amd64/amd64

2018-02-22 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Thu Feb 22 14:57:11 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: locore.S Log Message: Adapt previous; put #ifdef SVS around the declaration directly. To generate a diff of this commit: cvs rdiff -u -r1.154 -r1.155

Re: CVS commit: src/sys/arch/amd64/amd64

2018-02-22 Thread Christos Zoulas
In article <20180222140848.70e95f...@cvs.netbsd.org>, Martin Husemann wrote: >-=-=-=-=-=- > >Module Name: src >Committed By: martin >Date: Thu Feb 22 14:08:48 UTC 2018 > >Modified Files: > src/sys/arch/amd64/amd64: locore.S > >Log Message: >Protect

CVS commit: src/sys/arch/amd64/amd64

2018-02-22 Thread Martin Husemann
Module Name:src Committed By: martin Date: Thu Feb 22 14:08:48 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: locore.S Log Message: Protect the SVS part of SYSCALL_ENTRY by #ifdef SVS to make non-SVS kernels compile again. To generate a diff of this commit: cvs

CVS commit: src/sys/arch/amd64/amd64

2018-02-22 Thread Martin Husemann
Module Name:src Committed By: martin Date: Thu Feb 22 14:08:48 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: locore.S Log Message: Protect the SVS part of SYSCALL_ENTRY by #ifdef SVS to make non-SVS kernels compile again. To generate a diff of this commit: cvs

CVS commit: src/sys/arch/amd64/amd64

2018-02-22 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Thu Feb 22 10:26:32 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: machdep.c Log Message: Mmh, add #ifdef SVS around svs_init(). To generate a diff of this commit: cvs rdiff -u -r1.299 -r1.300

CVS commit: src/sys/arch/amd64/amd64

2018-02-22 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Thu Feb 22 10:26:32 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: machdep.c Log Message: Mmh, add #ifdef SVS around svs_init(). To generate a diff of this commit: cvs rdiff -u -r1.299 -r1.300

CVS commit: src/sys/arch/amd64/amd64

2018-02-22 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Thu Feb 22 08:36:31 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: amd64_trap.S Log Message: Revert all my latest changes, and restore this file back to how it was in rev1.24. I wanted to replace the functions dynamically for

CVS commit: src/sys/arch/amd64/amd64

2018-02-22 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Thu Feb 22 08:36:31 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: amd64_trap.S Log Message: Revert all my latest changes, and restore this file back to how it was in rev1.24. I wanted to replace the functions dynamically for

CVS commit: src/sys/arch/amd64/amd64

2018-02-18 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sun Feb 18 14:32:31 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: amd64_trap.S Log Message: Pass the name of the function as argument in SWAPGS_HANDLER. To generate a diff of this commit: cvs rdiff -u -r1.31 -r1.32

CVS commit: src/sys/arch/amd64/amd64

2018-02-18 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sun Feb 18 14:32:31 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: amd64_trap.S Log Message: Pass the name of the function as argument in SWAPGS_HANDLER. To generate a diff of this commit: cvs rdiff -u -r1.31 -r1.32

CVS commit: src/sys/arch/amd64/amd64

2018-02-17 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sat Feb 17 21:05:58 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: amd64_trap.S Log Message: Declare check_swapgs in an ASM macro. No real functional change. To generate a diff of this commit: cvs rdiff -u -r1.30 -r1.31

CVS commit: src/sys/arch/amd64/amd64

2018-02-17 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sat Feb 17 21:05:58 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: amd64_trap.S Log Message: Declare check_swapgs in an ASM macro. No real functional change. To generate a diff of this commit: cvs rdiff -u -r1.30 -r1.31

CVS commit: src/sys/arch/amd64/amd64

2018-02-17 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sat Feb 17 20:59:14 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: amd64_trap.S Log Message: Use ASM macros for the rest of the entry points. No real functional change. Now the format of the entry points is: .macro

CVS commit: src/sys/arch/amd64/amd64

2018-02-17 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sat Feb 17 20:47:04 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: amd64_trap.S Log Message: Declare and use TRAP_ENTRY_POINT_DNA. This time we don't give an is_ztrap argument, because the macro is tied to the entry point, and

CVS commit: src/sys/arch/amd64/amd64

2018-02-17 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sat Feb 17 20:41:57 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: amd64_trap.S Log Message: Now that [Z]TRAP and [Z]TRAP_NJ are identical, put back the INTRENTRY jmp .Lalltraps_noentry instructions for

CVS commit: src/sys/arch/amd64/amd64

2018-02-17 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sat Feb 17 20:41:57 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: amd64_trap.S Log Message: Now that [Z]TRAP and [Z]TRAP_NJ are identical, put back the INTRENTRY jmp .Lalltraps_noentry instructions for

CVS commit: src/sys/arch/amd64/amd64

2018-02-17 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sat Feb 17 20:33:28 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: amd64_trap.S Log Message: Declare and use TRAP_ENTRY_POINT_SPUR. No real functional change. To generate a diff of this commit: cvs rdiff -u -r1.26 -r1.27

CVS commit: src/sys/arch/amd64/amd64

2018-02-17 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sat Feb 17 20:33:28 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: amd64_trap.S Log Message: Declare and use TRAP_ENTRY_POINT_SPUR. No real functional change. To generate a diff of this commit: cvs rdiff -u -r1.26 -r1.27

CVS commit: src/sys/arch/amd64/amd64

2018-02-17 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sat Feb 17 20:28:18 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: amd64_trap.S Log Message: Declare and use TRAP_ENTRY_POINT_FPU. No real functional change. To generate a diff of this commit: cvs rdiff -u -r1.25 -r1.26

CVS commit: src/sys/arch/amd64/amd64

2018-02-17 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sat Feb 17 20:28:18 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: amd64_trap.S Log Message: Declare and use TRAP_ENTRY_POINT_FPU. No real functional change. To generate a diff of this commit: cvs rdiff -u -r1.25 -r1.26

CVS commit: src/sys/arch/amd64/amd64

2018-02-17 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sat Feb 17 20:22:05 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: amd64_trap.S Log Message: Start using ASM macros to define the trap entry points. No real functional change. To generate a diff of this commit: cvs rdiff -u

CVS commit: src/sys/arch/amd64/amd64

2018-02-17 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sat Feb 17 20:22:05 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: amd64_trap.S Log Message: Start using ASM macros to define the trap entry points. No real functional change. To generate a diff of this commit: cvs rdiff -u

CVS commit: src/sys/arch/amd64/amd64

2018-02-17 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sat Feb 17 19:26:20 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: vector.S Log Message: Define legacy_stubs in a macro. To generate a diff of this commit: cvs rdiff -u -r1.59 -r1.60 src/sys/arch/amd64/amd64/vector.S Please

CVS commit: src/sys/arch/amd64/amd64

2018-02-17 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sat Feb 17 19:26:20 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: vector.S Log Message: Define legacy_stubs in a macro. To generate a diff of this commit: cvs rdiff -u -r1.59 -r1.60 src/sys/arch/amd64/amd64/vector.S Please

CVS commit: src/sys/arch/amd64/amd64

2018-02-09 Thread Christos Zoulas
Module Name:src Committed By: christos Date: Sat Feb 10 03:55:59 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: db_interface.c Log Message: make it compile without MULTIPROCESSOR (xen?) To generate a diff of this commit: cvs rdiff -u -r1.28 -r1.29

CVS commit: src/sys/arch/amd64/amd64

2018-02-09 Thread Christos Zoulas
Module Name:src Committed By: christos Date: Sat Feb 10 03:55:59 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: db_interface.c Log Message: make it compile without MULTIPROCESSOR (xen?) To generate a diff of this commit: cvs rdiff -u -r1.28 -r1.29

CVS commit: src/sys/arch/amd64/amd64

2018-02-09 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Fri Feb 9 08:54:12 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: amd64_trap.S Log Message: Don't restore segment registers when leaving NMIs. In nmitrap (and the functions it later calls), we are not allowing the trap frame

CVS commit: src/sys/arch/amd64/amd64

2018-02-09 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Fri Feb 9 08:54:12 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: amd64_trap.S Log Message: Don't restore segment registers when leaving NMIs. In nmitrap (and the functions it later calls), we are not allowing the trap frame

CVS commit: src/sys/arch/amd64/amd64

2018-02-09 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Fri Feb 9 08:42:26 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: vector.S Log Message: Define INTRSTUB_ARRAY, simplifies a lot. To generate a diff of this commit: cvs rdiff -u -r1.57 -r1.58 src/sys/arch/amd64/amd64/vector.S

CVS commit: src/sys/arch/amd64/amd64

2018-02-09 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Fri Feb 9 08:42:26 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: vector.S Log Message: Define INTRSTUB_ARRAY, simplifies a lot. To generate a diff of this commit: cvs rdiff -u -r1.57 -r1.58 src/sys/arch/amd64/amd64/vector.S

CVS commit: src/sys/arch/amd64/conf

2018-02-04 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sun Feb 4 17:54:35 UTC 2018 Modified Files: src/sys/arch/amd64/conf: GENERIC_KASLR Log Message: Explicitly disable the kernel-mode GPROF (even though it is never enabled), and explain a bit. To generate a diff of this commit:

CVS commit: src/sys/arch/amd64/conf

2018-02-04 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sun Feb 4 17:54:35 UTC 2018 Modified Files: src/sys/arch/amd64/conf: GENERIC_KASLR Log Message: Explicitly disable the kernel-mode GPROF (even though it is never enabled), and explain a bit. To generate a diff of this commit:

CVS commit: src/sys/arch/amd64/amd64

2018-02-04 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sun Feb 4 17:03:21 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: machdep.c Log Message: Add a TODO list for SVS. To generate a diff of this commit: cvs rdiff -u -r1.296 -r1.297 src/sys/arch/amd64/amd64/machdep.c Please

CVS commit: src/sys/arch/amd64/amd64

2018-02-04 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sun Feb 4 17:03:21 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: machdep.c Log Message: Add a TODO list for SVS. To generate a diff of this commit: cvs rdiff -u -r1.296 -r1.297 src/sys/arch/amd64/amd64/machdep.c Please

CVS commit: src/sys/arch/amd64/conf

2018-01-27 Thread Paul Goyette
Module Name:src Committed By: pgoyette Date: Sat Jan 27 21:46:54 UTC 2018 Modified Files: src/sys/arch/amd64/conf: ALL GENERIC XEN3_DOM0 Log Message: Update amdzentemp(4) attachment info. Also for ALL, remove duplicate entry for amdtemp(4). To generate a diff of this

CVS commit: src/sys/arch/amd64/conf

2018-01-27 Thread Paul Goyette
Module Name:src Committed By: pgoyette Date: Sat Jan 27 21:46:54 UTC 2018 Modified Files: src/sys/arch/amd64/conf: ALL GENERIC XEN3_DOM0 Log Message: Update amdzentemp(4) attachment info. Also for ALL, remove duplicate entry for amdtemp(4). To generate a diff of this

CVS commit: src/sys/arch/amd64/include

2018-01-27 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sat Jan 27 18:27:08 UTC 2018 Modified Files: src/sys/arch/amd64/include: frameasm.h Log Message: Put the default %cs value in INTR_RECURSE_HWFRAME. Pushing an immediate costs less than reading the %cs register and pushing its

CVS commit: src/sys/arch/amd64/include

2018-01-27 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sat Jan 27 18:27:08 UTC 2018 Modified Files: src/sys/arch/amd64/include: frameasm.h Log Message: Put the default %cs value in INTR_RECURSE_HWFRAME. Pushing an immediate costs less than reading the %cs register and pushing its

CVS commit: src/sys/arch/amd64

2018-01-27 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sat Jan 27 18:17:57 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: vector.S src/sys/arch/amd64/include: frameasm.h Log Message: Declare and use INTR_RECURSE_ENTRY, an optimized version of INTRENTRY. When processing

CVS commit: src/sys/arch/amd64

2018-01-27 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sat Jan 27 18:17:57 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: vector.S src/sys/arch/amd64/include: frameasm.h Log Message: Declare and use INTR_RECURSE_ENTRY, an optimized version of INTRENTRY. When processing

CVS commit: src/sys/arch/amd64/amd64

2018-01-27 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sat Jan 27 17:54:13 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: locore.S Log Message: Use testb, faster. To generate a diff of this commit: cvs rdiff -u -r1.149 -r1.150 src/sys/arch/amd64/amd64/locore.S Please note that

CVS commit: src/sys/arch/amd64/amd64

2018-01-27 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sat Jan 27 17:54:13 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: locore.S Log Message: Use testb, faster. To generate a diff of this commit: cvs rdiff -u -r1.149 -r1.150 src/sys/arch/amd64/amd64/locore.S Please note that

CVS commit: src/sys/arch/amd64/conf

2018-01-26 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Fri Jan 26 14:41:22 UTC 2018 Modified Files: src/sys/arch/amd64/conf: GENERIC Log Message: Add etherip, so that we at least know it exists on amd64. To generate a diff of this commit: cvs rdiff -u -r1.482 -r1.483

CVS commit: src/sys/arch/amd64/conf

2018-01-26 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Fri Jan 26 14:41:22 UTC 2018 Modified Files: src/sys/arch/amd64/conf: GENERIC Log Message: Add etherip, so that we at least know it exists on amd64. To generate a diff of this commit: cvs rdiff -u -r1.482 -r1.483

CVS commit: src/sys/arch/amd64/amd64

2018-01-26 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Fri Jan 26 14:38:46 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: machdep.c Log Message: Zero out the scratch value in the UTLS page during context switches. We temporarily put %rax there when processing syscalls, and we

CVS commit: src/sys/arch/amd64/amd64

2018-01-26 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Fri Jan 26 14:38:46 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: machdep.c Log Message: Zero out the scratch value in the UTLS page during context switches. We temporarily put %rax there when processing syscalls, and we

CVS commit: src/sys/arch/amd64/conf

2018-01-24 Thread Christos Zoulas
Module Name:src Committed By: christos Date: Thu Jan 25 01:21:40 UTC 2018 Modified Files: src/sys/arch/amd64/conf: ALL GENERIC XEN3_DOM0 Log Message: add amdzentemp To generate a diff of this commit: cvs rdiff -u -r1.78 -r1.79 src/sys/arch/amd64/conf/ALL cvs rdiff -u

CVS commit: src/sys/arch/amd64/conf

2018-01-24 Thread Christos Zoulas
Module Name:src Committed By: christos Date: Thu Jan 25 01:21:40 UTC 2018 Modified Files: src/sys/arch/amd64/conf: ALL GENERIC XEN3_DOM0 Log Message: add amdzentemp To generate a diff of this commit: cvs rdiff -u -r1.78 -r1.79 src/sys/arch/amd64/conf/ALL cvs rdiff -u

CVS commit: src/sys/arch/amd64/amd64

2018-01-22 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Mon Jan 22 08:14:09 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: locore.S Log Message: Ah, remove duplicate SVS_LEAVE. Fixes 32bit binaries. While here remove duplicate 'cli', but that's harmless. To generate a diff of this

CVS commit: src/sys/arch/amd64/amd64

2018-01-22 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Mon Jan 22 08:14:09 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: locore.S Log Message: Ah, remove duplicate SVS_LEAVE. Fixes 32bit binaries. While here remove duplicate 'cli', but that's harmless. To generate a diff of this

CVS commit: src/sys/arch/amd64/amd64

2018-01-21 Thread Christos Zoulas
Module Name:src Committed By: christos Date: Sun Jan 21 16:51:15 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: db_disasm.c Log Message: CID-1364351: Fix uninitialized warnings. To generate a diff of this commit: cvs rdiff -u -r1.23 -r1.24

CVS commit: src/sys/arch/amd64/amd64

2018-01-21 Thread Christos Zoulas
Module Name:src Committed By: christos Date: Sun Jan 21 16:51:15 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: db_disasm.c Log Message: CID-1364351: Fix uninitialized warnings. To generate a diff of this commit: cvs rdiff -u -r1.23 -r1.24

CVS commit: src/sys/arch/amd64

2018-01-21 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sun Jan 21 11:21:40 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: amd64_trap.S locore.S machdep.c vector.S src/sys/arch/amd64/conf: kern.ldscript kern.ldscript.kaslr src/sys/arch/amd64/include: frameasm.h Log

CVS commit: src/sys/arch/amd64

2018-01-21 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sun Jan 21 11:21:40 UTC 2018 Modified Files: src/sys/arch/amd64/amd64: amd64_trap.S locore.S machdep.c vector.S src/sys/arch/amd64/conf: kern.ldscript kern.ldscript.kaslr src/sys/arch/amd64/include: frameasm.h Log

CVS commit: src/sys/arch/amd64

2018-01-21 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sun Jan 21 10:59:21 UTC 2018 Modified Files: src/sys/arch/amd64/include: pmap.h src/sys/arch/amd64/stand/prekern: pdir.h Log Message: Increase the size of the initial mapping of the kernel. KASLR kernels are bigger than

CVS commit: src/sys/arch/amd64

2018-01-21 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sun Jan 21 10:59:21 UTC 2018 Modified Files: src/sys/arch/amd64/include: pmap.h src/sys/arch/amd64/stand/prekern: pdir.h Log Message: Increase the size of the initial mapping of the kernel. KASLR kernels are bigger than

<    1   2   3   4   5   6   7   8   9   10   >