CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: jmcneill Date: Sun Jun 30 09:36:43 UTC 2024 Modified Files: src/sys/arch/aarch64/include: vmparam.h Log Message: aarch64: Bump VM_PHYSSEG_MAX to match DRAM_BANKS / FDT_MEMORY_RANGES. On aarch64 there is a single free list, so VM_PHYSSEG_MAX needs to be the same as FDT_MEMORY_RANGES (which needs to be the same as DRAM_BANKS). Future cleanup should be done to fold these into a single define. To generate a diff of this commit: cvs rdiff -u -r1.20 -r1.21 src/sys/arch/aarch64/include/vmparam.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: jmcneill Date: Sun Jun 30 09:36:43 UTC 2024 Modified Files: src/sys/arch/aarch64/include: vmparam.h Log Message: aarch64: Bump VM_PHYSSEG_MAX to match DRAM_BANKS / FDT_MEMORY_RANGES. On aarch64 there is a single free list, so VM_PHYSSEG_MAX needs to be the same as FDT_MEMORY_RANGES (which needs to be the same as DRAM_BANKS). Future cleanup should be done to fold these into a single define. To generate a diff of this commit: cvs rdiff -u -r1.20 -r1.21 src/sys/arch/aarch64/include/vmparam.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/vmparam.h diff -u src/sys/arch/aarch64/include/vmparam.h:1.20 src/sys/arch/aarch64/include/vmparam.h:1.21 --- src/sys/arch/aarch64/include/vmparam.h:1.20 Sun Apr 16 14:01:51 2023 +++ src/sys/arch/aarch64/include/vmparam.h Sun Jun 30 09:36:43 2024 @@ -1,4 +1,4 @@ -/* $NetBSD: vmparam.h,v 1.20 2023/04/16 14:01:51 skrll Exp $ */ +/* $NetBSD: vmparam.h,v 1.21 2024/06/30 09:36:43 jmcneill Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -179,7 +179,7 @@ #define AARCH64_KVA_TO_PA(va) ((paddr_t) ((va) & ~AARCH64_DIRECTMAP_MASK)) /* */ -#define VM_PHYSSEG_MAX 64 /* XXX */ +#define VM_PHYSSEG_MAX 256 /* XXX */ #define VM_PHYSSEG_STRAT VM_PSTRAT_BSEARCH #define VM_NFREELIST 1
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: riastradh Date: Sun May 5 15:18:10 UTC 2024 Modified Files: src/sys/arch/aarch64/include: sljit_machdep.h Log Message: aarch64/sljit_machdep.h: Make this work in compat32 context. Should fix clang build of compat32 eabi libsljit: dependall ===> compat/arm/eabi/../../../lib/../external/bsd/sljit/lib In file included from /home/source/ab/HEAD-llvm/src/sys/external/bsd/sljit/dist/sljit_src/sljitLir.c:1678: /home/source/ab/HEAD-llvm/src/sys/external/bsd/sljit/dist/sljit_src/sljitNativeARM_64.c:142:54: error: shift count >= width of type [-Werror,-Wshift-count-overflow] FAIL_IF(push_inst(compiler, MOVK | RD(dst) | (((imm >> 32) & 0x) << 5) | (2 << 21))); ^ ~~ To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/aarch64/include/sljit_machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/sljit_machdep.h diff -u src/sys/arch/aarch64/include/sljit_machdep.h:1.4 src/sys/arch/aarch64/include/sljit_machdep.h:1.5 --- src/sys/arch/aarch64/include/sljit_machdep.h:1.4 Tue Apr 2 22:37:34 2024 +++ src/sys/arch/aarch64/include/sljit_machdep.h Sun May 5 15:18:10 2024 @@ -1,4 +1,4 @@ -/* $NetBSD: sljit_machdep.h,v 1.4 2024/04/02 22:37:34 riastradh Exp $ */ +/* $NetBSD: sljit_machdep.h,v 1.5 2024/05/05 15:18:10 riastradh Exp $ */ /*- * Copyright (c) 2014 Alexander Nasonov. @@ -29,6 +29,12 @@ #ifndef _AARCH64_SLJITARCH_H #define _AARCH64_SLJITARCH_H +#ifndef __aarch64__ /* compat32 */ + +#include + +#else /* __aarch64__ */ + #include #ifdef _KERNEL @@ -56,4 +62,6 @@ (void)__builtin___clear_cache((char *)(from), (char *)(to)) #endif -#endif +#endif /* __aarch64__ (vs compat32) */ + +#endif /* _AARCH64_SLJITARCH_H */
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: riastradh Date: Sun May 5 15:18:10 UTC 2024 Modified Files: src/sys/arch/aarch64/include: sljit_machdep.h Log Message: aarch64/sljit_machdep.h: Make this work in compat32 context. Should fix clang build of compat32 eabi libsljit: dependall ===> compat/arm/eabi/../../../lib/../external/bsd/sljit/lib In file included from /home/source/ab/HEAD-llvm/src/sys/external/bsd/sljit/dist/sljit_src/sljitLir.c:1678: /home/source/ab/HEAD-llvm/src/sys/external/bsd/sljit/dist/sljit_src/sljitNativeARM_64.c:142:54: error: shift count >= width of type [-Werror,-Wshift-count-overflow] FAIL_IF(push_inst(compiler, MOVK | RD(dst) | (((imm >> 32) & 0x) << 5) | (2 << 21))); ^ ~~ To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/aarch64/include/sljit_machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: andvar Date: Wed Jan 3 18:13:19 UTC 2024 Modified Files: src/sys/arch/aarch64/include: armreg.h Log Message: ddress->address in comment. To generate a diff of this commit: cvs rdiff -u -r1.65 -r1.66 src/sys/arch/aarch64/include/armreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: andvar Date: Wed Jan 3 18:13:19 UTC 2024 Modified Files: src/sys/arch/aarch64/include: armreg.h Log Message: ddress->address in comment. To generate a diff of this commit: cvs rdiff -u -r1.65 -r1.66 src/sys/arch/aarch64/include/armreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/armreg.h diff -u src/sys/arch/aarch64/include/armreg.h:1.65 src/sys/arch/aarch64/include/armreg.h:1.66 --- src/sys/arch/aarch64/include/armreg.h:1.65 Sun Sep 24 10:13:44 2023 +++ src/sys/arch/aarch64/include/armreg.h Wed Jan 3 18:13:19 2024 @@ -1,4 +1,4 @@ -/* $NetBSD: armreg.h,v 1.65 2023/09/24 10:13:44 skrll Exp $ */ +/* $NetBSD: armreg.h,v 1.66 2024/01/03 18:13:19 andvar Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -1153,7 +1153,7 @@ AARCH64REG_WRITE_INLINE(tcr_el2) #define TCR_EL2_DS __BIT(32) // 52-bit output address (FEAT_LPA2) //__BIT(31) // Res1 #define TCR_EL2_TCMA __BIT(30) // Unchecked accesses control (FEAT_MTE2) -#define TCR_EL2_TBID __BIT(29) // Top Byte Instruction ddress matching (FEAT_PAuth) +#define TCR_EL2_TBID __BIT(29) // Top Byte Instruction address matching (FEAT_PAuth) #define TCR_EL2_HWU62 __BIT(28) // Hardware use bit 62 (FEAT_HPDS2) #define TCR_EL2_HWU61 __BIT(27) // Hardware use bit 61 (FEAT_HPDS2) #define TCR_EL2_HWU60 __BIT(26) // Hardware use bit 60 (FEAT_HPDS2)
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Sun Sep 24 10:13:44 UTC 2023 Modified Files: src/sys/arch/aarch64/include: armreg.h Log Message: Add a bunch of system registers and their bit / bit field definitions. Taken from ryo's nvmm branch with updates from me. To generate a diff of this commit: cvs rdiff -u -r1.64 -r1.65 src/sys/arch/aarch64/include/armreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/armreg.h diff -u src/sys/arch/aarch64/include/armreg.h:1.64 src/sys/arch/aarch64/include/armreg.h:1.65 --- src/sys/arch/aarch64/include/armreg.h:1.64 Sat May 6 21:53:26 2023 +++ src/sys/arch/aarch64/include/armreg.h Sun Sep 24 10:13:44 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: armreg.h,v 1.64 2023/05/06 21:53:26 andvar Exp $ */ +/* $NetBSD: armreg.h,v 1.65 2023/09/24 10:13:44 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -229,7 +229,13 @@ AARCH64REG_READ_INLINE(clidr_el1) #define CLIDR_TYPE_IDCACHE 3 // Separate inst and data caches #define CLIDR_TYPE_UNIFIEDCACHE 4 // Unified cache +AARCH64REG_READ_INLINE(contextidr_el1) +AARCH64REG_WRITE_INLINE(contextidr_el1) + AARCH64REG_READ_INLINE(currentel) + +#define CURRENTEL_EL __BITS(3,2) // Current exception Level + AARCH64REG_READ_INLINE(id_aa64afr0_el1) AARCH64REG_READ_INLINE(id_aa64afr1_el1) AARCH64REG_READ_INLINE(id_aa64dfr0_el1) @@ -661,6 +667,8 @@ AARCH64REG_WRITE_INLINE(esr_el1) #define ESR_EC_CP14_DT 0x06 // A32: LDC/STC access to CP14 #define ESR_EC_FP_ACCESS 0x07 // AXX: Access to SIMD/FP Registers #define ESR_EC_FPID 0x08 // A32: MCR/MRC access to CP10 !EC=7 +#define ESR_EC_PAUTH 0x09 // A64: Pointer auth trap (FEAT_PAUTH) +#define ESR_EC_LS64 0x0a // AXX: LD64B/ST64B instruction (FEAT_LS64) // XXXNH #define ESR_EC_CP14_RRT 0x0c // A32: MRRC access to CP14 #define ESR_EC_BTE_A64 0x0d // A64: Branch Target Exception (V8.5) #define ESR_EC_ILL_STATE 0x0e // AXX: Illegal Execution State @@ -671,29 +679,54 @@ AARCH64REG_WRITE_INLINE(esr_el1) #define ESR_EC_HVC_A64 0x16 // A64: HVC Instruction Execution #define ESR_EC_SMC_A64 0x17 // A64: SMC Instruction Execution #define ESR_EC_SYS_REG 0x18 // A64: MSR/MRS/SYS instruction (!EC0/1/7) -#define ESR_EC_INSN_ABT_EL0 0x20 // AXX: Instruction Abort (EL0) -#define ESR_EC_INSN_ABT_EL1 0x21 // AXX: Instruction Abort (EL1) +#define ESR_EC_SVE 0x19 // AXX: SVE Instruction Execution (FEAT_SVE) +#define ESR_EC_PAUTH_ERET 0x1a // A64: ERET/ERETAA/ERETAB (FEAT_PAUTH and FEAT_NV) +#define ESR_EC_TME 0x1b // A64: TSTART instruction (FEAT_TME) +#define ESR_EC_FRAC 0x1c // A64: Pointer auth trap (FEAT_FPAC) +#define ESR_EC_SME 0x1d // AXX: Access to SME (FEAT_SME) +#define ESR_EC_RME 0x1e // A64: Granule Protection Check (FEAT_RME) +#define ESR_EC_INSN_ABT_EL_LOW 0x20 // AXX: Instruction Abort from lower level +#define ESR_EC_INSN_ABT_EL_CUR 0x21 // AXX: Instruction Abort from current level #define ESR_EC_PC_ALIGNMENT 0x22 // AXX: Misaligned PC -#define ESR_EC_DATA_ABT_EL0 0x24 // AXX: Data Abort (EL0) -#define ESR_EC_DATA_ABT_EL1 0x25 // AXX: Data Abort (EL1) -#define ESR_EC_SP_ALIGNMENT 0x26 // AXX: Misaligned SP +#define ESR_EC_DATA_ABT_EL_LOW 0x24 // AXX: Data Abort from lower level +#define ESR_EC_DATA_ABT_EL_CUR 0x25 // AXX: Data Abort from current level +#define ESR_EC_SP_ALIGNMENT 0x26 // AXX: Misaligned SP +#define ESR_EC_MOPS 0x27 // A64: Memory Operation Exception (FEAT_MOPS) #define ESR_EC_FP_TRAP_A32 0x28 // A32: FP Exception #define ESR_EC_FP_TRAP_A64 0x2c // A64: FP Exception -#define ESR_EC_SERROR 0x2f // AXX: SError Interrupt -#define ESR_EC_BRKPNT_EL0 0x30 // AXX: Breakpoint Exception (EL0) -#define ESR_EC_BRKPNT_EL1 0x31 // AXX: Breakpoint Exception (EL1) -#define ESR_EC_SW_STEP_EL0 0x32 // AXX: Software Step (EL0) -#define ESR_EC_SW_STEP_EL1 0x33 // AXX: Software Step (EL1) -#define ESR_EC_WTCHPNT_EL0 0x34 // AXX: Watchpoint (EL0) -#define ESR_EC_WTCHPNT_EL1 0x35 // AXX: Watchpoint (EL1) +#define ESR_EC_SERROR 0x2f // AXX: SError Interrupt +#define ESR_EC_BRKPNT_EL_LOW 0x30 // AXX: Breakpoint Exception from lower level +#define ESR_EC_BRKPNT_EL_CUR 0x31 // AXX: Breakpoint Exception from current level +#define ESR_EC_SW_STEP_EL_LOW 0x32 // AXX: Software Step from lower level +#define ESR_EC_SW_STEP_EL_CUR 0x33 // AXX: Software Step from current level +#define ESR_EC_WTCHPNT_EL_LOW 0x34 // AXX: Watchpoint from lower level +#define ESR_EC_WTCHPNT_EL_CUR 0x35 // AXX: Watchpoint from current level #define ESR_EC_BKPT_INSN_A32 0x38 // A32: BKPT Instruction Execution #define ESR_EC_VECTOR_CATCH 0x3a // A32: Vector Catch Exception #define ESR_EC_BKPT_INSN_A64 0x3c // A64: BKPT Instruction Execution +/* alias for EL1 kernel */ +#define ESR_EC_INSN_ABT_EL0 ESR_EC_INSN_ABT_EL_LOW +#define ESR_EC_INSN_A
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Sun Sep 24 10:13:44 UTC 2023 Modified Files: src/sys/arch/aarch64/include: armreg.h Log Message: Add a bunch of system registers and their bit / bit field definitions. Taken from ryo's nvmm branch with updates from me. To generate a diff of this commit: cvs rdiff -u -r1.64 -r1.65 src/sys/arch/aarch64/include/armreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Wed Jul 26 07:00:32 UTC 2023 Modified Files: src/sys/arch/aarch64/include: pmap_machdep.h Log Message: blank line audit To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/sys/arch/aarch64/include/pmap_machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/pmap_machdep.h diff -u src/sys/arch/aarch64/include/pmap_machdep.h:1.7 src/sys/arch/aarch64/include/pmap_machdep.h:1.8 --- src/sys/arch/aarch64/include/pmap_machdep.h:1.7 Wed Jul 26 06:58:34 2023 +++ src/sys/arch/aarch64/include/pmap_machdep.h Wed Jul 26 07:00:31 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: pmap_machdep.h,v 1.7 2023/07/26 06:58:34 skrll Exp $ */ +/* $NetBSD: pmap_machdep.h,v 1.8 2023/07/26 07:00:31 skrll Exp $ */ /*- * Copyright (c) 2022 The NetBSD Foundation, Inc. @@ -388,7 +388,6 @@ pte_pde_set(pd_entry_t *pdep, pd_entry_t } - static inline pt_entry_t pte_memattr(u_int flags) { @@ -439,6 +438,7 @@ pte_make_kenter_pa(paddr_t pa, struct vm return pte; } + static inline pt_entry_t pte_make_enter_efirt(paddr_t pa, vm_prot_t prot, u_int flags) { @@ -464,6 +464,7 @@ pte_make_enter_efirt(paddr_t pa, vm_prot return npte; } + static inline pt_entry_t pte_make_enter(paddr_t pa, const struct vm_page_md *mdpg, vm_prot_t prot, u_int flags, bool is_kernel_pmap_p)
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Wed Jul 26 07:00:32 UTC 2023 Modified Files: src/sys/arch/aarch64/include: pmap_machdep.h Log Message: blank line audit To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/sys/arch/aarch64/include/pmap_machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Wed Jul 26 06:47:38 UTC 2023 Modified Files: src/sys/arch/aarch64/include: pmap_machdep.h Log Message: Reduce #ifdefs To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/aarch64/include/pmap_machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/pmap_machdep.h diff -u src/sys/arch/aarch64/include/pmap_machdep.h:1.5 src/sys/arch/aarch64/include/pmap_machdep.h:1.6 --- src/sys/arch/aarch64/include/pmap_machdep.h:1.5 Wed Jul 26 06:45:41 2023 +++ src/sys/arch/aarch64/include/pmap_machdep.h Wed Jul 26 06:47:38 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: pmap_machdep.h,v 1.5 2023/07/26 06:45:41 skrll Exp $ */ +/* $NetBSD: pmap_machdep.h,v 1.6 2023/07/26 06:47:38 skrll Exp $ */ /*- * Copyright (c) 2022 The NetBSD Foundation, Inc. @@ -204,9 +204,7 @@ pmap_md_nptep(pt_entry_t *ptep) return ptep + 1; } -#endif /* __PMAP_PRIVATE */ -#ifdef __PMAP_PRIVATE static __inline paddr_t pte_to_paddr(pt_entry_t pte) {
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Wed Jul 26 06:47:38 UTC 2023 Modified Files: src/sys/arch/aarch64/include: pmap_machdep.h Log Message: Reduce #ifdefs To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/aarch64/include/pmap_machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Wed Jul 26 06:45:41 UTC 2023 Modified Files: src/sys/arch/aarch64/include: pmap_machdep.h Log Message: Wrap long lines in a comment block. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/aarch64/include/pmap_machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/pmap_machdep.h diff -u src/sys/arch/aarch64/include/pmap_machdep.h:1.4 src/sys/arch/aarch64/include/pmap_machdep.h:1.5 --- src/sys/arch/aarch64/include/pmap_machdep.h:1.4 Wed Jul 26 06:43:53 2023 +++ src/sys/arch/aarch64/include/pmap_machdep.h Wed Jul 26 06:45:41 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: pmap_machdep.h,v 1.4 2023/07/26 06:43:53 skrll Exp $ */ +/* $NetBSD: pmap_machdep.h,v 1.5 2023/07/26 06:45:41 skrll Exp $ */ /*- * Copyright (c) 2022 The NetBSD Foundation, Inc. @@ -321,11 +321,11 @@ pte_set(pt_entry_t *ptep, pt_entry_t pte *ptep = pte; dsb(ishst); /* - * if this mapping is going to be used by userland then the eret *can* act - * as the isb, but might not (apple m1). + * if this mapping is going to be used by userland then the eret *can* + * act as the isb, but might not (apple m1). * - * if this mapping is kernel then the isb is always needed (for some micro- - * architectures) + * if this mapping is kernel then the isb is always needed (for some + * micro-architectures) */ isb();
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Wed Jul 26 06:45:41 UTC 2023 Modified Files: src/sys/arch/aarch64/include: pmap_machdep.h Log Message: Wrap long lines in a comment block. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/aarch64/include/pmap_machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Wed Jul 26 06:43:53 UTC 2023 Modified Files: src/sys/arch/aarch64/include: pmap_machdep.h Log Message: spaces to tabs. To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/aarch64/include/pmap_machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/pmap_machdep.h diff -u src/sys/arch/aarch64/include/pmap_machdep.h:1.3 src/sys/arch/aarch64/include/pmap_machdep.h:1.4 --- src/sys/arch/aarch64/include/pmap_machdep.h:1.3 Thu Apr 20 08:28:03 2023 +++ src/sys/arch/aarch64/include/pmap_machdep.h Wed Jul 26 06:43:53 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: pmap_machdep.h,v 1.3 2023/04/20 08:28:03 skrll Exp $ */ +/* $NetBSD: pmap_machdep.h,v 1.4 2023/07/26 06:43:53 skrll Exp $ */ /*- * Copyright (c) 2022 The NetBSD Foundation, Inc. @@ -64,9 +64,9 @@ #define NSEGPG (1 << SEGLENGTH) -#ifndef __BSD_PTENTRY_T__ +#ifndef __BSD_PTENTRY_T__ #define __BSD_PTENTRY_T__ -#define PRIxPTE PRIx64 +#define PRIxPTE PRIx64 #endif /* __BSD_PTENTRY_T__ */ #define KERNEL_PID 0 @@ -92,12 +92,14 @@ struct pmap_md { #define pm_l0_pa pm_md.pmd_l0_pa -void pmap_md_pdetab_init(struct pmap *); -void pmap_md_pdetab_fini(struct pmap *); +void pmap_md_pdetab_init(struct pmap *); +void pmap_md_pdetab_fini(struct pmap *); -vaddr_t pmap_md_map_poolpage(paddr_t, size_t); -paddr_t pmap_md_unmap_poolpage(vaddr_t, size_t); -struct vm_page *pmap_md_alloc_poolpage(int); +vaddr_t pmap_md_map_poolpage(paddr_t, size_t); +paddr_t pmap_md_unmap_poolpage(vaddr_t, size_t); + +struct vm_page * + pmap_md_alloc_poolpage(int); bool pmap_md_kernel_vaddr_p(vaddr_t); paddr_t pmap_md_kernel_vaddr_to_paddr(vaddr_t); @@ -140,7 +142,7 @@ struct pmap_page { static inline paddr_t pmap_l0pa(struct pmap *pm) { -return pm->pm_l0_pa; + return pm->pm_l0_pa; } #if defined(__PMAP_PRIVATE) @@ -159,7 +161,7 @@ bool pmap_md_ok_to_steal_p(const uvm_phy void pmap_md_xtab_activate(pmap_t, struct lwp *); void pmap_md_xtab_deactivate(pmap_t); -vaddr_t pmap_md_direct_map_paddr(paddr_t); +vaddr_t pmap_md_direct_map_paddr(paddr_t); #ifdef MULTIPROCESSOR @@ -239,7 +241,7 @@ static inline bool pte_wired_p(pt_entry_t pte) { -return (pte & LX_BLKPAG_OS_WIRED) != 0; + return (pte & LX_BLKPAG_OS_WIRED) != 0; } @@ -247,7 +249,7 @@ static inline pt_entry_t pte_wire_entry(pt_entry_t pte) { -return pte | LX_BLKPAG_OS_WIRED; + return pte | LX_BLKPAG_OS_WIRED; } @@ -255,7 +257,7 @@ static inline pt_entry_t pte_unwire_entry(pt_entry_t pte) { -return pte & ~LX_BLKPAG_OS_WIRED; + return pte & ~LX_BLKPAG_OS_WIRED; }
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Wed Jul 26 06:43:53 UTC 2023 Modified Files: src/sys/arch/aarch64/include: pmap_machdep.h Log Message: spaces to tabs. To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/aarch64/include/pmap_machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Sat Oct 29 08:29:28 UTC 2022 Modified Files: src/sys/arch/aarch64/include: pmap.h Log Message: KNF + remove unnecessary brackets To generate a diff of this commit: cvs rdiff -u -r1.55 -r1.56 src/sys/arch/aarch64/include/pmap.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/pmap.h diff -u src/sys/arch/aarch64/include/pmap.h:1.55 src/sys/arch/aarch64/include/pmap.h:1.56 --- src/sys/arch/aarch64/include/pmap.h:1.55 Sun Oct 23 07:13:07 2022 +++ src/sys/arch/aarch64/include/pmap.h Sat Oct 29 08:29:28 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: pmap.h,v 1.55 2022/10/23 07:13:07 skrll Exp $ */ +/* $NetBSD: pmap.h,v 1.56 2022/10/29 08:29:28 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -256,11 +256,11 @@ pmap_kvattr(pt_entry_t *ptep, vm_prot_t case 0: break; case VM_PROT_READ: - pte |= (LX_BLKPAG_AF | LX_BLKPAG_AP_RO); + pte |= LX_BLKPAG_AF | LX_BLKPAG_AP_RO; break; case VM_PROT_WRITE: - case VM_PROT_READ|VM_PROT_WRITE: - pte |= (LX_BLKPAG_AF | LX_BLKPAG_AP_RW); + case VM_PROT_READ | VM_PROT_WRITE: + pte |= LX_BLKPAG_AF | LX_BLKPAG_AP_RW; break; }
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Sat Oct 29 08:29:28 UTC 2022 Modified Files: src/sys/arch/aarch64/include: pmap.h Log Message: KNF + remove unnecessary brackets To generate a diff of this commit: cvs rdiff -u -r1.55 -r1.56 src/sys/arch/aarch64/include/pmap.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Sun Oct 23 07:13:07 UTC 2022 Modified Files: src/sys/arch/aarch64/include: pmap.h Log Message: KNF. To generate a diff of this commit: cvs rdiff -u -r1.54 -r1.55 src/sys/arch/aarch64/include/pmap.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/pmap.h diff -u src/sys/arch/aarch64/include/pmap.h:1.54 src/sys/arch/aarch64/include/pmap.h:1.55 --- src/sys/arch/aarch64/include/pmap.h:1.54 Sun Oct 23 07:11:26 2022 +++ src/sys/arch/aarch64/include/pmap.h Sun Oct 23 07:13:07 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: pmap.h,v 1.54 2022/10/23 07:11:26 skrll Exp $ */ +/* $NetBSD: pmap.h,v 1.55 2022/10/23 07:13:07 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -176,7 +176,7 @@ struct vm_page_md { #define LX_BLKPAG_OS_WRITE LX_BLKPAG_OS_1 #define LX_BLKPAG_OS_WIRED LX_BLKPAG_OS_2 #define LX_BLKPAG_OS_BOOT LX_BLKPAG_OS_3 -#define LX_BLKPAG_OS_RWMASK (LX_BLKPAG_OS_WRITE|LX_BLKPAG_OS_READ) +#define LX_BLKPAG_OS_RWMASK (LX_BLKPAG_OS_WRITE | LX_BLKPAG_OS_READ) #define PMAP_PTE_OS0 "read" #define PMAP_PTE_OS1 "write" @@ -215,7 +215,7 @@ struct vm_page_md { (((pde) & ((user) ? LX_BLKPAG_UXN : LX_BLKPAG_PXN)) == 0) #define l3pte_readable(pde) ((pde) & LX_BLKPAG_AF) #define l3pte_writable(pde) \ -(((pde) & (LX_BLKPAG_AF|LX_BLKPAG_AP)) == (LX_BLKPAG_AF|LX_BLKPAG_AP_RW)) +(((pde) & (LX_BLKPAG_AF | LX_BLKPAG_AP)) == (LX_BLKPAG_AF | LX_BLKPAG_AP_RW)) #define l3pte_index(v) (((vaddr_t)(v) & L3_ADDR_BITS) >> L3_SHIFT) #define l3pte_valid(pde) lxpde_valid(pde) #define l3pte_is_page(pde) (((pde) & LX_TYPE) == L3_TYPE_PAG) @@ -251,16 +251,16 @@ pmap_kvattr(pt_entry_t *ptep, vm_prot_t pt_entry_t pte = *ptep; const pt_entry_t opte = pte; - pte &= ~(LX_BLKPAG_AF|LX_BLKPAG_AP); - switch (prot & (VM_PROT_READ|VM_PROT_WRITE)) { + pte &= ~(LX_BLKPAG_AF | LX_BLKPAG_AP); + switch (prot & (VM_PROT_READ | VM_PROT_WRITE)) { case 0: break; case VM_PROT_READ: - pte |= (LX_BLKPAG_AF|LX_BLKPAG_AP_RO); + pte |= (LX_BLKPAG_AF | LX_BLKPAG_AP_RO); break; case VM_PROT_WRITE: case VM_PROT_READ|VM_PROT_WRITE: - pte |= (LX_BLKPAG_AF|LX_BLKPAG_AP_RW); + pte |= (LX_BLKPAG_AF | LX_BLKPAG_AP_RW); break; } @@ -320,7 +320,7 @@ paddr_t pmap_devmap_vtophys(paddr_t); .pd_va = DEVMAP_ALIGN(va), \ .pd_pa = DEVMAP_ALIGN(pa), \ .pd_size = DEVMAP_SIZE(sz), \ - .pd_prot = VM_PROT_READ|VM_PROT_WRITE, \ + .pd_prot = VM_PROT_READ | VM_PROT_WRITE, \ .pd_flags = PMAP_DEV\ } #define DEVMAP_ENTRY_END { 0 }
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Sun Oct 23 07:13:07 UTC 2022 Modified Files: src/sys/arch/aarch64/include: pmap.h Log Message: KNF. To generate a diff of this commit: cvs rdiff -u -r1.54 -r1.55 src/sys/arch/aarch64/include/pmap.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Sun Oct 23 07:11:27 UTC 2022 Modified Files: src/sys/arch/aarch64/include: pmap.h Log Message: Line continuation alignment whitespace. NFC. To generate a diff of this commit: cvs rdiff -u -r1.53 -r1.54 src/sys/arch/aarch64/include/pmap.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/pmap.h diff -u src/sys/arch/aarch64/include/pmap.h:1.53 src/sys/arch/aarch64/include/pmap.h:1.54 --- src/sys/arch/aarch64/include/pmap.h:1.53 Sat Oct 15 11:07:38 2022 +++ src/sys/arch/aarch64/include/pmap.h Sun Oct 23 07:11:26 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: pmap.h,v 1.53 2022/10/15 11:07:38 jmcneill Exp $ */ +/* $NetBSD: pmap.h,v 1.54 2022/10/23 07:11:26 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -315,13 +315,13 @@ paddr_t pmap_devmap_vtophys(paddr_t); #define DEVMAP_ALIGN(x) L3_TRUNC_BLOCK((x)) #define DEVMAP_SIZE(x) L3_ROUND_BLOCK((x)) -#define DEVMAP_ENTRY(va, pa, sz) \ - { \ - .pd_va = DEVMAP_ALIGN(va), \ - .pd_pa = DEVMAP_ALIGN(pa), \ +#define DEVMAP_ENTRY(va, pa, sz)\ + { \ + .pd_va = DEVMAP_ALIGN(va), \ + .pd_pa = DEVMAP_ALIGN(pa), \ .pd_size = DEVMAP_SIZE(sz), \ - .pd_prot = VM_PROT_READ|VM_PROT_WRITE, \ - .pd_flags = PMAP_DEV \ + .pd_prot = VM_PROT_READ|VM_PROT_WRITE, \ + .pd_flags = PMAP_DEV\ } #define DEVMAP_ENTRY_END { 0 }
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Sun Oct 23 07:11:27 UTC 2022 Modified Files: src/sys/arch/aarch64/include: pmap.h Log Message: Line continuation alignment whitespace. NFC. To generate a diff of this commit: cvs rdiff -u -r1.53 -r1.54 src/sys/arch/aarch64/include/pmap.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
re: CVS commit: src/sys/arch/aarch64/include
"Taylor R Campbell" writes: > Module Name: src > Committed By: riastradh > Date: Sun Jul 24 20:28:32 UTC 2022 > > Modified Files: > src/sys/arch/aarch64/include: lock.h > > Log Message: > aarch64/lock.h: Need for _HARDKERNEL. > > Add include guard while here. > > XXX Why does this aarch64-specific file have #ifdef __aarch64__? there're __aarch32__ / __arm32__ environments that supported on arm64 hosts. (clang better than gcc.) .mrg.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: riastradh Date: Sun Jul 24 20:28:32 UTC 2022 Modified Files: src/sys/arch/aarch64/include: lock.h Log Message: aarch64/lock.h: Need for _HARDKERNEL. Add include guard while here. XXX Why does this aarch64-specific file have #ifdef __aarch64__? To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/aarch64/include/lock.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/lock.h diff -u src/sys/arch/aarch64/include/lock.h:1.4 src/sys/arch/aarch64/include/lock.h:1.5 --- src/sys/arch/aarch64/include/lock.h:1.4 Sun Sep 26 20:15:04 2021 +++ src/sys/arch/aarch64/include/lock.h Sun Jul 24 20:28:32 2022 @@ -1,4 +1,9 @@ -/* $NetBSD: lock.h,v 1.4 2021/09/26 20:15:04 jmcneill Exp $ */ +/* $NetBSD: lock.h,v 1.5 2022/07/24 20:28:32 riastradh Exp $ */ + +#ifndef _AARCH64_LOCK_H_ +#define _AARCH64_LOCK_H_ + +#include #ifdef __aarch64__ # ifdef _HARDKERNEL @@ -11,3 +16,5 @@ #elif defined(__arm__) # include #endif + +#endif /* _AARCH64_LOCK_H_ */
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: riastradh Date: Sun Jul 24 20:28:32 UTC 2022 Modified Files: src/sys/arch/aarch64/include: lock.h Log Message: aarch64/lock.h: Need for _HARDKERNEL. Add include guard while here. XXX Why does this aarch64-specific file have #ifdef __aarch64__? To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/aarch64/include/lock.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: riastradh Date: Wed Jul 20 01:35:26 UTC 2022 Modified Files: src/sys/arch/aarch64/include: cpufunc.h Log Message: aarch64: Make cpufunc.h includable without sys/cpu.h first. To generate a diff of this commit: cvs rdiff -u -r1.23 -r1.24 src/sys/arch/aarch64/include/cpufunc.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/cpufunc.h diff -u src/sys/arch/aarch64/include/cpufunc.h:1.23 src/sys/arch/aarch64/include/cpufunc.h:1.24 --- src/sys/arch/aarch64/include/cpufunc.h:1.23 Mon Jan 31 09:16:09 2022 +++ src/sys/arch/aarch64/include/cpufunc.h Wed Jul 20 01:35:25 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: cpufunc.h,v 1.23 2022/01/31 09:16:09 ryo Exp $ */ +/* $NetBSD: cpufunc.h,v 1.24 2022/07/20 01:35:25 riastradh Exp $ */ /* * Copyright (c) 2017 Ryo Shimizu @@ -34,6 +34,7 @@ #include #include +#include extern u_int aarch64_cache_vindexsize; /* cachesize/way (VIVT/VIPT) */ extern u_int aarch64_cache_prefer_mask;
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: riastradh Date: Wed Jul 20 01:35:26 UTC 2022 Modified Files: src/sys/arch/aarch64/include: cpufunc.h Log Message: aarch64: Make cpufunc.h includable without sys/cpu.h first. To generate a diff of this commit: cvs rdiff -u -r1.23 -r1.24 src/sys/arch/aarch64/include/cpufunc.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: jkoshy Date: Mon May 30 21:18:37 UTC 2022 Modified Files: src/sys/arch/aarch64/include: elf_machdep.h Log Message: Use the ABI value for 'R_AARCH64_TLSLD_LDST128_DTPREL_LO12_NC'. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/aarch64/include/elf_machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: jkoshy Date: Mon May 30 21:18:37 UTC 2022 Modified Files: src/sys/arch/aarch64/include: elf_machdep.h Log Message: Use the ABI value for 'R_AARCH64_TLSLD_LDST128_DTPREL_LO12_NC'. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/aarch64/include/elf_machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/elf_machdep.h diff -u src/sys/arch/aarch64/include/elf_machdep.h:1.4 src/sys/arch/aarch64/include/elf_machdep.h:1.5 --- src/sys/arch/aarch64/include/elf_machdep.h:1.4 Fri Oct 12 01:28:58 2018 +++ src/sys/arch/aarch64/include/elf_machdep.h Mon May 30 21:18:37 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: elf_machdep.h,v 1.4 2018/10/12 01:28:58 ryo Exp $ */ +/* $NetBSD: elf_machdep.h,v 1.5 2022/05/30 21:18:37 jkoshy Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -198,7 +198,7 @@ #define R_AARCH64_TLSLE_LDST128_TPREL_LO12 570 /* TPREL(S+A) */ #define R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC 571 /* TPREL(S+A) */ #define R_AARCH64_TLSLD_LDST128_DTPREL_LO12 572 /* DTPREL(S+A) */ -#define R_AARCH64_TLSLD_LDST128_DTPREL_LO12_NC 572 /* DTPREL(S+A) */ +#define R_AARCH64_TLSLD_LDST128_DTPREL_LO12_NC 573 /* DTPREL(S+A) */ /* Dynamic Relocations */ #define R_AARCH64_P32_COPY 180
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: thorpej Date: Fri Nov 5 15:18:18 UTC 2021 Modified Files: src/sys/arch/aarch64/include: signal.h Log Message: Normally, to support COMPAT_NETBSD32 we need to define __HAVE_STRUCT_SIGCONTEXT in order to support the old "sigcontext" style of handlers for 32-bit binaries. However, we only support 32-bit EABI binaries on AArch64, and by happy accident (due to a libc bug introduced in 2006), 32-bit NetBSD EABI binaries never used "sigcontext" style handlers. So, we don't need to carry any of this baggage forward. This addresses the AArch64 case of PR kern/56487. To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/aarch64/include/signal.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/signal.h diff -u src/sys/arch/aarch64/include/signal.h:1.3 src/sys/arch/aarch64/include/signal.h:1.4 --- src/sys/arch/aarch64/include/signal.h:1.3 Wed Oct 27 04:45:42 2021 +++ src/sys/arch/aarch64/include/signal.h Fri Nov 5 15:18:18 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: signal.h,v 1.3 2021/10/27 04:45:42 thorpej Exp $ */ +/* $NetBSD: signal.h,v 1.4 2021/11/05 15:18:18 thorpej Exp $ */ #ifndef _AARCH64_SIGNAL_H_ #define _AARCH64_SIGNAL_H_ @@ -6,8 +6,16 @@ #include #ifdef _KERNEL -/* This is needed to support COMPAT_NETBSD32. */ -#define __HAVE_STRUCT_SIGCONTEXT +/* + * Normally, to support COMPAT_NETBSD32 we need to define + * __HAVE_STRUCT_SIGCONTEXT in order to support the old + * "sigcontext" style of handlers for 32-bit binaries. + * However, we only support 32-bit EABI binaries on AArch64, + * and by happy accident (due to a libc bug introduced in + * 2006), 32-bit NetBSD EABI binaries never used "sigcontext" + * style handlers. So, we don't need to carry any of this + * baggage forward. + */ #endif /* _KERNEL */ #endif /* ! _AARCH64_SIGNAL_H_ */
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: thorpej Date: Fri Nov 5 15:18:18 UTC 2021 Modified Files: src/sys/arch/aarch64/include: signal.h Log Message: Normally, to support COMPAT_NETBSD32 we need to define __HAVE_STRUCT_SIGCONTEXT in order to support the old "sigcontext" style of handlers for 32-bit binaries. However, we only support 32-bit EABI binaries on AArch64, and by happy accident (due to a libc bug introduced in 2006), 32-bit NetBSD EABI binaries never used "sigcontext" style handlers. So, we don't need to carry any of this baggage forward. This addresses the AArch64 case of PR kern/56487. To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/aarch64/include/signal.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Mon Nov 1 08:53:40 UTC 2021 Modified Files: src/sys/arch/aarch64/include: cpu.h Log Message: Fix a last minute rebase/merge botch so that the cpu_hatch commit actually works. To generate a diff of this commit: cvs rdiff -u -r1.43 -r1.44 src/sys/arch/aarch64/include/cpu.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/cpu.h diff -u src/sys/arch/aarch64/include/cpu.h:1.43 src/sys/arch/aarch64/include/cpu.h:1.44 --- src/sys/arch/aarch64/include/cpu.h:1.43 Sun Oct 31 16:23:47 2021 +++ src/sys/arch/aarch64/include/cpu.h Mon Nov 1 08:53:40 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: cpu.h,v 1.43 2021/10/31 16:23:47 skrll Exp $ */ +/* $NetBSD: cpu.h,v 1.44 2021/11/01 08:53:40 skrll Exp $ */ /*- * Copyright (c) 2014, 2020 The NetBSD Foundation, Inc. @@ -168,7 +168,7 @@ struct cpu_info { struct aarch64_sysctl_cpu_id ci_id; /* cache information and function pointers */ - struct aarch64_cache_info *ci_cacheinfo; + struct aarch64_cache_info ci_cacheinfo[MAX_CACHE_LEVEL]; struct aarch64_cpufuncs ci_cpufuncs; #if defined(GPROF) && defined(MULTIPROCESSOR)
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Mon Nov 1 08:53:40 UTC 2021 Modified Files: src/sys/arch/aarch64/include: cpu.h Log Message: Fix a last minute rebase/merge botch so that the cpu_hatch commit actually works. To generate a diff of this commit: cvs rdiff -u -r1.43 -r1.44 src/sys/arch/aarch64/include/cpu.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Sun Oct 31 22:06:32 UTC 2021 Modified Files: src/sys/arch/aarch64/include: db_machdep.h Log Message: Fix crash(8) build To generate a diff of this commit: cvs rdiff -u -r1.15 -r1.16 src/sys/arch/aarch64/include/db_machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/db_machdep.h diff -u src/sys/arch/aarch64/include/db_machdep.h:1.15 src/sys/arch/aarch64/include/db_machdep.h:1.16 --- src/sys/arch/aarch64/include/db_machdep.h:1.15 Sun Oct 31 16:23:47 2021 +++ src/sys/arch/aarch64/include/db_machdep.h Sun Oct 31 22:06:32 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: db_machdep.h,v 1.15 2021/10/31 16:23:47 skrll Exp $ */ +/* $NetBSD: db_machdep.h,v 1.16 2021/10/31 22:06:32 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -221,12 +221,6 @@ db_addr_t db_branch_taken(db_expr_t, db_ void db_pteinfo(vaddr_t, void (*)(const char *, ...) __printflike(1, 2)); void db_pte_print(pt_entry_t, int, void (*)(const char *, ...) __printflike(1, 2)); void db_ttbrdump(bool, vaddr_t, void (*pr)(const char *, ...) __printflike(1, 2)); -#endif - -void dump_trapframe(struct trapframe *, void (*)(const char *, ...) __printflike(1, 2)); - -void dump_switchframe(struct trapframe *, void (*)(const char *, ...) __printflike(1, 2)); -const char *strdisasm(vaddr_t, uint64_t); void db_machdep_cpu_init(void); void db_machdep_init(struct cpu_info * const); @@ -237,6 +231,12 @@ void aarch64_watchpoint_set(int, vaddr_t #define WATCHPOINT_ACCESS_STORE 0x02 #define WATCHPOINT_ACCESS_LOADSTORE 0x03 #define WATCHPOINT_ACCESS_MASK 0x03 +#endif + +void dump_trapframe(struct trapframe *, void (*)(const char *, ...) __printflike(1, 2)); + +void dump_switchframe(struct trapframe *, void (*)(const char *, ...) __printflike(1, 2)); +const char *strdisasm(vaddr_t, uint64_t); #define DB_ELF_SYMBOLS
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Sun Oct 31 22:06:32 UTC 2021 Modified Files: src/sys/arch/aarch64/include: db_machdep.h Log Message: Fix crash(8) build To generate a diff of this commit: cvs rdiff -u -r1.15 -r1.16 src/sys/arch/aarch64/include/db_machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Sun Oct 31 08:21:25 UTC 2021 Modified Files: src/sys/arch/aarch64/include: cpu.h Log Message: Annotate some cpu_info members To generate a diff of this commit: cvs rdiff -u -r1.41 -r1.42 src/sys/arch/aarch64/include/cpu.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/cpu.h diff -u src/sys/arch/aarch64/include/cpu.h:1.41 src/sys/arch/aarch64/include/cpu.h:1.42 --- src/sys/arch/aarch64/include/cpu.h:1.41 Tue Oct 26 06:02:00 2021 +++ src/sys/arch/aarch64/include/cpu.h Sun Oct 31 08:21:24 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: cpu.h,v 1.41 2021/10/26 06:02:00 skrll Exp $ */ +/* $NetBSD: cpu.h,v 1.42 2021/10/31 08:21:24 skrll Exp $ */ /*- * Copyright (c) 2014, 2020 The NetBSD Foundation, Inc. @@ -134,8 +134,10 @@ struct cpu_info { /* ACPI */ uint32_t ci_acpiid; /* ACPI Processor Unique ID */ + /* sysctl(9) exposed system registers */ struct aarch64_sysctl_cpu_id ci_id; + /* cache information and function pointers */ struct aarch64_cache_info *ci_cacheinfo; struct aarch64_cpufuncs ci_cpufuncs;
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Sun Oct 31 08:21:25 UTC 2021 Modified Files: src/sys/arch/aarch64/include: cpu.h Log Message: Annotate some cpu_info members To generate a diff of this commit: cvs rdiff -u -r1.41 -r1.42 src/sys/arch/aarch64/include/cpu.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: ryo Date: Tue Oct 26 16:58:46 UTC 2021 Modified Files: src/sys/arch/aarch64/include: armreg.h Log Message: fix build with COPTS=-O0 To generate a diff of this commit: cvs rdiff -u -r1.58 -r1.59 src/sys/arch/aarch64/include/armreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/armreg.h diff -u src/sys/arch/aarch64/include/armreg.h:1.58 src/sys/arch/aarch64/include/armreg.h:1.59 --- src/sys/arch/aarch64/include/armreg.h:1.58 Sat Oct 23 05:31:53 2021 +++ src/sys/arch/aarch64/include/armreg.h Tue Oct 26 16:58:46 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: armreg.h,v 1.58 2021/10/23 05:31:53 skrll Exp $ */ +/* $NetBSD: armreg.h,v 1.59 2021/10/26 16:58:46 ryo Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -74,8 +74,8 @@ reg_##regname##_write(uint64_t __val) AARCH64REG_WRITE_INLINE3(regname, regdesc, ) #define AARCH64REG_WRITEIMM_INLINE2(regname, regdesc) \ -static __inline void \ -reg_##regname##_write(uint64_t __val)\ +static __inline void __always_inline\ +reg_##regname##_write(const uint64_t __val) \ {\ __asm __volatile( \ "msr " #regdesc ", %0" :: "n"(__val) : "memory" \
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: ryo Date: Tue Oct 26 16:58:46 UTC 2021 Modified Files: src/sys/arch/aarch64/include: armreg.h Log Message: fix build with COPTS=-O0 To generate a diff of this commit: cvs rdiff -u -r1.58 -r1.59 src/sys/arch/aarch64/include/armreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Tue Oct 26 06:02:00 UTC 2021 Modified Files: src/sys/arch/aarch64/include: cpu.h Log Message: Add a comment and adjust whitespace to match style in this file To generate a diff of this commit: cvs rdiff -u -r1.40 -r1.41 src/sys/arch/aarch64/include/cpu.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/cpu.h diff -u src/sys/arch/aarch64/include/cpu.h:1.40 src/sys/arch/aarch64/include/cpu.h:1.41 --- src/sys/arch/aarch64/include/cpu.h:1.40 Sun Oct 10 07:15:25 2021 +++ src/sys/arch/aarch64/include/cpu.h Tue Oct 26 06:02:00 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: cpu.h,v 1.40 2021/10/10 07:15:25 skrll Exp $ */ +/* $NetBSD: cpu.h,v 1.41 2021/10/26 06:02:00 skrll Exp $ */ /*- * Copyright (c) 2014, 2020 The NetBSD Foundation, Inc. @@ -113,7 +113,8 @@ struct cpu_info { int ci_kfpu_spl; - tlb_asid_t ci_pmap_asid_cur; + /* ASID of current pmap */ + tlb_asid_t ci_pmap_asid_cur; /* event counters */ struct evcnt ci_vfp_use;
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Tue Oct 26 06:02:00 UTC 2021 Modified Files: src/sys/arch/aarch64/include: cpu.h Log Message: Add a comment and adjust whitespace to match style in this file To generate a diff of this commit: cvs rdiff -u -r1.40 -r1.41 src/sys/arch/aarch64/include/cpu.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Sat Oct 23 05:32:40 UTC 2021 Modified Files: src/sys/arch/aarch64/include: cpufunc.h Log Message: Whitespace To generate a diff of this commit: cvs rdiff -u -r1.20 -r1.21 src/sys/arch/aarch64/include/cpufunc.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/cpufunc.h diff -u src/sys/arch/aarch64/include/cpufunc.h:1.20 src/sys/arch/aarch64/include/cpufunc.h:1.21 --- src/sys/arch/aarch64/include/cpufunc.h:1.20 Thu May 27 06:11:20 2021 +++ src/sys/arch/aarch64/include/cpufunc.h Sat Oct 23 05:32:40 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: cpufunc.h,v 1.20 2021/05/27 06:11:20 ryo Exp $ */ +/* $NetBSD: cpufunc.h,v 1.21 2021/10/23 05:32:40 skrll Exp $ */ /* * Copyright (c) 2017 Ryo Shimizu @@ -108,7 +108,6 @@ void aarch64_tlbi_by_asid_va_ll(int, vad #define cpu_idnum() aarch64_cpuid() /* cache op */ - #define cpu_dcache_wbinv_all() aarch64_dcache_wbinv_all() #define cpu_dcache_inv_all() aarch64_dcache_inv_all() #define cpu_dcache_wb_all() aarch64_dcache_wb_all()
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Sat Oct 23 05:32:40 UTC 2021 Modified Files: src/sys/arch/aarch64/include: cpufunc.h Log Message: Whitespace To generate a diff of this commit: cvs rdiff -u -r1.20 -r1.21 src/sys/arch/aarch64/include/cpufunc.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Sat Oct 23 05:31:53 UTC 2021 Modified Files: src/sys/arch/aarch64/include: armreg.h Log Message: Typo in comment To generate a diff of this commit: cvs rdiff -u -r1.57 -r1.58 src/sys/arch/aarch64/include/armreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/armreg.h diff -u src/sys/arch/aarch64/include/armreg.h:1.57 src/sys/arch/aarch64/include/armreg.h:1.58 --- src/sys/arch/aarch64/include/armreg.h:1.57 Sat Jun 19 13:40:00 2021 +++ src/sys/arch/aarch64/include/armreg.h Sat Oct 23 05:31:53 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: armreg.h,v 1.57 2021/06/19 13:40:00 jmcneill Exp $ */ +/* $NetBSD: armreg.h,v 1.58 2021/10/23 05:31:53 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -1636,7 +1636,7 @@ struct aarch64_sysctl_cpu_id { uint32_t ac_mvfr2; /* Media and VFP Feature Register 2 */ uint32_t ac_pad; - uint64_t ac_clidr; /* Cacle Level ID Register */ + uint64_t ac_clidr; /* Cache Level ID Register */ uint64_t ac_ctr; /* Cache Type Register */ };
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Sat Oct 23 05:31:53 UTC 2021 Modified Files: src/sys/arch/aarch64/include: armreg.h Log Message: Typo in comment To generate a diff of this commit: cvs rdiff -u -r1.57 -r1.58 src/sys/arch/aarch64/include/armreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Thu Sep 30 18:33:28 UTC 2021 Modified Files: src/sys/arch/aarch64/include: types.h Log Message: Make tlb_asid_t unsigned int as pmap_tlb.c expects tlb_asid_t to be able to hold ASID_MAX + 1. To generate a diff of this commit: cvs rdiff -u -r1.18 -r1.19 src/sys/arch/aarch64/include/types.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Thu Sep 30 18:33:28 UTC 2021 Modified Files: src/sys/arch/aarch64/include: types.h Log Message: Make tlb_asid_t unsigned int as pmap_tlb.c expects tlb_asid_t to be able to hold ASID_MAX + 1. To generate a diff of this commit: cvs rdiff -u -r1.18 -r1.19 src/sys/arch/aarch64/include/types.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/types.h diff -u src/sys/arch/aarch64/include/types.h:1.18 src/sys/arch/aarch64/include/types.h:1.19 --- src/sys/arch/aarch64/include/types.h:1.18 Wed Mar 24 05:00:24 2021 +++ src/sys/arch/aarch64/include/types.h Thu Sep 30 18:33:28 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: types.h,v 1.18 2021/03/24 05:00:24 simonb Exp $ */ +/* $NetBSD: types.h,v 1.19 2021/09/30 18:33:28 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -59,7 +59,7 @@ typedef __uint32_t register32_t; #define PRIxREGISTER PRIx64 #define PRIxREGISTER32 PRIx32 -typedef unsigned short tlb_asid_t; +typedef unsigned int tlb_asid_t; #if defined(_KERNEL) #define LBL_X19 0
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: jmcneill Date: Sun Sep 26 20:15:04 UTC 2021 Modified Files: src/sys/arch/aarch64/include: lock.h Log Message: Use the yield instruction as SPINLOCK_BACKOFF_HOOK for aarch64. To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/aarch64/include/lock.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/lock.h diff -u src/sys/arch/aarch64/include/lock.h:1.3 src/sys/arch/aarch64/include/lock.h:1.4 --- src/sys/arch/aarch64/include/lock.h:1.3 Fri Jun 26 18:27:52 2015 +++ src/sys/arch/aarch64/include/lock.h Sun Sep 26 20:15:04 2021 @@ -1,6 +1,12 @@ -/* $NetBSD: lock.h,v 1.3 2015/06/26 18:27:52 matt Exp $ */ +/* $NetBSD: lock.h,v 1.4 2021/09/26 20:15:04 jmcneill Exp $ */ #ifdef __aarch64__ +# ifdef _HARDKERNEL +# ifdef SPINLOCK_BACKOFF_HOOK +# undef SPINLOCK_BACKOFF_HOOK +# endif +# define SPINLOCK_BACKOFF_HOOK asm volatile("yield" ::: "memory") +# endif # include #elif defined(__arm__) # include
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: jmcneill Date: Sun Sep 26 20:15:04 UTC 2021 Modified Files: src/sys/arch/aarch64/include: lock.h Log Message: Use the yield instruction as SPINLOCK_BACKOFF_HOOK for aarch64. To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/aarch64/include/lock.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: jmcneill Date: Mon Aug 30 22:32:06 UTC 2021 Modified Files: src/sys/arch/aarch64/include: hypervisor.h Log Message: Add definition for HCR_E2H bit To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/aarch64/include/hypervisor.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/hypervisor.h diff -u src/sys/arch/aarch64/include/hypervisor.h:1.2 src/sys/arch/aarch64/include/hypervisor.h:1.3 --- src/sys/arch/aarch64/include/hypervisor.h:1.2 Sat Aug 29 07:17:23 2020 +++ src/sys/arch/aarch64/include/hypervisor.h Mon Aug 30 22:32:06 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: hypervisor.h,v 1.2 2020/08/29 07:17:23 maxv Exp $ */ +/* $NetBSD: hypervisor.h,v 1.3 2021/08/30 22:32:06 jmcneill Exp $ */ /*- * Copyright (c) 2013, 2014 Andrew Turner * All rights reserved. @@ -81,6 +81,7 @@ #define HCR_RW 0x8000 #define HCR_CD 0x0001 #define HCR_ID 0x0002 +#define HCR_E2H 0x0004 #define HCR_ATA 0x0100 /*
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: jmcneill Date: Mon Aug 30 22:32:06 UTC 2021 Modified Files: src/sys/arch/aarch64/include: hypervisor.h Log Message: Add definition for HCR_E2H bit To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/aarch64/include/hypervisor.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: rin Date: Sun Nov 24 11:28:40 UTC 2019 Modified Files: src/sys/arch/aarch64/include: proc.h Log Message: part of PR port-arm/54702 Having md_march32 unconditionally in struct mdproc, in order to make libkvm happy. XXX pullup to netbsd-9 To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/aarch64/include/proc.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: rin Date: Sun Nov 24 11:28:40 UTC 2019 Modified Files: src/sys/arch/aarch64/include: proc.h Log Message: part of PR port-arm/54702 Having md_march32 unconditionally in struct mdproc, in order to make libkvm happy. XXX pullup to netbsd-9 To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/aarch64/include/proc.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/proc.h diff -u src/sys/arch/aarch64/include/proc.h:1.4 src/sys/arch/aarch64/include/proc.h:1.5 --- src/sys/arch/aarch64/include/proc.h:1.4 Sun Nov 24 04:08:36 2019 +++ src/sys/arch/aarch64/include/proc.h Sun Nov 24 11:28:40 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: proc.h,v 1.4 2019/11/24 04:08:36 rin Exp $ */ +/* $NetBSD: proc.h,v 1.5 2019/11/24 11:28:40 rin Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -47,9 +47,7 @@ struct mdlwp { struct mdproc { void (*md_syscall)(struct trapframe *); -#ifdef COMPAT_NETBSD32 char md_march32[12]; /* machine arch of executable */ -#endif }; #ifdef COMPAT_NETBSD32
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Wed Sep 11 18:23:31 UTC 2019 Modified Files: src/sys/arch/aarch64/include: pte.h Log Message: Define PRIxPTE To generate a diff of this commit: cvs rdiff -u -r1.9 -r1.10 src/sys/arch/aarch64/include/pte.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/pte.h diff -u src/sys/arch/aarch64/include/pte.h:1.9 src/sys/arch/aarch64/include/pte.h:1.10 --- src/sys/arch/aarch64/include/pte.h:1.9 Wed Sep 11 18:19:35 2019 +++ src/sys/arch/aarch64/include/pte.h Wed Sep 11 18:23:31 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: pte.h,v 1.9 2019/09/11 18:19:35 skrll Exp $ */ +/* $NetBSD: pte.h,v 1.10 2019/09/11 18:23:31 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -36,7 +36,13 @@ #ifndef _LOCORE typedef uint64_t pd_entry_t; /* L0(512G) / L1(1G) / L2(2M) table entry */ + +#ifndef __BSD_PTENTRY_T__ +#define __BSD_PTENTRY_T__ typedef uint64_t pt_entry_t; /* L3(4k) table entry */ +#define PRIxPTE PRIx64 +#endif /* __BSD_PTENTRY_T__ */ + #endif /* _LOCORE */ /*
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Wed Sep 11 18:23:31 UTC 2019 Modified Files: src/sys/arch/aarch64/include: pte.h Log Message: Define PRIxPTE To generate a diff of this commit: cvs rdiff -u -r1.9 -r1.10 src/sys/arch/aarch64/include/pte.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Wed Sep 11 18:19:35 UTC 2019 Modified Files: src/sys/arch/aarch64/include: armreg.h pte.h Log Message: Move the TCR and TTBR defines into armreg.h where they below. NFCI. To generate a diff of this commit: cvs rdiff -u -r1.26 -r1.27 src/sys/arch/aarch64/include/armreg.h cvs rdiff -u -r1.8 -r1.9 src/sys/arch/aarch64/include/pte.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/armreg.h diff -u src/sys/arch/aarch64/include/armreg.h:1.26 src/sys/arch/aarch64/include/armreg.h:1.27 --- src/sys/arch/aarch64/include/armreg.h:1.26 Mon Aug 12 23:31:48 2019 +++ src/sys/arch/aarch64/include/armreg.h Wed Sep 11 18:19:35 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: armreg.h,v 1.26 2019/08/12 23:31:48 jmcneill Exp $ */ +/* $NetBSD: armreg.h,v 1.27 2019/09/11 18:19:35 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -646,7 +646,60 @@ AARCH64REG_WRITE_INLINE(spsr_el1) AARCH64REG_READ_INLINE(tcr_el1) // Translation Control Register AARCH64REG_WRITE_INLINE(tcr_el1) -#define TCR_PAGE_SIZE1(tcr) (1L << ((1L << __SHIFTOUT(tcr, TCR_TG1)) + 8)) + +/* TCR_EL1 - Translation Control Register */ +#define TCR_TBI1 __BIT(38) /* ignore Top Byte TTBR1_EL1 */ +#define TCR_TBI0 __BIT(37) /* ignore Top Byte TTBR0_EL1 */ +#define TCR_AS64K __BIT(36) /* Use 64K ASIDs */ +#define TCR_IPS __BITS(34,32) /* Intermediate PhysAdr Size */ +#define TCR_IPS_4PB __SHIFTIN(6,TCR_IPS) /* 52 bits ( 4 PB) */ +#define TCR_IPS_256TB __SHIFTIN(5,TCR_IPS) /* 48 bits (256 TB) */ +#define TCR_IPS_16TB __SHIFTIN(4,TCR_IPS) /* 44 bits (16 TB) */ +#define TCR_IPS_4TB __SHIFTIN(3,TCR_IPS) /* 42 bits ( 4 TB) */ +#define TCR_IPS_1TB __SHIFTIN(2,TCR_IPS) /* 40 bits ( 1 TB) */ +#define TCR_IPS_64GB __SHIFTIN(1,TCR_IPS) /* 36 bits (64 GB) */ +#define TCR_IPS_4GB __SHIFTIN(0,TCR_IPS) /* 32 bits (4 GB) */ +#define TCR_TG1 __BITS(31,30) /* TTBR1 Page Granule Size */ +#define TCR_TG1_16KB __SHIFTIN(1,TCR_TG1) /* 16KB page size */ +#define TCR_TG1_4KB __SHIFTIN(2,TCR_TG1) /* 4KB page size */ +#define TCR_TG1_64KB __SHIFTIN(3,TCR_TG1) /* 64KB page size */ +#define TCR_SH1 __BITS(29,28) +#define TCR_SH1_NONE __SHIFTIN(0,TCR_SH1) +#define TCR_SH1_OUTER __SHIFTIN(2,TCR_SH1) +#define TCR_SH1_INNER __SHIFTIN(3,TCR_SH1) +#define TCR_ORGN1 __BITS(27,26) /* TTBR1 Outer cacheability */ +#define TCR_ORGN1_NC __SHIFTIN(0,TCR_ORGN1) /* Non Cacheable */ +#define TCR_ORGN1_WB_WA __SHIFTIN(1,TCR_ORGN1) /* WriteBack WriteAllocate */ +#define TCR_ORGN1_WT __SHIFTIN(2,TCR_ORGN1) /* WriteThrough */ +#define TCR_ORGN1_WB __SHIFTIN(3,TCR_ORGN1) /* WriteBack */ +#define TCR_IRGN1 __BITS(25,24) /* TTBR1 Inner cacheability */ +#define TCR_IRGN1_NC __SHIFTIN(0,TCR_IRGN1) /* Non Cacheable */ +#define TCR_IRGN1_WB_WA __SHIFTIN(1,TCR_IRGN1) /* WriteBack WriteAllocate */ +#define TCR_IRGN1_WT __SHIFTIN(2,TCR_IRGN1) /* WriteThrough */ +#define TCR_IRGN1_WB __SHIFTIN(3,TCR_IRGN1) /* WriteBack */ +#define TCR_EPD1 __BIT(23) /* Walk Disable for TTBR1_EL1 */ +#define TCR_A1 __BIT(22) /* ASID is in TTBR1_EL1 */ +#define TCR_T1SZ __BITS(21,16) /* Size offset for TTBR1_EL1 */ +#define TCR_TG0 __BITS(15,14) /* TTBR0 Page Granule Size */ +#define TCR_TG0_4KB __SHIFTIN(0,TCR_TG0) /* 4KB page size */ +#define TCR_TG0_64KB __SHIFTIN(1,TCR_TG0) /* 64KB page size */ +#define TCR_TG0_16KB __SHIFTIN(2,TCR_TG0) /* 16KB page size */ +#define TCR_SH0 __BITS(13,12) +#define TCR_SH0_NONE __SHIFTIN(0,TCR_SH0) +#define TCR_SH0_OUTER __SHIFTIN(2,TCR_SH0) +#define TCR_SH0_INNER __SHIFTIN(3,TCR_SH0) +#define TCR_ORGN0 __BITS(11,10) /* TTBR0 Outer cacheability */ +#define TCR_ORGN0_NC __SHIFTIN(0,TCR_ORGN0) /* Non Cacheable */ +#define TCR_ORGN0_WB_WA __SHIFTIN(1,TCR_ORGN0) /* WriteBack WriteAllocate */ +#define TCR_ORGN0_WT __SHIFTIN(2,TCR_ORGN0) /* WriteThrough */ +#define TCR_ORGN0_WB __SHIFTIN(3,TCR_ORGN0) /* WriteBack */ +#define TCR_IRGN0 __BITS(9,8) /* TTBR0 Inner cacheability */ +#define TCR_IRGN0_NC __SHIFTIN(0,TCR_IRGN0) /* Non Cacheable */ +#define TCR_IRGN0_WB_WA __SHIFTIN(1,TCR_IRGN0) /* WriteBack WriteAllocate */ +#define TCR_IRGN0_WT __SHIFTIN(2,TCR_IRGN0) /* WriteThrough */ +#define TCR_IRGN0_WB __SHIFTIN(3,TCR_IRGN0) /* WriteBack */ +#define TCR_EPD0 __BIT(7) /* Walk Disable for TTBR0 */ +#define TCR_T0SZ __BITS(5,0) /* Size offset for TTBR0_EL1 */ AARCH64REG_READ_INLINE(tpidr_el1) // Thread ID Register (EL1) AARCH64REG_WRITE_INLINE(tpidr_el1) @@ -659,6 +712,9 @@ AARCH64REG_WRITE_INLINE(ttbr0_el1) AARCH64REG_READ_INLINE(ttbr1_el1) // Translation Table Base Register 1 EL1 AARCH64REG_WRITE_INLINE(ttbr1_el1) +#define TTBR_ASID __BITS(63,48) +#define TTBR_BADDR __BITS(47,0) + AARCH64REG_READ_INLINE(vbar_el1) // Vector Base Address Register AARCH64REG_WRITE_INLINE(vbar_el1) Index: src/sys/a
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Wed Sep 11 18:19:35 UTC 2019 Modified Files: src/sys/arch/aarch64/include: armreg.h pte.h Log Message: Move the TCR and TTBR defines into armreg.h where they below. NFCI. To generate a diff of this commit: cvs rdiff -u -r1.26 -r1.27 src/sys/arch/aarch64/include/armreg.h cvs rdiff -u -r1.8 -r1.9 src/sys/arch/aarch64/include/pte.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: jmcneill Date: Wed Sep 11 11:43:15 UTC 2019 Modified Files: src/sys/arch/aarch64/include: pte.h Log Message: - Fix TCR_TG0 field definitions to match Armv8 ARM - Rename TCR_IPS_64TB to TCR_IPS_16TB, add TCR_IPS_4PB - Whitespace fixes To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/sys/arch/aarch64/include/pte.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: jmcneill Date: Wed Sep 11 11:43:15 UTC 2019 Modified Files: src/sys/arch/aarch64/include: pte.h Log Message: - Fix TCR_TG0 field definitions to match Armv8 ARM - Rename TCR_IPS_64TB to TCR_IPS_16TB, add TCR_IPS_4PB - Whitespace fixes To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/sys/arch/aarch64/include/pte.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/pte.h diff -u src/sys/arch/aarch64/include/pte.h:1.7 src/sys/arch/aarch64/include/pte.h:1.8 --- src/sys/arch/aarch64/include/pte.h:1.7 Thu Aug 15 09:07:34 2019 +++ src/sys/arch/aarch64/include/pte.h Wed Sep 11 11:43:15 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: pte.h,v 1.7 2019/08/15 09:07:34 skrll Exp $ */ +/* $NetBSD: pte.h,v 1.8 2019/09/11 11:43:15 jmcneill Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -134,8 +134,9 @@ typedef uint64_t pt_entry_t; /* L3(4k) t #define TCR_TBI0 __BIT(37) /* ignore Top Byte TTBR0_EL1 */ #define TCR_AS64K __BIT(36) /* Use 64K ASIDs */ #define TCR_IPS __BITS(34,32) /* Intermediate PhysAdr Size */ +#define TCR_IPS_4PB __SHIFTIN(6,TCR_IPS) /* 52 bits ( 4 PB) */ #define TCR_IPS_256TB __SHIFTIN(5,TCR_IPS) /* 48 bits (256 TB) */ -#define TCR_IPS_64TB __SHIFTIN(4,TCR_IPS) /* 44 bits (16 TB) */ +#define TCR_IPS_16TB __SHIFTIN(4,TCR_IPS) /* 44 bits (16 TB) */ #define TCR_IPS_4TB __SHIFTIN(3,TCR_IPS) /* 42 bits ( 4 TB) */ #define TCR_IPS_1TB __SHIFTIN(2,TCR_IPS) /* 40 bits ( 1 TB) */ #define TCR_IPS_64GB __SHIFTIN(1,TCR_IPS) /* 36 bits (64 GB) */ @@ -162,9 +163,9 @@ typedef uint64_t pt_entry_t; /* L3(4k) t #define TCR_A1 __BIT(22) /* ASID is in TTBR1_EL1 */ #define TCR_T1SZ __BITS(21,16) /* Size offset for TTBR1_EL1 */ #define TCR_TG0 __BITS(15,14) /* TTBR0 Page Granule Size */ -#define TCR_TG0_16KB __SHIFTIN(1,TCR_TG1) /* 16KB page size */ -#define TCR_TG0_4KB __SHIFTIN(2,TCR_TG1) /* 4KB page size */ -#define TCR_TG0_64KB __SHIFTIN(3,TCR_TG1) /* 64KB page size */ +#define TCR_TG0_4KB __SHIFTIN(0,TCR_TG0) /* 4KB page size */ +#define TCR_TG0_64KB __SHIFTIN(1,TCR_TG0) /* 64KB page size */ +#define TCR_TG0_16KB __SHIFTIN(2,TCR_TG0) /* 16KB page size */ #define TCR_SH0 __BITS(13,12) #define TCR_SH0_NONE __SHIFTIN(0,TCR_SH0) #define TCR_SH0_OUTER __SHIFTIN(2,TCR_SH0) @@ -176,7 +177,7 @@ typedef uint64_t pt_entry_t; /* L3(4k) t #define TCR_ORGN0_WB __SHIFTIN(3,TCR_ORGN0) /* WriteBack */ #define TCR_IRGN0 __BITS(9,8) /* TTBR0 Inner cacheability */ #define TCR_IRGN0_NC __SHIFTIN(0,TCR_IRGN0) /* Non Cacheable */ -#define TCR_IRGN0_WB_WA __SHIFTIN(1,TCR_IRGN0) /* WriteBack WriteAllocate */ +#define TCR_IRGN0_WB_WA __SHIFTIN(1,TCR_IRGN0) /* WriteBack WriteAllocate */ #define TCR_IRGN0_WT __SHIFTIN(2,TCR_IRGN0) /* WriteThrough */ #define TCR_IRGN0_WB __SHIFTIN(3,TCR_IRGN0) /* WriteBack */ #define TCR_EPD0 __BIT(7) /* Walk Disable for TTBR0 */
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: ryo Date: Sat Sep 7 11:10:24 UTC 2019 Modified Files: src/sys/arch/aarch64/include: cpufunc.h Log Message: add checking status of MMU and devmap to make _platform_early_putchar() available at all times. To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/aarch64/include/cpufunc.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: ryo Date: Sat Sep 7 11:10:24 UTC 2019 Modified Files: src/sys/arch/aarch64/include: cpufunc.h Log Message: add checking status of MMU and devmap to make _platform_early_putchar() available at all times. To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/aarch64/include/cpufunc.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/cpufunc.h diff -u src/sys/arch/aarch64/include/cpufunc.h:1.5 src/sys/arch/aarch64/include/cpufunc.h:1.6 --- src/sys/arch/aarch64/include/cpufunc.h:1.5 Fri Dec 21 08:01:01 2018 +++ src/sys/arch/aarch64/include/cpufunc.h Sat Sep 7 11:10:24 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: cpufunc.h,v 1.5 2018/12/21 08:01:01 ryo Exp $ */ +/* $NetBSD: cpufunc.h,v 1.6 2019/09/07 11:10:24 ryo Exp $ */ /* * Copyright (c) 2017 Ryo Shimizu @@ -148,8 +148,17 @@ cpu_clusterid(void) static inline bool cpu_earlydevice_va_p(void) { + extern vaddr_t virtual_devmap_addr; /* in pmap.c */ - return false; + /* This function may be called before enabling MMU, or mapping KVA */ + if ((reg_sctlr_el1_read() & SCTLR_M) == 0) + return false; + + /* device mapping will be availabled after pmap_devmap_bootstrap() */ + if (virtual_devmap_addr == 0) + return false; + + return true; } #endif /* _KERNEL */
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Thu Aug 15 09:07:34 UTC 2019 Modified Files: src/sys/arch/aarch64/include: pte.h Log Message: Indent the field value defines. NFCI. To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/aarch64/include/pte.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/pte.h diff -u src/sys/arch/aarch64/include/pte.h:1.6 src/sys/arch/aarch64/include/pte.h:1.7 --- src/sys/arch/aarch64/include/pte.h:1.6 Tue Aug 13 08:27:42 2019 +++ src/sys/arch/aarch64/include/pte.h Thu Aug 15 09:07:34 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: pte.h,v 1.6 2019/08/13 08:27:42 skrll Exp $ */ +/* $NetBSD: pte.h,v 1.7 2019/08/15 09:07:34 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -44,17 +44,17 @@ typedef uint64_t pt_entry_t; /* L3(4k) t */ #define LX_TBL_NSTABLE __BIT(63) /* inherited next level */ #define LX_TBL_APTABLE __BITS(62,61) /* inherited next level */ -#define LX_TBL_APTABLE_NOEFFECT __SHIFTIN(0,LX_TBL_APTABLE) -#define LX_TBL_APTABLE_EL0_NOACCESS __SHIFTIN(1,LX_TBL_APTABLE) -#define LX_TBL_APTABLE_RO __SHIFTIN(2,LX_TBL_APTABLE) -#define LX_TBL_APTABLE_RO_EL0_NOREAD __SHIFTIN(3,LX_TBL_APTABLE) +#define LX_TBL_APTABLE_NOEFFECT __SHIFTIN(0,LX_TBL_APTABLE) +#define LX_TBL_APTABLE_EL0_NOACCESS __SHIFTIN(1,LX_TBL_APTABLE) +#define LX_TBL_APTABLE_RO __SHIFTIN(2,LX_TBL_APTABLE) +#define LX_TBL_APTABLE_RO_EL0_NOREAD __SHIFTIN(3,LX_TBL_APTABLE) #define LX_TBL_UXNTABLE __BIT(60) /* inherited next level */ #define LX_TBL_PXNTABLE __BIT(59) /* inherited next level */ #define LX_BLKPAG_OS __BITS(58, 55) -# define LX_BLKPAG_OS_0 __SHIFTIN(1,LX_BLKPAG_OS) -# define LX_BLKPAG_OS_1 __SHIFTIN(2,LX_BLKPAG_OS) -# define LX_BLKPAG_OS_2 __SHIFTIN(4,LX_BLKPAG_OS) -# define LX_BLKPAG_OS_3 __SHIFTIN(8,LX_BLKPAG_OS) +#define LX_BLKPAG_OS_0 __SHIFTIN(1,LX_BLKPAG_OS) +#define LX_BLKPAG_OS_1 __SHIFTIN(2,LX_BLKPAG_OS) +#define LX_BLKPAG_OS_2 __SHIFTIN(4,LX_BLKPAG_OS) +#define LX_BLKPAG_OS_3 __SHIFTIN(8,LX_BLKPAG_OS) #define LX_BLKPAG_UXN __BIT(54) /* Unprivileged Execute Never */ #define LX_BLKPAG_PXN __BIT(53) /* Privileged Execute Never */ #define LX_BLKPAG_CONTIG __BIT(52) /* Hint of TLB cache */ @@ -64,12 +64,12 @@ typedef uint64_t pt_entry_t; /* L3(4k) t #define LX_BLKPAG_NG __BIT(11) /* Not Global */ #define LX_BLKPAG_AF __BIT(10) /* Access Flag */ #define LX_BLKPAG_SH __BITS(9,8) /* Shareability */ -#define LX_BLKPAG_SH_NS __SHIFTIN(0,LX_BLKPAG_SH) /* Non Shareable */ -#define LX_BLKPAG_SH_OS __SHIFTIN(2,LX_BLKPAG_SH) /* Outer Shareable */ -#define LX_BLKPAG_SH_IS __SHIFTIN(3,LX_BLKPAG_SH) /* Inner Shareable */ +#define LX_BLKPAG_SH_NS __SHIFTIN(0,LX_BLKPAG_SH) /* Non Shareable */ +#define LX_BLKPAG_SH_OS __SHIFTIN(2,LX_BLKPAG_SH) /* Outer Shareable */ +#define LX_BLKPAG_SH_IS __SHIFTIN(3,LX_BLKPAG_SH) /* Inner Shareable */ #define LX_BLKPAG_AP __BIT(7) -#define LX_BLKPAG_AP_RW __SHIFTIN(0,LX_BLKPAG_AP) /* RW */ -#define LX_BLKPAG_AP_RO __SHIFTIN(1,LX_BLKPAG_AP) /* RO */ +#define LX_BLKPAG_AP_RW __SHIFTIN(0,LX_BLKPAG_AP) /* RW */ +#define LX_BLKPAG_AP_RO __SHIFTIN(1,LX_BLKPAG_AP) /* RO */ #define LX_BLKPAG_APUSER __BIT(6) #define LX_BLKPAG_NS __BIT(5) #define LX_BLKPAG_ATTR_INDX __BITS(4,2) /* refer MAIR_EL1 attr */ @@ -78,9 +78,9 @@ typedef uint64_t pt_entry_t; /* L3(4k) t #define LX_BLKPAG_ATTR_INDX_2 __SHIFTIN(2,LX_BLKPAG_ATTR_INDX) #define LX_BLKPAG_ATTR_INDX_3 __SHIFTIN(3,LX_BLKPAG_ATTR_INDX) #define LX_TYPE __BIT(1) -#define LX_TYPE_BLK __SHIFTIN(0, LX_TYPE) -#define LX_TYPE_TBL __SHIFTIN(1, LX_TYPE) -#define L3_TYPE_PAG __SHIFTIN(1, LX_TYPE) +#define LX_TYPE_BLK __SHIFTIN(0, LX_TYPE) +#define LX_TYPE_TBL __SHIFTIN(1, LX_TYPE) +#define L3_TYPE_PAG __SHIFTIN(1, LX_TYPE) #define LX_VALID __BIT(0) #define L1_BLK_OA __BITS(47, 30) /* 1GB */ @@ -130,57 +130,57 @@ typedef uint64_t pt_entry_t; /* L3(4k) t /* TCR_EL1 - Translation Control Register */ -#define TCR_TBI1 __BIT(38) /* ignore Top Byte TTBR1_EL1 */ -#define TCR_TBI0 __BIT(37) /* ignore Top Byte TTBR0_EL1 */ -#define TCR_AS64K __BIT(36) /* Use 64K ASIDs */ -#define TCR_IPS __BITS(34,32) /* Intermediate PhysAdr Size */ -#define TCR_IPS_256TB __SHIFTIN(5,TCR_IPS) /* 48 bits (256 TB) */ -#define TCR_IPS_64TB __SHIFTIN(4,TCR_IPS) /* 44 bits (16 TB) */ -#define TCR_IPS_4TB __SHIFTIN(3,TCR_IPS) /* 42 bits ( 4 TB) */ -#define TCR_IPS_1TB __SHIFTIN(2,TCR_IPS) /* 40 bits ( 1 TB) */ -#define TCR_IPS_64GB __SHIFTIN(1,TCR_IPS) /* 36 bits (64 GB) */ -#define TCR_IPS_4GB __SHIFTIN(0,TCR_IPS) /* 32 bits (4 GB) */ -#define TCR_TG1 __BITS(31,30) /* TTBR1 Page Granule Size */ -#define TCR_TG1_16KB __SHIFTIN(1,TCR_TG1) /* 16KB page size */ -#define TCR_TG1_4KB __SHIFTIN(2,TCR_TG1) /* 4KB page size */ -#define TCR_TG1_64KB __SHIFTIN(3,TCR_TG1) /* 64KB page size */ -#define TCR_SH1 __BITS(29,
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Thu Aug 15 09:07:34 UTC 2019 Modified Files: src/sys/arch/aarch64/include: pte.h Log Message: Indent the field value defines. NFCI. To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/aarch64/include/pte.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Tue Aug 13 08:27:42 UTC 2019 Modified Files: src/sys/arch/aarch64/include: pte.h Log Message: Add DBM To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/aarch64/include/pte.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Tue Aug 13 08:27:42 UTC 2019 Modified Files: src/sys/arch/aarch64/include: pte.h Log Message: Add DBM To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/aarch64/include/pte.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/pte.h diff -u src/sys/arch/aarch64/include/pte.h:1.5 src/sys/arch/aarch64/include/pte.h:1.6 --- src/sys/arch/aarch64/include/pte.h:1.5 Thu Oct 4 09:09:29 2018 +++ src/sys/arch/aarch64/include/pte.h Tue Aug 13 08:27:42 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: pte.h,v 1.5 2018/10/04 09:09:29 ryo Exp $ */ +/* $NetBSD: pte.h,v 1.6 2019/08/13 08:27:42 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -58,6 +58,7 @@ typedef uint64_t pt_entry_t; /* L3(4k) t #define LX_BLKPAG_UXN __BIT(54) /* Unprivileged Execute Never */ #define LX_BLKPAG_PXN __BIT(53) /* Privileged Execute Never */ #define LX_BLKPAG_CONTIG __BIT(52) /* Hint of TLB cache */ +#define LX_BLKPAG_DBM __BIT(51) /* Dirty Bit Modifier (V8.1) */ #define LX_TBL_PA __BITS(47, 12) #define LX_BLKPAG_OA __BITS(47, 12) #define LX_BLKPAG_NG __BIT(11) /* Not Global */
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Sat Aug 10 16:46:07 UTC 2019 Modified Files: src/sys/arch/aarch64/include: bus_funcs.h Log Message: Really provide bus_funcs.h To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/aarch64/include/bus_funcs.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Sat Aug 10 16:46:07 UTC 2019 Modified Files: src/sys/arch/aarch64/include: bus_funcs.h Log Message: Really provide bus_funcs.h To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/aarch64/include/bus_funcs.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/bus_funcs.h diff -u src/sys/arch/aarch64/include/bus_funcs.h:1.2 src/sys/arch/aarch64/include/bus_funcs.h:1.3 --- src/sys/arch/aarch64/include/bus_funcs.h:1.2 Sun Apr 1 04:35:03 2018 +++ src/sys/arch/aarch64/include/bus_funcs.h Sat Aug 10 16:46:07 2019 @@ -1,3 +1,3 @@ -/* $NetBSD: bus_funcs.h,v 1.2 2018/04/01 04:35:03 ryo Exp $ */ +/* $NetBSD: bus_funcs.h,v 1.3 2019/08/10 16:46:07 skrll Exp $ */ -#include +#include
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: joerg Date: Mon Aug 5 16:24:48 UTC 2019 Modified Files: src/sys/arch/aarch64/include: asm.h Log Message: Don't define register replacements when targetting 32bit ARM. To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/aarch64/include/asm.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: joerg Date: Mon Aug 5 16:24:48 UTC 2019 Modified Files: src/sys/arch/aarch64/include: asm.h Log Message: Don't define register replacements when targetting 32bit ARM. To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/aarch64/include/asm.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/asm.h diff -u src/sys/arch/aarch64/include/asm.h:1.3 src/sys/arch/aarch64/include/asm.h:1.4 --- src/sys/arch/aarch64/include/asm.h:1.3 Tue Jul 17 18:08:37 2018 +++ src/sys/arch/aarch64/include/asm.h Mon Aug 5 16:24:48 2019 @@ -1,11 +1,13 @@ -/* $NetBSD: asm.h,v 1.3 2018/07/17 18:08:37 christos Exp $ */ +/* $NetBSD: asm.h,v 1.4 2019/08/05 16:24:48 joerg Exp $ */ #ifndef _AARCH64_ASM_H_ #define _AARCH64_ASM_H_ #include +#ifdef __aarch64__ #define fp x29 #define lr x30 +#endif #endif /* !_AARCH64_ASM_H_ */
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Tue Jul 16 16:18:56 UTC 2019 Modified Files: src/sys/arch/aarch64/include: machdep.h Log Message: Add vaddr_t initarm(void *); Missed in previous commit. To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/sys/arch/aarch64/include/machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Tue Jul 16 16:18:56 UTC 2019 Modified Files: src/sys/arch/aarch64/include: machdep.h Log Message: Add vaddr_t initarm(void *); Missed in previous commit. To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/sys/arch/aarch64/include/machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/machdep.h diff -u src/sys/arch/aarch64/include/machdep.h:1.7 src/sys/arch/aarch64/include/machdep.h:1.8 --- src/sys/arch/aarch64/include/machdep.h:1.7 Sat Apr 6 03:06:24 2019 +++ src/sys/arch/aarch64/include/machdep.h Tue Jul 16 16:18:56 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: machdep.h,v 1.7 2019/04/06 03:06:24 thorpej Exp $ */ +/* $NetBSD: machdep.h,v 1.8 2019/07/16 16:18:56 skrll Exp $ */ /* * Copyright (c) 2017 Ryo Shimizu @@ -70,6 +70,12 @@ extern char *booted_kernel; extern u_int arm_cpu_max; #endif +/* + * note that we use void * as all the platforms have different ideas on what + * the structure is + */ +vaddr_t initarm(void *); + vaddr_t initarm_common(vaddr_t, vsize_t, const struct boot_physmem *, size_t); void cpu_kernel_vm_init(paddr_t, psize_t); void uartputc(int);
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Sun Jun 16 15:16:15 UTC 2019 Modified Files: src/sys/arch/aarch64/include: armreg.h Log Message: Provide icc_pmr_read To generate a diff of this commit: cvs rdiff -u -r1.24 -r1.25 src/sys/arch/aarch64/include/armreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/include/armreg.h diff -u src/sys/arch/aarch64/include/armreg.h:1.24 src/sys/arch/aarch64/include/armreg.h:1.25 --- src/sys/arch/aarch64/include/armreg.h:1.24 Wed Mar 20 07:16:07 2019 +++ src/sys/arch/aarch64/include/armreg.h Sun Jun 16 15:16:15 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: armreg.h,v 1.24 2019/03/20 07:16:07 ryo Exp $ */ +/* $NetBSD: armreg.h,v 1.25 2019/06/16 15:16:15 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -1056,6 +1056,7 @@ AARCH64REG_READ_INLINE2(icc_iar1_el1, s3 #define icc_sre_read reg_icc_sre_el1_read #define icc_sre_write reg_icc_sre_el1_write +#define icc_pmr_read reg_icc_pmr_el1_read #define icc_pmr_write reg_icc_pmr_el1_write #define icc_bpr0_write reg_icc_bpr0_el1_write #define icc_bpr1_write reg_icc_bpr1_el1_write
CVS commit: src/sys/arch/aarch64/include
Module Name:src Committed By: skrll Date: Sun Jun 16 15:16:15 UTC 2019 Modified Files: src/sys/arch/aarch64/include: armreg.h Log Message: Provide icc_pmr_read To generate a diff of this commit: cvs rdiff -u -r1.24 -r1.25 src/sys/arch/aarch64/include/armreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
re: CVS commit: src/sys/arch/aarch64/include
"Jaromir Dolecek" writes: > Module Name: src > Committed By: jdolecek > Date: Tue Nov 20 20:53:50 UTC 2018 > > Modified Files: > src/sys/arch/aarch64/include: pmap.h > > Log Message: > Implement PMAP_DIRECT / pmap_direct_process() in support of experimental > UBC optimizations (compile-tested only for now) > > PR kern/53124 can we please not commit *untested* pmap changes. espcially when this port is actively maintained and you could very easily ask someone to test this specific change. compile testing kernel changes is really bad. compile testing memory management code is pretty much forbidden. .mrg.
Re: CVS commit: src/sys/arch/aarch64/include
In article <2018071711.5b119f...@cvs.netbsd.org>, Joerg Sonnenberger wrote: >-=-=-=-=-=- > >Module Name: src >Committed By: joerg >Date: Tue Jul 17 11:55:55 UTC 2018 > >Modified Files: > src/sys/arch/aarch64/include: types.h > >Log Message: >Be consistent and explicitly size register32_t too. The reason I did not do that (I don't disagree with the change though) is that in reg.h they are declared as unsigned int, not __uint32_t. christos