CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Sun May 12 23:41:10 UTC 2024 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: s/RPMQUERY/RMPQUERY/ To generate a diff of this commit: cvs rdiff -u -r1.210 -r1.211 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.210 src/sys/arch/x86/include/specialreg.h:1.211 --- src/sys/arch/x86/include/specialreg.h:1.210 Fri Mar 8 20:29:17 2024 +++ src/sys/arch/x86/include/specialreg.h Sun May 12 23:41:10 2024 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.210 2024/03/08 20:29:17 rillig Exp $ */ +/* $NetBSD: specialreg.h,v 1.211 2024/05/12 23:41:10 msaitoh Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -1021,7 +1021,7 @@ #define CPUID_AMD_ENCMEM_SEVES __BIT(3) /* SEV Encrypted State */ #define CPUID_AMD_ENCMEM_SEV_SNP __BIT(4) /* Secure Nested Paging */ #define CPUID_AMD_ENCMEM_VMPL __BIT(5) /* Virtual Machine Privilege Lvl */ -#define CPUID_AMD_ENCMEM_RPMQUERY __BIT(6) /* RMPQUERY instruction */ +#define CPUID_AMD_ENCMEM_RMPQUERY __BIT(6) /* RMPQUERY instruction */ #define CPUID_AMD_ENCMEM_VMPLSSS __BIT(7) /* VMPL Secure Shadow Stack */ #define CPUID_AMD_ENCMEM_SECTSC __BIT(8) /* Secure TSC */ #define CPUID_AMD_ENCMEM_TSCAUX_V __BIT(9) /* TSC AUX Virtualization */
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Sun May 12 23:41:10 UTC 2024 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: s/RPMQUERY/RMPQUERY/ To generate a diff of this commit: cvs rdiff -u -r1.210 -r1.211 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: christos
Date: Tue Jan 2 19:28:25 UTC 2024
Modified Files:
src/sys/arch/x86/include: ieee.h
Log Message:
use sized types
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/x86/include/ieee.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/ieee.h
diff -u src/sys/arch/x86/include/ieee.h:1.12 src/sys/arch/x86/include/ieee.h:1.13
--- src/sys/arch/x86/include/ieee.h:1.12 Sat Sep 16 09:37:10 2023
+++ src/sys/arch/x86/include/ieee.h Tue Jan 2 14:28:25 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: ieee.h,v 1.12 2023/09/16 13:37:10 christos Exp $ */
+/* $NetBSD: ieee.h,v 1.13 2024/01/02 19:28:25 christos Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -69,13 +69,13 @@
* i386: 16 bits.
*/
struct ieee_ext {
- u_int ext_fracl:EXT_FRACLBITS;
- u_int ext_frach:EXT_FRACHBITS;
+ uint32_t ext_fracl:EXT_FRACLBITS;
+ uint32_t ext_frach:EXT_FRACHBITS;
#if 0
- u_int ext_int:1;
+ uint32_t ext_int:1;
#endif
- u_int ext_exp:EXT_EXPBITS;
- u_int ext_sign:1;
+ uint32_t ext_exp:EXT_EXPBITS;
+ uint32_t ext_sign:1;
};
/*
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: christos Date: Tue Jan 2 19:28:25 UTC 2024 Modified Files: src/sys/arch/x86/include: ieee.h Log Message: use sized types To generate a diff of this commit: cvs rdiff -u -r1.12 -r1.13 src/sys/arch/x86/include/ieee.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: mrg Date: Fri Oct 27 06:31:49 UTC 2023 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: add MSR stuff for AMD errata 1474. To generate a diff of this commit: cvs rdiff -u -r1.208 -r1.209 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.208 src/sys/arch/x86/include/specialreg.h:1.209 --- src/sys/arch/x86/include/specialreg.h:1.208 Thu Jul 27 00:34:07 2023 +++ src/sys/arch/x86/include/specialreg.h Fri Oct 27 06:31:48 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.208 2023/07/27 00:34:07 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.209 2023/10/27 06:31:48 mrg Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -1363,6 +1363,10 @@ #define NB_CFG_DISDATMSK 0x0010ULL #define NB_CFG_INITAPICCPUIDLO (1ULL << 54) +/* AMD Errata 1474. */ +#define MSR_CC6_CFG 0xc0010296 +#define CC6_CFG_DISABLE_BITS (__BIT(22) | __BIT(14) | __BIT(6)) + #define MSR_LS_CFG 0xc0011020 #define LS_CFG_ERRATA_1033 __BIT(4) #define LS_CFG_ERRATA_793 __BIT(15)
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: mrg Date: Fri Oct 27 06:31:49 UTC 2023 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: add MSR stuff for AMD errata 1474. To generate a diff of this commit: cvs rdiff -u -r1.208 -r1.209 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: christos Date: Sat Sep 16 13:37:10 UTC 2023 Modified Files: src/sys/arch/x86/include: ieee.h Log Message: protect against multiple inclusion To generate a diff of this commit: cvs rdiff -u -r1.11 -r1.12 src/sys/arch/x86/include/ieee.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: christos
Date: Sat Sep 16 13:37:10 UTC 2023
Modified Files:
src/sys/arch/x86/include: ieee.h
Log Message:
protect against multiple inclusion
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/x86/include/ieee.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/ieee.h
diff -u src/sys/arch/x86/include/ieee.h:1.11 src/sys/arch/x86/include/ieee.h:1.12
--- src/sys/arch/x86/include/ieee.h:1.11 Wed Sep 15 12:11:28 2010
+++ src/sys/arch/x86/include/ieee.h Sat Sep 16 09:37:10 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: ieee.h,v 1.11 2010/09/15 16:11:28 christos Exp $ */
+/* $NetBSD: ieee.h,v 1.12 2023/09/16 13:37:10 christos Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -39,6 +39,8 @@
*
* @(#)ieee.h 8.1 (Berkeley) 6/11/93
*/
+#ifndef _X86_IEEE_H_
+#define _X86_IEEE_H_
/*
* ieee.h defines the machine-dependent layout of the machine's IEEE
@@ -115,3 +117,5 @@ union ieee_ext_u {
#define LDBL_NBIT 0x8000
#define mask_nbit_l(u) ((u).extu_frach &= ~LDBL_NBIT)
+
+#endif /* _X86_IEEE_H_ */
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Thu Jul 27 00:34:07 UTC 2023 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add AMD IBPB_RET and BusLockThreshold. To generate a diff of this commit: cvs rdiff -u -r1.207 -r1.208 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Thu Jul 27 00:34:07 UTC 2023 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add AMD IBPB_RET and BusLockThreshold. To generate a diff of this commit: cvs rdiff -u -r1.207 -r1.208 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.207 src/sys/arch/x86/include/specialreg.h:1.208 --- src/sys/arch/x86/include/specialreg.h:1.207 Tue Jul 25 01:09:05 2023 +++ src/sys/arch/x86/include/specialreg.h Thu Jul 27 00:34:07 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.207 2023/07/25 01:09:05 mrg Exp $ */ +/* $NetBSD: specialreg.h,v 1.208 2023/07/27 00:34:07 msaitoh Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -890,6 +890,7 @@ #define CPUID_CAPEX_CPPC __BIT(27) /* Collaborative Processor Perf. Control */ #define CPUID_CAPEX_PSFD __BIT(28) /* Predictive Store Forward Dis */ #define CPUID_CAPEX_BTC_NO __BIT(29) /* Branch Type Confusion NO */ +#define CPUID_CAPEX_IBPB_RET __BIT(30) /* Clear RET address predictor */ #define CPUID_CAPEX_FLAGS "\20" \ "\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" "\4INVLPGB" \ @@ -900,7 +901,7 @@ "\24IBRS_SAMEMODE" \ "\25EFER_LSMSLE_UN""\30PPIN" \ "\31SSBD" "\32VIRT_SSBD" "\33SSB_NO" "\34CPPC" \ - "\35PSFD" "\36BTC_NO" + "\35PSFD" "\36BTC_NO" "\37IBPB_RET" /* %ecx */ #define CPUID_CAPEX_PerfTscSize __BITS(17,16) /* Perf. tstamp counter size */ @@ -940,6 +941,7 @@ #define CPUID_AMD_SVM_IBSVIRT __BIT(26) /* IBS Virtualization */ #define CPUID_AMD_SVM_XLVTOFFFLTCHG __BIT(27) /* Ext LVToffset FLT changed */ #define CPUID_AMD_SVM_VMCBADRCHKCHG __BIT(28) /* VMCB addr check changed */ +#define CPUID_AMD_SVM_BUSLOCKTHRESH __BIT(29) /* Bus Lock Threshold */ #define CPUID_AMD_SVM_FLAGS "\20" \ @@ -952,7 +954,7 @@ "\21" "VGIF" "\22" "GMET" "\23x2AVIC" "\24SSSCHECK" \ "\25" "SPEC_CTRL" "\26" "ROGPT" "\30HOST_MCE_OVERRIDE" \ "\31" "TLBICTL" "\32VNMI" "\33IBSVIRT" "\34ExtLvtOffsetFaultChg" \ - "\35VmcbAddrChkChg" + "\35VmcbAddrChkChg" "\36BusLockThreshold" /* * AMD Instruction-Based Sampling Capabilities.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Tue Apr 11 06:42:30 UTC 2023 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Fix compile error. To generate a diff of this commit: cvs rdiff -u -r1.205 -r1.206 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.205 src/sys/arch/x86/include/specialreg.h:1.206 --- src/sys/arch/x86/include/specialreg.h:1.205 Tue Apr 11 02:44:06 2023 +++ src/sys/arch/x86/include/specialreg.h Tue Apr 11 06:42:30 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.205 2023/04/11 02:44:06 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.206 2023/04/11 06:42:30 msaitoh Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -481,7 +481,7 @@ "b\14AVX512_BITALG\0" "b\15TME_EN\0" "b\16AVX512_VPOPCNTDQ\0" \ "b\20LA57\0" \ "f\21\5MAWAU\0" "b\26RDPID\0" "b\27KL\0" \ - "b\30\BUS_LOCK_DETECT" "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \ + "b\30BUS_LOCK_DETECT" "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \ "b\34MOVDIR64B\0" "b\35ENQCMD\0" "b\36SGXLC\0" "b\37PKS\0" /* %ecx = 0, %edx */
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Tue Apr 11 06:42:30 UTC 2023 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Fix compile error. To generate a diff of this commit: cvs rdiff -u -r1.205 -r1.206 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: msaitoh
Date: Tue Apr 11 02:44:06 UTC 2023
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Add CPUID 0x07 %ecx bit 24 BUS_LOCK_DETECT.
To generate a diff of this commit:
cvs rdiff -u -r1.204 -r1.205 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.204 src/sys/arch/x86/include/specialreg.h:1.205
--- src/sys/arch/x86/include/specialreg.h:1.204 Sat Mar 25 21:47:10 2023
+++ src/sys/arch/x86/include/specialreg.h Tue Apr 11 02:44:06 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.204 2023/03/25 21:47:10 andvar Exp $ */
+/* $NetBSD: specialreg.h,v 1.205 2023/04/11 02:44:06 msaitoh Exp $ */
/*
* Copyright (c) 2014-2020 The NetBSD Foundation, Inc.
@@ -466,6 +466,7 @@
#define CPUID_SEF_MAWAU __BITS(21, 17) /* MAWAU for BND{LD,ST}X */
#define CPUID_SEF_RDPID __BIT(22) /* RDPID and IA32_TSC_AUX */
#define CPUID_SEF_KL __BIT(23) /* Key Locker */
+#define CPUID_SEF_BUS_LOCK_DETECT __BIT(24) /* OS bus-lock detection */
#define CPUID_SEF_CLDEMOTE __BIT(25) /* Cache line demote */
#define CPUID_SEF_MOVDIRI __BIT(27) /* MOVDIRI instruction */
#define CPUID_SEF_MOVDIR64B __BIT(28) /* MOVDIR64B instruction */
@@ -480,7 +481,7 @@
"b\14AVX512_BITALG\0" "b\15TME_EN\0" "b\16AVX512_VPOPCNTDQ\0" \
"b\20LA57\0" \
"f\21\5MAWAU\0" "b\26RDPID\0" "b\27KL\0" \
- "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \
+ "b\30\BUS_LOCK_DETECT" "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \
"b\34MOVDIR64B\0" "b\35ENQCMD\0" "b\36SGXLC\0" "b\37PKS\0"
/* %ecx = 0, %edx */
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Tue Apr 11 02:44:06 UTC 2023 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add CPUID 0x07 %ecx bit 24 BUS_LOCK_DETECT. To generate a diff of this commit: cvs rdiff -u -r1.204 -r1.205 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Fri Feb 17 09:53:24 UTC 2023 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add AMD CPUID Fn_0008 %ebx bit 3 INVLPGB. To generate a diff of this commit: cvs rdiff -u -r1.202 -r1.203 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.202 src/sys/arch/x86/include/specialreg.h:1.203 --- src/sys/arch/x86/include/specialreg.h:1.202 Tue Feb 14 15:46:06 2023 +++ src/sys/arch/x86/include/specialreg.h Fri Feb 17 09:53:24 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.202 2023/02/14 15:46:06 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.203 2023/02/17 09:53:24 msaitoh Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -868,6 +868,7 @@ #define CPUID_CAPEX_CLZERO __BIT(0) /* CLZERO instruction */ #define CPUID_CAPEX_IRPERF __BIT(1) /* InstRetCntMsr */ #define CPUID_CAPEX_XSAVEERPTR __BIT(2) /* RstrFpErrPtrs by XRSTOR */ +#define CPUID_CAPEX_INVLPGB __BIT(3) /* INVLPGB instruction */ #define CPUID_CAPEX_RDPRU __BIT(4) /* RDPRU instruction */ #define CPUID_CAPEX_MBE __BIT(6) /* Memory Bandwidth Enforcement */ #define CPUID_CAPEX_MCOMMIT __BIT(8) /* MCOMMIT instruction */ @@ -890,7 +891,7 @@ #define CPUID_CAPEX_BTC_NO __BIT(29) /* Branch Type Confusion NO */ #define CPUID_CAPEX_FLAGS "\20" \ - "\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" \ + "\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" "\4INVLPGB" \ "\5RDPRU" "\7MBE" \ "\11MCOMMIT" "\12WBNOINVD" "\13B10" \ "\15IBPB" "\16INT_WBINVD" "\17IBRS" "\20STIBP" \
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Fri Feb 17 09:53:24 UTC 2023 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add AMD CPUID Fn_0008 %ebx bit 3 INVLPGB. To generate a diff of this commit: cvs rdiff -u -r1.202 -r1.203 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Fri Dec 30 14:50:52 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Fix comment. To generate a diff of this commit: cvs rdiff -u -r1.200 -r1.201 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Fri Dec 30 14:50:52 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Fix comment. To generate a diff of this commit: cvs rdiff -u -r1.200 -r1.201 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.200 src/sys/arch/x86/include/specialreg.h:1.201 --- src/sys/arch/x86/include/specialreg.h:1.200 Fri Dec 30 12:12:54 2022 +++ src/sys/arch/x86/include/specialreg.h Fri Dec 30 14:50:52 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.200 2022/12/30 12:12:54 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.201 2022/12/30 14:50:52 msaitoh Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -550,10 +550,10 @@ /* %ecx = 2, %edx */ #define CPUID_SEF_PSFD __BIT(0) /* Fast Forwarding Predictor Dis. */ -#define CPUID_SEF_IPRED_CTRL __BIT(1) /* bit 3&4 */ -#define CPUID_SEF_RRSBA_CTRL __BIT(2) /* bit 5 */ -#define CPUID_SEF_DDPD_U __BIT(3) /* bit 8 Data Dependent Prefetcher */ -#define CPUID_SEF_BHI_CTRL __BIT(4) /* bit 10 */ +#define CPUID_SEF_IPRED_CTRL __BIT(1) /* IPRED_DIS */ +#define CPUID_SEF_RRSBA_CTRL __BIT(2) /* RRSBA for CPL3 */ +#define CPUID_SEF_DDPD_U __BIT(3) /* Data Dependent Prefetcher */ +#define CPUID_SEF_BHI_CTRL __BIT(4) /* BHI_DIS_S */ #define CPUID_SEF_MCDT_NO __BIT(5) /* !MXCSR Config Dependent Timing */ #define CPUID_SEF2_FLAGS_D "\20"\
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Fri Dec 30 12:12:54 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Update definitions from the latest Intel SDM. - Rename HW_FEEDBACK to HWI (Hardware Feedback Interface). - Add CPUID Fn_0006 %eax bit 24 IA32_THERM_INTERRUPT MSR bit 25 Hardware Feedback Notification support. - Add CPUID Fn_0007 %ecx bit 29 ENQCMD. - Add CPUID Fn_0007 %edx bit 1 SGX-KEYS. - Add CPUID Fn_0007 %edx bit 5 UINTR(User INTeRrupts). - Add CPUID Fn_0007 %edx bit 1 RTM_ALWAYS_ABORT. - Rename TSX_FORCE_ABORT to RTM_FORCE_ABORT. - Add CPUID Fn_0007 %edx bit 22 AMX_BF16. - Add CPUID Fn_0007 %edx bit 23 AVX512_FP16. - Add CPUID Fn_0007 %edx bit 24 AMX_TILE. - Add CPUID Fn_0007 %edx bit 25 AMX_INT8. - Add CPUID Fn_0007 sub-leaf 1 %edx bit 18 CET_SSS. - Add CPUID Fn_0007 sub-leaf 2 %edx bit 0 PSFD. - Add CPUID Fn_0007 sub-leaf 2 %edx bit 1 IPRED_CTRL. - Add CPUID Fn_0007 sub-leaf 2 %edx bit 2 RRSBA_CTRL. - Add CPUID Fn_0007 sub-leaf 2 %edx bit 3 DDPD_U. - Add CPUID Fn_0007 sub-leaf 2 %edx bit 4 BHI_CTRL. - Add CPUID Fn_0007 sub-leaf 2 %edx bit 5 MCDT_NO. - Modify comment. Both Intel and AMD support CPUID Fn000b. - Add CPUID Fn_000d sub-leaf 1 %eax bit 4 XFD. - Modify comment. Hybrid Information -> Native Model ID Information. - Add CPUID Fn_001d Tile Information. - Add CPUID Fn_001e TMUL Information. To generate a diff of this commit: cvs rdiff -u -r1.199 -r1.200 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.199 src/sys/arch/x86/include/specialreg.h:1.200 --- src/sys/arch/x86/include/specialreg.h:1.199 Tue Dec 27 09:36:29 2022 +++ src/sys/arch/x86/include/specialreg.h Fri Dec 30 12:12:54 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.199 2022/12/27 09:36:29 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.200 2022/12/30 12:12:54 msaitoh Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -366,17 +366,19 @@ #define CPUID_DSPM_HWP_PECI __BIT(16) /* HWP PECI override */ #define CPUID_DSPM_HWP_FLEX __BIT(17) /* Flexible HWP */ #define CPUID_DSPM_HWP_FAST __BIT(18) /* Fast access for IA32_HWP_REQUEST */ -#define CPUID_DSPM_HW_FEEDBACK __BIT(19) /* HW_FEEDBACK*, IA32_PACKAGE_TERM* */ +#define CPUID_DSPM_HFI __BIT(19) /* Hardware Feedback Interface */ #define CPUID_DSPM_HWP_IGNIDL __BIT(20) /* Ignore Idle Logical Processor HWP */ #define CPUID_DSPM_TD __BIT(23) /* Thread Director */ +#define CPUID_DSPM_THERMI_HFN __BIT(24) /* THERM_INTERRUPT MSR HFN bit */ #define CPUID_DSPM_FLAGS "\20" \ "\1" "DTS" "\2" "IDA" "\3" "ARAT" \ "\5" "PLN" "\6" "ECMD" "\7" "PTM" "\10" "HWP" \ "\11" "HWP_NOTIFY" "\12" "HWP_ACTWIN" "\13" "HWP_EPP" "\14" "HWP_PLR" \ "\16" "HDC" "\17" "TBM3" "\20" "HWP_CAP" \ - "\21" "HWP_PECI" "\22" "HWP_FLEX" "\23" "HWP_FAST" "\24HW_FEEDBACK" \ - "\25" "HWP_IGNIDL""\30" "TD" + "\21" "HWP_PECI" "\22" "HWP_FLEX" "\23" "HWP_FAST" "\24HFI" \ + "\25" "HWP_IGNIDL""\30" "TD" \ + "\31" "THERMI_HFN" /* %ecx */ #define CPUID_DSPM_HWF __BIT(0) /* MSR_APERF/MSR_MPERF available */ @@ -467,6 +469,7 @@ #define CPUID_SEF_CLDEMOTE __BIT(25) /* Cache line demote */ #define CPUID_SEF_MOVDIRI __BIT(27) /* MOVDIRI instruction */ #define CPUID_SEF_MOVDIR64B __BIT(28) /* MOVDIR64B instruction */ +#define CPUID_SEF_ENQCMD __BIT(29) /* Enqueue Stores */ #define CPUID_SEF_SGXLC __BIT(30) /* SGX Launch Configuration */ #define CPUID_SEF_PKS __BIT(31) /* Protection Keys for kern-mode pages */ @@ -478,22 +481,29 @@ "b\20LA57\0" \ "f\21\5MAWAU\0" "b\26RDPID\0" "b\27KL\0" \ "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \ - "b\34MOVDIR64B\0" "b\36SGXLC\0" "b\37PKS\0" + "b\34MOVDIR64B\0" "b\35ENQCMD\0" "b\36SGXLC\0" "b\37PKS\0" /* %ecx = 0, %edx */ +#define CPUID_SEF_SGX_KEYS __BIT(1) /* Attestation support for SGX */ #define CPUID_SEF_AVX512_4VNNIW __BIT(2) /* AVX512 4-reg Neural Network ins */ #define CPUID_SEF_AVX512_4FMAPS __BIT(3) /* AVX512 4-reg Mult Accum Single precision */ #define CPUID_SEF_FSRM __BIT(4) /* Fast Short Rep Move */ +#define CPUID_SEF_UINTR __BIT(5) /* User Interrupts */ #define CPUID_SEF_AVX512_VP2INTERSECT __BIT(8) /* AVX512 VP2INTERSECT */ #define CPUID_SEF_SRBDS_CTRL __BIT(9) /* IA32_MCU_OPT_CTRL */ #define CPUID_SEF_MD_CLEAR __BIT(10) /* VERW clears CPU buffers */ -#define CPUID_SEF_TSX_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */ +#define CPUID_SEF_RTM_ALWAYS_ABORT __BIT(11) /* XBEGIN immediately abort */ +#define CPUID_SEF_RTM_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */ #define CPUID_SEF_SERIALIZE __BIT(14) /* SERIALIZE instruction */ #def
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Fri Dec 30 12:12:54 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Update definitions from the latest Intel SDM. - Rename HW_FEEDBACK to HWI (Hardware Feedback Interface). - Add CPUID Fn_0006 %eax bit 24 IA32_THERM_INTERRUPT MSR bit 25 Hardware Feedback Notification support. - Add CPUID Fn_0007 %ecx bit 29 ENQCMD. - Add CPUID Fn_0007 %edx bit 1 SGX-KEYS. - Add CPUID Fn_0007 %edx bit 5 UINTR(User INTeRrupts). - Add CPUID Fn_0007 %edx bit 1 RTM_ALWAYS_ABORT. - Rename TSX_FORCE_ABORT to RTM_FORCE_ABORT. - Add CPUID Fn_0007 %edx bit 22 AMX_BF16. - Add CPUID Fn_0007 %edx bit 23 AVX512_FP16. - Add CPUID Fn_0007 %edx bit 24 AMX_TILE. - Add CPUID Fn_0007 %edx bit 25 AMX_INT8. - Add CPUID Fn_0007 sub-leaf 1 %edx bit 18 CET_SSS. - Add CPUID Fn_0007 sub-leaf 2 %edx bit 0 PSFD. - Add CPUID Fn_0007 sub-leaf 2 %edx bit 1 IPRED_CTRL. - Add CPUID Fn_0007 sub-leaf 2 %edx bit 2 RRSBA_CTRL. - Add CPUID Fn_0007 sub-leaf 2 %edx bit 3 DDPD_U. - Add CPUID Fn_0007 sub-leaf 2 %edx bit 4 BHI_CTRL. - Add CPUID Fn_0007 sub-leaf 2 %edx bit 5 MCDT_NO. - Modify comment. Both Intel and AMD support CPUID Fn000b. - Add CPUID Fn_000d sub-leaf 1 %eax bit 4 XFD. - Modify comment. Hybrid Information -> Native Model ID Information. - Add CPUID Fn_001d Tile Information. - Add CPUID Fn_001e TMUL Information. To generate a diff of this commit: cvs rdiff -u -r1.199 -r1.200 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Tue Dec 27 09:36:29 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Use __BIT(). Add comment. Whitespace. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.198 -r1.199 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.198 src/sys/arch/x86/include/specialreg.h:1.199 --- src/sys/arch/x86/include/specialreg.h:1.198 Mon Nov 21 12:21:17 2022 +++ src/sys/arch/x86/include/specialreg.h Tue Dec 27 09:36:29 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.198 2022/11/21 12:21:17 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.199 2022/12/27 09:36:29 msaitoh Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -124,21 +124,21 @@ /* * Extended Control Register XCR0 */ -#define XCR0_X87 0x0001 /* x87 FPU/MMX state */ -#define XCR0_SSE 0x0002 /* SSE state */ -#define XCR0_YMM_Hi128 0x0004 /* AVX-256 (ymmn registers) */ -#define XCR0_BNDREGS 0x0008 /* Memory protection ext bounds */ -#define XCR0_BNDCSR 0x0010 /* Memory protection ext state */ -#define XCR0_Opmask 0x0020 /* AVX-512 Opmask */ -#define XCR0_ZMM_Hi256 0x0040 /* AVX-512 upper 256 bits low regs */ -#define XCR0_Hi16_ZMM 0x0080 /* AVX-512 512 bits upper registers */ -#define XCR0_PT 0x0100 /* Processor Trace state */ -#define XCR0_PKRU 0x0200 /* Protection Key state */ -#define XCR0_CET_U 0x0800 /* User CET state */ -#define XCR0_CET_S 0x1000 /* Kern CET state */ -#define XCR0_HDC 0x2000 /* Hardware Duty Cycle state */ -#define XCR0_LBR 0x8000 /* Last Branch Record */ -#define XCR0_HWP 0x0001 /* Hardware P-states */ +#define XCR0_X87 __BIT(0) /* x87 FPU/MMX state */ +#define XCR0_SSE __BIT(1) /* SSE state */ +#define XCR0_YMM_Hi128 __BIT(2) /* AVX-256 (ymmn registers) */ +#define XCR0_BNDREGS __BIT(3) /* Memory protection ext bounds */ +#define XCR0_BNDCSR __BIT(4) /* Memory protection ext state */ +#define XCR0_Opmask __BIT(5) /* AVX-512 Opmask */ +#define XCR0_ZMM_Hi256 __BIT(6) /* AVX-512 upper 256 bits low regs */ +#define XCR0_Hi16_ZMM __BIT(7) /* AVX-512 512 bits upper registers */ +#define XCR0_PT __BIT(8) /* Processor Trace state */ +#define XCR0_PKRU __BIT(9) /* Protection Key state */ +#define XCR0_CET_U __BIT(11) /* User CET state */ +#define XCR0_CET_S __BIT(12) /* Kern CET state */ +#define XCR0_HDC __BIT(13) /* Hardware Duty Cycle state */ +#define XCR0_LBR __BIT(15) /* Last Branch Record */ +#define XCR0_HWP __BIT(16) /* Hardware P-states */ #define XCR0_FLAGS1 "\20" \ "\1" "x87" "\2" "SSE" "\3" "AVX" "\4" "BNDREGS" \ @@ -224,38 +224,38 @@ #endif /* %ecx */ -#define CPUID2_SSE3 0x0001 /* Streaming SIMD Extensions 3 */ -#define CPUID2_PCLMULQDQ 0x0002 /* PCLMULQDQ instructions */ -#define CPUID2_DTES64 0x0004 /* 64-bit Debug Trace */ -#define CPUID2_MONITOR 0x0008 /* MONITOR/MWAIT instructions */ -#define CPUID2_DS_CPL 0x0010 /* CPL Qualified Debug Store */ -#define CPUID2_VMX 0x0020 /* Virtual Machine eXtensions */ -#define CPUID2_SMX 0x0040 /* Safer Mode eXtensions */ -#define CPUID2_EST 0x0080 /* Enhanced SpeedStep Technology */ -#define CPUID2_TM2 0x0100 /* Thermal Monitor 2 */ -#define CPUID2_SSSE3 0x0200 /* Supplemental SSE3 */ -#define CPUID2_CNXTID 0x0400 /* Context ID */ -#define CPUID2_SDBG 0x0800 /* Silicon Debug */ -#define CPUID2_FMA 0x1000 /* Fused Multiply Add */ -#define CPUID2_CX16 0x2000 /* CMPXCHG16B instruction */ -#define CPUID2_XTPR 0x4000 /* Task Priority Messages disabled? */ -#define CPUID2_PDCM 0x8000 /* Perf/Debug Capability MSR */ -/* bit 16 unused 0x0001 */ -#define CPUID2_PCID 0x0002 /* Process Context ID */ -#define CPUID2_DCA 0x0004 /* Direct Cache Access */ -#define CPUID2_SSE41 0x0008 /* Streaming SIMD Extensions 4.1 */ -#define CPUID2_SSE42 0x0010 /* Streaming SIMD Extensions 4.2 */ -#define CPUID2_X2APIC 0x0020 /* xAPIC Extensions */ -#define CPUID2_MOVBE 0x0040 /* MOVBE (move after byteswap) */ -#define CPUID2_POPCNT 0x0080 /* POPCNT instruction available */ -#define CPUID2_DEADLINE 0x0100 /* APIC Timer supports TSC Deadline */ -#define CPUID2_AESNI 0x0200 /* AES instructions */ -#define CPUID2_XSAVE 0x0400 /* XSAVE instructions */ -#define CPUID2_OSXSAVE 0x0800 /* XGETBV/XSETBV instructions */ -#define CPUID2_AVX 0x1000 /* AVX instructions */ -#define CPUID2_F16C 0x2000 /* half precision conversion */ -#define CPUID2_RDRAND 0x4000 /* RDRAND (hardware random number) */ -#define CPUID2_RAZ 0x8000 /* RAZ. Indicates guest state. */ +#define CPUID2_SSE3 __BIT(0) /* Streaming SIMD Extensions 3 */ +#define CPUID2_PCLMULQDQ __BIT(1) /* PCLMULQDQ instruction
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Tue Dec 27 09:36:29 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Use __BIT(). Add comment. Whitespace. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.198 -r1.199 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Mon Nov 21 12:21:17 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Update AMD CPUID Fn8000_001b - Add IbsFetchCtlExtd and IbsOpData4. - Fix typo (lbs -> Ibs). To generate a diff of this commit: cvs rdiff -u -r1.197 -r1.198 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.197 src/sys/arch/x86/include/specialreg.h:1.198 --- src/sys/arch/x86/include/specialreg.h:1.197 Wed Nov 16 14:55:50 2022 +++ src/sys/arch/x86/include/specialreg.h Mon Nov 21 12:21:17 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.197 2022/11/16 14:55:50 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.198 2022/11/21 12:21:17 msaitoh Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -908,12 +908,15 @@ #define CPUID_IBS_OPCNTEXT __BIT(6) /* OpCurCnt and OpMaxCnt extended */ #define CPUID_IBS_RIPINVALIDCHK __BIT(7) /* Invalid RIP indication */ #define CPUID_IBS_OPBRNFUSE __BIT(8) /* Fused branch micro-op indicate */ +#define CPUID_IBS_FETCHCTLEXTD __BIT(9) /* IC_IBS_EXTD_CTL MSR */ +#define CPUID_IBS_OPDATA4 __BIT(10) /* IBS op data 4 MSR */ #define CPUID_IBS_L3MISSFILT __BIT(11) /* L3 Miss Filtering */ #define CPUID_IBS_FLAGS "\20" \ "\1IBSFFV" "\2FetchSam" "\3OpSam" "\4RdWrOpCnt" \ "\5OpCnt" "\6BrnTrgt" "\7OpCntExt" "\10RipInvalidChk" \ - "\11OpBrnFuse" "\12B9""\14IbsL3MissFiltering" + "\11OpBrnFuse" "\12IbsFetchCtlExtd" "\13IbsOpData4" \ + "\14IbsL3MissFiltering" /* * AMD Cache Topology Information. @@ -980,7 +983,7 @@ "\1" "SME" "\2" "SEV" "\3" "PageFlushMsr" "\4" "SEV-ES" \ "\5" "SEV-SNP" "\6" "VMPL" "\7RMPQUERY" "\10VmplSSS" \ "\11SecureTSC" "\12TscAuxVirt" "\13HwEnfCacheCoh" "\14" "64BitHost" \ - "\15" "RSTRINJ" "\16" "ALTINJ" "\17" "DebugSwap" "\20PreventHostlbs" \ + "\15" "RSTRINJ" "\16" "ALTINJ" "\17" "DebugSwap" "\20PreventHostIbs" \ "\21VTE" "\22VmgexitParam" "\23VirtualTomMsr" "\24IbsVirtGuest" \ "\31VmsaRegProt" "\32SmtProtection" \ "\35SvsmCommPageMSR" "\36NestedVirtSnpMsr"
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Mon Nov 21 12:21:17 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Update AMD CPUID Fn8000_001b - Add IbsFetchCtlExtd and IbsOpData4. - Fix typo (lbs -> Ibs). To generate a diff of this commit: cvs rdiff -u -r1.197 -r1.198 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Wed Nov 16 13:14:34 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add Some definitions from AMD APM: - Add CPUID Fn8000_0007 %eax RAS capabilities. - Add CPUID Fn8000_001b Instruction-Based Sampling capabilities. - Add BTC_NO, ROGPT, RPMQUERY, VmplSSS, TscAuxVirt, VmgexitParam, VirtualTomMsr, bsVirtGuest, SmtProtection, vsmCommPageMSR and NestedVirtSnpMsr. To generate a diff of this commit: cvs rdiff -u -r1.194 -r1.195 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.194 src/sys/arch/x86/include/specialreg.h:1.195 --- src/sys/arch/x86/include/specialreg.h:1.194 Wed Oct 19 15:01:24 2022 +++ src/sys/arch/x86/include/specialreg.h Wed Nov 16 13:14:33 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.194 2022/10/19 15:01:24 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.195 2022/11/16 13:14:33 msaitoh Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -759,11 +759,24 @@ "\35" "L2IPERFC" "\36" "MWAITX" "\37" "AddrMaskExt" "\40" "B31" /* - * Advanced Power Management. + * Advanced Power Management and RAS. * CPUID Fn8000_0007 * * Only ITSC is for both Intel and AMD. Others are only for AMD. + * + * %ebx: RAS capabilities. See below. + * %ecx: Processor Power Monitoring Interface. + * %edx: See below. + * */ +/* %ebx */ +#define CPUID_RAS_OVFL_RECOV __BIT(0) /* MCA Overflow Recovery */ +#define CPUID_RAS_SUCCOR __BIT(1) /* Sw UnCorr. err. COntainment & Recovery */ +#define CPUID_RAS_MCAX __BIT(3) /* MCA Extension */ + +#define CPUID_RAS_FLAGS "\20" \ + "\1OVFL_RECOV" "\2SUCCOR" "\4" "MCAX" + /* %edx */ #define CPUID_APM_TS __BIT(0) /* Temperature Sensor */ #define CPUID_APM_FID __BIT(1) /* Frequency ID control */ @@ -819,6 +832,7 @@ #define CPUID_CAPEX_SSB_NO __BIT(26) /* SSBD not required */ #define CPUID_CAPEX_CPPC __BIT(27) /* Collaborative Processor Perf. Control */ #define CPUID_CAPEX_PSFD __BIT(28) /* Predictive Store Forward Dis */ +#define CPUID_CAPEX_BTC_NO __BIT(29) /* Branch Type Confusion NO */ #define CPUID_CAPEX_FLAGS "\20" \ "\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" \ @@ -829,7 +843,7 @@ "\24IBRS_SAMEMODE" \ "\25EFER_LSMSLE_UN""\30PPIN" \ "\31SSBD" "\32VIRT_SSBD" "\33SSB_NO" "\34CPPC" \ - "\35PSFD" + "\35PSFD" "\36BTC_NO" /* %ecx */ #define CPUID_CAPEX_PerfTscSize __BITS(17,16) /* Perf. tstamp counter size */ @@ -862,6 +876,7 @@ #define CPUID_AMD_SVM_X2AVIC __BIT(18) /* Virt. Intr. Ctrl 4 x2APIC */ #define CPUID_AMD_SVM_SSSCHECK __BIT(19) /* Shadow Stack restrictions */ #define CPUID_AMD_SVM_SPEC_CTRL __BIT(20) /* SPEC_CTRL virtualization */ +#define CPUID_AMD_SVM_ROGPT __BIT(21) /* Read-Only Guest PTable */ #define CPUID_AMD_SVM_HOST_MCE_OVERRIDE __BIT(23) /* #MC intercept */ #define CPUID_AMD_SVM_TLBICTL __BIT(24) /* TLB Intercept Control */ #define CPUID_AMD_SVM_VNMI __BIT(25) /* NMI Virtualization */ @@ -875,11 +890,32 @@ "\15" "PFThreshold" "\16" "AVIC" "\17" "B14" \ "\20" "V_VMSAVE_VMLOAD" \ "\21" "VGIF" "\22" "GMET" "\23x2AVIC" "\24SSSCHECK" \ - "\25" "SPEC_CTRL" "\30HOST_MCE_OVERRIDE" \ + "\25" "SPEC_CTRL" "\26" "ROGPT" "\30HOST_MCE_OVERRIDE" \ "\31" "TLBICTL" "\32VNMI" "\33IBSVIRT" "\34B27" \ "\35B28" /* + * AMD Instruction-Based Sampling Capabilities. + * CPUID Fn8000_001b + */ +/* %eax */ +#define CPUID_IBS_FFV __BIT(0) /* Feature Flags Valid */ +#define CPUID_IBS_FETCHSUM __BIT(1) /* Fetch Sampling */ +#define CPUID_IBS_OPSAM __BIT(2) /* execution SAMpling */ +#define CPUID_IBS_RDWROPCNT __BIT(3) /* Read Write of Op Counter */ +#define CPUID_IBS_OPCNT __BIT(4) /* OP CouNTing mode */ +#define CPUID_IBS_BRNTRGT __BIT(5) /* Branch Target */ +#define CPUID_IBS_OPCNTEXT __BIT(6) /* OpCurCnt and OpMaxCnt extended */ +#define CPUID_IBS_RIPINVALIDCHK __BIT(7) /* Invalid RIP indication */ +#define CPUID_IBS_OPBRNFUSE __BIT(8) /* Fused branch micro-op indicate */ +#define CPUID_IBS_L3MISSFILT __BIT(11) /* L3 Miss Filtering */ + +#define CPUID_IBS_FLAGS "\20" \ + "\1IBSFFV" "\2FetchSam" "\3OpSam" "\4RdWrOpCnt" \ + "\5OpCnt" "\6BrnTrgt" "\7OpCntExt" "\10RipInvalidChk" \ + "\11OpBrnFuse" "\12B9""\14IbsL3MissFiltering" + +/* * AMD Cache Topology Information. * CPUID Fn8000_001d * It's almost the same as Intel Deterministic Cache Parameter Leaf(0x04) @@ -920,7 +956,10 @@ #define CPUID_AMD_ENCMEM_SEVES __BIT(3) /* SEV Encrypted State */ #define CPUID_AMD_ENCMEM_SEV_SNP __BIT(4) /* Secure Nested Paging */ #define CPUID_AMD_ENCMEM_VMPL __BIT(5) /* Virtual Machine Privilege Lvl */ +#define CPUID_AMD_ENCMEM_RPMQUERY __BIT(6) /* RMPQUERY instruction */ +#define CPUID_AMD_ENCME
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Wed Nov 16 13:14:34 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add Some definitions from AMD APM: - Add CPUID Fn8000_0007 %eax RAS capabilities. - Add CPUID Fn8000_001b Instruction-Based Sampling capabilities. - Add BTC_NO, ROGPT, RPMQUERY, VmplSSS, TscAuxVirt, VmgexitParam, VirtualTomMsr, bsVirtGuest, SmtProtection, vsmCommPageMSR and NestedVirtSnpMsr. To generate a diff of this commit: cvs rdiff -u -r1.194 -r1.195 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Wed Oct 19 15:01:24 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add AMD cpuid Fn8000_000a x2AVIC, VNMI and IBSVIRT from APM Vol. 3 Rev. 3.34. To generate a diff of this commit: cvs rdiff -u -r1.193 -r1.194 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: msaitoh
Date: Wed Oct 19 15:01:24 UTC 2022
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Add AMD cpuid Fn8000_000a x2AVIC, VNMI and IBSVIRT from APM Vol. 3 Rev. 3.34.
To generate a diff of this commit:
cvs rdiff -u -r1.193 -r1.194 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.193 src/sys/arch/x86/include/specialreg.h:1.194
--- src/sys/arch/x86/include/specialreg.h:1.193 Wed Oct 12 10:25:41 2022
+++ src/sys/arch/x86/include/specialreg.h Wed Oct 19 15:01:24 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.193 2022/10/12 10:25:41 msaitoh Exp $ */
+/* $NetBSD: specialreg.h,v 1.194 2022/10/19 15:01:24 msaitoh Exp $ */
/*
* Copyright (c) 2014-2020 The NetBSD Foundation, Inc.
@@ -859,10 +859,13 @@
#define CPUID_AMD_SVM_V_VMSAVE_VMLOAD __BIT(15) /* Virtual VM{SAVE/LOAD} */
#define CPUID_AMD_SVM_vGIF __BIT(16) /* Virtualized GIF */
#define CPUID_AMD_SVM_GMET __BIT(17) /* Guest Mode Execution Trap */
+#define CPUID_AMD_SVM_X2AVIC __BIT(18) /* Virt. Intr. Ctrl 4 x2APIC */
#define CPUID_AMD_SVM_SSSCHECK __BIT(19) /* Shadow Stack restrictions */
#define CPUID_AMD_SVM_SPEC_CTRL __BIT(20) /* SPEC_CTRL virtualization */
#define CPUID_AMD_SVM_HOST_MCE_OVERRIDE __BIT(23) /* #MC intercept */
#define CPUID_AMD_SVM_TLBICTL __BIT(24) /* TLB Intercept Control */
+#define CPUID_AMD_SVM_VNMI __BIT(25) /* NMI Virtualization */
+#define CPUID_AMD_SVM_IBSVIRT __BIT(26) /* IBS Virtualization */
#define CPUID_AMD_SVM_FLAGS "\20" \
"\1" "NP" "\2" "LbrVirt" "\3" "SVML" "\4" "NRIPS" \
@@ -871,9 +874,9 @@
"\11" "B08" "\12" "B09" "\13" "PauseFilter" "\14" "B11" \
"\15" "PFThreshold" "\16" "AVIC" "\17" "B14" \
"\20" "V_VMSAVE_VMLOAD" \
- "\21" "VGIF" "\22" "GMET" "\23B18" "\24SSSCHECK" \
+ "\21" "VGIF" "\22" "GMET" "\23x2AVIC" "\24SSSCHECK" \
"\25" "SPEC_CTRL" "\30HOST_MCE_OVERRIDE" \
- "\31" "TLBICTL" "\32B25" "\32B26" "\32B27" \
+ "\31" "TLBICTL" "\32VNMI" "\33IBSVIRT" "\34B27" \
"\35B28"
/*
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Wed Oct 12 10:25:41 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add CPUID Fn8000_001e Processor Topology Information. To generate a diff of this commit: cvs rdiff -u -r1.192 -r1.193 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.192 src/sys/arch/x86/include/specialreg.h:1.193 --- src/sys/arch/x86/include/specialreg.h:1.192 Thu Oct 6 00:22:16 2022 +++ src/sys/arch/x86/include/specialreg.h Wed Oct 12 10:25:41 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.192 2022/10/06 00:22:16 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.193 2022/10/12 10:25:41 msaitoh Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -886,6 +886,22 @@ */ /* + * AMD Processor Topology Information. + * CPUID Fn8000_001e + * %eax: Extended APIC ID. + * %ebx: Core Identifiers. + * %ecx: Node Identifiers. + */ + +/* %ebx */ +#define CPUID_AMD_PROCT_COREID __BITS(7,0) /* Core ID */ +#define CPUID_AMD_PROCT_THREADS_PER_CORE __BITS(15,8) /* Threads/Core - 1 */ + +/* %ecx */ +#define CPUID_AMD_PROCT_NODEID __BITS(7,0) /* Node ID */ +#define CPUID_AMD_PROCT_NODE_PER_PROCESSOR __BITS(10,8) /* Node/Processor -1 */ + +/* * AMD Encrypted Memory Capabilities. * CPUID Fn8000_001f * %eax: flags
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Wed Oct 12 10:25:41 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add CPUID Fn8000_001e Processor Topology Information. To generate a diff of this commit: cvs rdiff -u -r1.192 -r1.193 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Thu Oct 6 06:51:37 UTC 2022 Modified Files: src/sys/arch/x86/include: i82093reg.h Log Message: IOAPIC_ID_MASK is 8 bits these days. Fixes PR kern/54276. To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/x86/include/i82093reg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Thu Oct 6 06:51:37 UTC 2022 Modified Files: src/sys/arch/x86/include: i82093reg.h Log Message: IOAPIC_ID_MASK is 8 bits these days. Fixes PR kern/54276. To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/x86/include/i82093reg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/i82093reg.h diff -u src/sys/arch/x86/include/i82093reg.h:1.6 src/sys/arch/x86/include/i82093reg.h:1.7 --- src/sys/arch/x86/include/i82093reg.h:1.6 Wed Jun 19 06:32:46 2019 +++ src/sys/arch/x86/include/i82093reg.h Thu Oct 6 06:51:36 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: i82093reg.h,v 1.6 2019/06/19 06:32:46 msaitoh Exp $ */ +/* $NetBSD: i82093reg.h,v 1.7 2022/10/06 06:51:36 msaitoh Exp $ */ /*- * Copyright (c) 2000 The NetBSD Foundation, Inc. @@ -60,7 +60,7 @@ #define IOAPIC_ID 0x00 #define IOAPIC_ID_SHIFT 24 -#define IOAPIC_ID_MASK 0x0f00 +#define IOAPIC_ID_MASK 0xff00 /* Version, and maximum interrupt pin number. */
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: riastradh Date: Tue Sep 13 09:40:18 UTC 2022 Modified Files: src/sys/arch/x86/include: pmap_private.h Log Message: x86/pmap.h: Need machine/cpufunc.h for invlpg. To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/x86/include/pmap_private.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/pmap_private.h diff -u src/sys/arch/x86/include/pmap_private.h:1.2 src/sys/arch/x86/include/pmap_private.h:1.3 --- src/sys/arch/x86/include/pmap_private.h:1.2 Sat Aug 20 23:49:31 2022 +++ src/sys/arch/x86/include/pmap_private.h Tue Sep 13 09:40:17 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: pmap_private.h,v 1.2 2022/08/20 23:49:31 riastradh Exp $ */ +/* $NetBSD: pmap_private.h,v 1.3 2022/09/13 09:40:17 riastradh Exp $ */ /* * Copyright (c) 1997 Charles D. Cranor and Washington University. @@ -80,6 +80,7 @@ #include #include +#include #include #include
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: riastradh Date: Tue Sep 13 09:40:18 UTC 2022 Modified Files: src/sys/arch/x86/include: pmap_private.h Log Message: x86/pmap.h: Need machine/cpufunc.h for invlpg. To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/x86/include/pmap_private.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: riastradh Date: Sat Aug 20 23:12:01 UTC 2022 Modified Files: src/sys/arch/x86/include: bootinfo.h Log Message: x86/bootinfo.h: Add include guard. To generate a diff of this commit: cvs rdiff -u -r1.30 -r1.31 src/sys/arch/x86/include/bootinfo.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/bootinfo.h diff -u src/sys/arch/x86/include/bootinfo.h:1.30 src/sys/arch/x86/include/bootinfo.h:1.31 --- src/sys/arch/x86/include/bootinfo.h:1.30 Fri Jun 21 02:08:55 2019 +++ src/sys/arch/x86/include/bootinfo.h Sat Aug 20 23:12:00 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: bootinfo.h,v 1.30 2019/06/21 02:08:55 nonaka Exp $ */ +/* $NetBSD: bootinfo.h,v 1.31 2022/08/20 23:12:00 riastradh Exp $ */ /* * Copyright (c) 1997 @@ -26,6 +26,9 @@ * */ +#ifndef _X86_BOOTINFO_H_ +#define _X86_BOOTINFO_H_ + #define BTINFO_BOOTPATH 0 #define BTINFO_ROOTDEVICE 1 #define BTINFO_BOOTDISK 3 @@ -275,3 +278,5 @@ void aprint_bootinfo(void); #endif /* _LOCORE */ #endif /* _KERNEL */ + +#endif /* _X86_BOOTINFO_H_ */
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: riastradh Date: Sat Aug 20 23:12:01 UTC 2022 Modified Files: src/sys/arch/x86/include: bootinfo.h Log Message: x86/bootinfo.h: Add include guard. To generate a diff of this commit: cvs rdiff -u -r1.30 -r1.31 src/sys/arch/x86/include/bootinfo.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: riastradh
Date: Sat Aug 20 10:54:53 UTC 2022
Modified Files:
src/sys/arch/x86/include: efi.h
Log Message:
x86/efi.h: Assert size of struct efi_systbl.
To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/x86/include/efi.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/efi.h
diff -u src/sys/arch/x86/include/efi.h:1.13 src/sys/arch/x86/include/efi.h:1.14
--- src/sys/arch/x86/include/efi.h:1.13 Sat Aug 20 09:43:27 2022
+++ src/sys/arch/x86/include/efi.h Sat Aug 20 10:54:53 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: efi.h,v 1.13 2022/08/20 09:43:27 riastradh Exp $ */
+/* $NetBSD: efi.h,v 1.14 2022/08/20 10:54:53 riastradh Exp $ */
/*-
* Copyright (c) 2004 Marcel Moolenaar
@@ -306,6 +306,11 @@ struct efi_systbl {
u_long st_entries;
struct efi_cfgtbl *st_cfgtbl;
};
+#ifdef _LP64
+__CTASSERT(sizeof(struct efi_systbl) == 120);
+#else
+__CTASSERT(sizeof(struct efi_systbl) == 72);
+#endif
#if defined(__amd64__)
struct efi_cfgtbl32 {
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: riastradh Date: Sat Aug 20 10:54:53 UTC 2022 Modified Files: src/sys/arch/x86/include: efi.h Log Message: x86/efi.h: Assert size of struct efi_systbl. To generate a diff of this commit: cvs rdiff -u -r1.13 -r1.14 src/sys/arch/x86/include/efi.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: riastradh
Date: Sat Aug 20 09:40:04 UTC 2022
Modified Files:
src/sys/arch/x86/include: efi.h
Log Message:
x86/efi.h: Fix whitespace. No functional change intended.
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/x86/include/efi.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/efi.h
diff -u src/sys/arch/x86/include/efi.h:1.11 src/sys/arch/x86/include/efi.h:1.12
--- src/sys/arch/x86/include/efi.h:1.11 Sat Aug 20 09:09:06 2022
+++ src/sys/arch/x86/include/efi.h Sat Aug 20 09:40:04 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: efi.h,v 1.11 2022/08/20 09:09:06 riastradh Exp $ */
+/* $NetBSD: efi.h,v 1.12 2022/08/20 09:40:04 riastradh Exp $ */
/*-
* Copyright (c) 2004 Marcel Moolenaar
@@ -35,9 +35,9 @@
#include
-#defineEFI_PAGE_SHIFT 12
-#defineEFI_PAGE_SIZE (1 << EFI_PAGE_SHIFT)
-#defineEFI_PAGE_MASK (EFI_PAGE_SIZE - 1)
+#define EFI_PAGE_SHIFT 12
+#define EFI_PAGE_SIZE (1 << EFI_PAGE_SHIFT)
+#define EFI_PAGE_MASK (EFI_PAGE_SIZE - 1)
#define EFI_TABLE_ACPI20 \
{0x8868e871,0xe4f1,0x11d3,0xbc,0x22,{0x00,0x80,0xc7,0x3c,0x88,0x81}}
@@ -60,7 +60,7 @@ enum efi_reset {
EFI_RESET_WARM
};
-typedef uint16_t efi_char;
+typedef uint16_t efi_char;
typedef unsigned long efi_status;
#if defined(__amd64__)
@@ -70,94 +70,94 @@ typedef uint32_t uintn;
#endif
struct efi_cfgtbl {
- struct uuid ct_uuid;
- void *ct_data;
+ struct uuid ct_uuid;
+ void *ct_data;
};
struct efi_md {
- uint32_tmd_type;
-#defineEFI_MD_TYPE_NULL0
-#defineEFI_MD_TYPE_CODE1 /* Loader text. */
-#defineEFI_MD_TYPE_DATA2 /* Loader data. */
-#defineEFI_MD_TYPE_BS_CODE 3 /* Boot services text. */
-#defineEFI_MD_TYPE_BS_DATA 4 /* Boot services data. */
-#defineEFI_MD_TYPE_RT_CODE 5 /* Runtime services text. */
-#defineEFI_MD_TYPE_RT_DATA 6 /* Runtime services data. */
-#defineEFI_MD_TYPE_FREE7 /* Unused/free memory. */
-#defineEFI_MD_TYPE_BAD 8 /* Bad memory */
-#defineEFI_MD_TYPE_RECLAIM 9 /* ACPI reclaimable memory. */
-#defineEFI_MD_TYPE_FIRMWARE10 /* ACPI NV memory */
-#defineEFI_MD_TYPE_IOMEM 11 /* Memory-mapped I/O. */
-#defineEFI_MD_TYPE_IOPORT 12 /* I/O port space. */
-#defineEFI_MD_TYPE_PALCODE 13 /* PAL */
-#defineEFI_MD_TYPE_PMEM14 /* Persistent memory. */
- uint32_t__pad;
- uint64_tmd_phys;
- uint64_tmd_virt;
- uint64_tmd_pages;
- uint64_tmd_attr;
-#defineEFI_MD_ATTR_UC 0x0001UL
-#defineEFI_MD_ATTR_WC 0x0002UL
-#defineEFI_MD_ATTR_WT 0x0004UL
-#defineEFI_MD_ATTR_WB 0x0008UL
-#defineEFI_MD_ATTR_UCE 0x0010UL
-#defineEFI_MD_ATTR_WP 0x1000UL
-#defineEFI_MD_ATTR_RP 0x2000UL
-#defineEFI_MD_ATTR_XP 0x4000UL
-#defineEFI_MD_ATTR_NV 0x8000UL
-#defineEFI_MD_ATTR_MORE_RELIABLE 0x0001UL
-#defineEFI_MD_ATTR_RO 0x0002UL
-#defineEFI_MD_ATTR_SP 0x0004UL
-#defineEFI_MD_ATTR_CPU_CRYPTO 0x0008UL
-#defineEFI_MD_ATTR_RT 0x8000UL
+ uint32_t md_type;
+#define EFI_MD_TYPE_NULL 0
+#define EFI_MD_TYPE_CODE 1 /* Loader text. */
+#define EFI_MD_TYPE_DATA 2 /* Loader data. */
+#define EFI_MD_TYPE_BS_CODE 3 /* Boot services text. */
+#define EFI_MD_TYPE_BS_DATA 4 /* Boot services data. */
+#define EFI_MD_TYPE_RT_CODE 5 /* Runtime services text. */
+#define EFI_MD_TYPE_RT_DATA 6 /* Runtime services data. */
+#define EFI_MD_TYPE_FREE 7 /* Unused/free memory. */
+#define EFI_MD_TYPE_BAD 8 /* Bad memory */
+#define EFI_MD_TYPE_RECLAIM 9 /* ACPI reclaimable memory. */
+#define EFI_MD_TYPE_FIRMWARE 10 /* ACPI NV memory */
+#define EFI_MD_TYPE_IOMEM 11 /* Memory-mapped I/O. */
+#define EFI_MD_TYPE_IOPORT 12 /* I/O port space. */
+#define EFI_MD_TYPE_PALCODE 13 /* PAL */
+#define EFI_MD_TYPE_PMEM 14 /* Persistent memory. */
+ uint32_t __pad;
+ uint64_t md_phys;
+ uint64_t md_virt;
+ uint64_t md_pages;
+ uint64_t md_attr;
+#define EFI_MD_ATTR_UC 0x0001UL
+#define EFI_MD_ATTR_WC 0x0002UL
+#define EFI_MD_ATTR_WT 0x0004UL
+#define EFI_MD_ATTR_WB 0x0008UL
+#define EFI_MD_ATTR_UCE 0x0010UL
+#define EFI_MD_ATTR_WP 0x1000UL
+#define EFI_MD_ATTR_RP 0x0
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: riastradh Date: Sat Aug 20 09:40:04 UTC 2022 Modified Files: src/sys/arch/x86/include: efi.h Log Message: x86/efi.h: Fix whitespace. No functional change intended. To generate a diff of this commit: cvs rdiff -u -r1.11 -r1.12 src/sys/arch/x86/include/efi.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Wed Jun 15 16:25:33 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Modify CPUID Fn000a %ebx's string. Add new string for %ecx. To generate a diff of this commit: cvs rdiff -u -r1.190 -r1.191 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.190 src/sys/arch/x86/include/specialreg.h:1.191 --- src/sys/arch/x86/include/specialreg.h:1.190 Mon Jun 13 06:22:31 2022 +++ src/sys/arch/x86/include/specialreg.h Wed Jun 15 16:25:33 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.190 2022/06/13 06:22:31 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.191 2022/06/15 16:25:33 msaitoh Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -560,8 +560,13 @@ #define CPUID_PERF_TOPDOWNSLOT __BIT(7) /* No top-down slots */ #define CPUID_PERF_FLAGS1 "\177\20" \ - "b\0CORECYCL\0" "b\1INSTRETRY\0" "b\2REFCYCL\0" "b\3LLCREF\0" \ - "b\4LLCMISS\0" "b\5BRINSRETR\0" "b\6BRMISPRRETR\0" "b\7TOPDOWNSLOT\0" + "b\0CORECYCL\0" "b\1INST\0" "b\2REFCYCL\0" "b\3LLCREF\0" \ + "b\4LLCMISS\0" "b\5BRINST\0" "b\6BRMISPR\0" "b\7TOPDOWNSLOT\0" + +/* %ecx */ + +#define CPUID_PERF_FLAGS2 "\177\20" \ + "b\0INST\0" "b\1CLK_CORETHREAD\0" "b\2CLK_REF_TSC\0" "b\3TOPDOWNSLOT\0" /* %edx */ #define CPUID_PERF_NFFPC __BITS(4, 0) /* Num of fixed-funct perfcnt */
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Wed Jun 15 16:25:33 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Modify CPUID Fn000a %ebx's string. Add new string for %ecx. To generate a diff of this commit: cvs rdiff -u -r1.190 -r1.191 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Mon Jun 13 06:22:32 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add top-down slots event bit of architectural performance monitoring leaf. To generate a diff of this commit: cvs rdiff -u -r1.189 -r1.190 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Mon Jun 13 06:22:32 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add top-down slots event bit of architectural performance monitoring leaf. To generate a diff of this commit: cvs rdiff -u -r1.189 -r1.190 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.189 src/sys/arch/x86/include/specialreg.h:1.190 --- src/sys/arch/x86/include/specialreg.h:1.189 Tue Feb 1 05:27:40 2022 +++ src/sys/arch/x86/include/specialreg.h Mon Jun 13 06:22:31 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.189 2022/02/01 05:27:40 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.190 2022/06/13 06:22:31 msaitoh Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -557,10 +557,11 @@ #define CPUID_PERF_LLCMISS __BIT(4) /* No LLCache miss */ #define CPUID_PERF_BRINSRETR __BIT(5) /* No branch inst. retried */ #define CPUID_PERF_BRMISPRRETR __BIT(6) /* No branch mispredict retry */ +#define CPUID_PERF_TOPDOWNSLOT __BIT(7) /* No top-down slots */ -#define CPUID_PERF_FLAGS1 "\177\20" \ - "b\0CORECYCL\0" "b\1INSTRETRY\0" "b\2REFCYCL\0" "b\3LLCREF\0" \ - "b\4LLCMISS\0" "b\5BRINSRETR\0" "b\6BRMISPRRETR\0" +#define CPUID_PERF_FLAGS1 "\177\20" \ + "b\0CORECYCL\0" "b\1INSTRETRY\0" "b\2REFCYCL\0" "b\3LLCREF\0" \ + "b\4LLCMISS\0" "b\5BRINSRETR\0" "b\6BRMISPRRETR\0" "b\7TOPDOWNSLOT\0" /* %edx */ #define CPUID_PERF_NFFPC __BITS(4, 0) /* Num of fixed-funct perfcnt */
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: skrll Date: Fri Apr 1 06:49:17 UTC 2022 Modified Files: src/sys/arch/x86/include: efi.h Log Message: Trailing whitespace To generate a diff of this commit: cvs rdiff -u -r1.9 -r1.10 src/sys/arch/x86/include/efi.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: skrll
Date: Fri Apr 1 06:49:17 UTC 2022
Modified Files:
src/sys/arch/x86/include: efi.h
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/x86/include/efi.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/efi.h
diff -u src/sys/arch/x86/include/efi.h:1.9 src/sys/arch/x86/include/efi.h:1.10
--- src/sys/arch/x86/include/efi.h:1.9 Fri Oct 18 00:54:48 2019
+++ src/sys/arch/x86/include/efi.h Fri Apr 1 06:49:17 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: efi.h,v 1.9 2019/10/18 00:54:48 manu Exp $ */
+/* $NetBSD: efi.h,v 1.10 2022/04/01 06:49:17 skrll Exp $ */
/*-
* Copyright (c) 2004 Marcel Moolenaar
@@ -233,7 +233,7 @@ struct efi_bs {
efi_status (*bs_calculatecrc32)(void *, uintn, uint32_t *);
efi_status (*bs_copymem)(void *, void *, uintn);
efi_status (*bs_setmem)(void *, uintn, uint8_t);
- efi_status (*bs_createeventex)(uint32_t, efi_tpl,
+ efi_status (*bs_createeventex)(uint32_t, efi_tpl,
efi_event_notify, void *, struct uuid, efi_event *);
};
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Tue Feb 1 05:27:40 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: s/shareing/sharing/. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.188 -r1.189 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.188 src/sys/arch/x86/include/specialreg.h:1.189 --- src/sys/arch/x86/include/specialreg.h:1.188 Sat Jan 29 08:18:22 2022 +++ src/sys/arch/x86/include/specialreg.h Tue Feb 1 05:27:40 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.188 2022/01/29 08:18:22 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.189 2022/02/01 05:27:40 msaitoh Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -311,7 +311,7 @@ #define CPUID_DCP_CACHELEVEL __BITS(7, 5) /* Cache level (start at 1) */ #define CPUID_DCP_SELFINITCL __BIT(8) /* Self initializing cachelvl*/ #define CPUID_DCP_FULLASSOC __BIT(9) /* Full associative */ -#define CPUID_DCP_SHAREING __BITS(25, 14) /* shareing */ +#define CPUID_DCP_SHARING __BITS(25, 14) /* sharing */ #define CPUID_DCP_CORE_P_PKG __BITS(31, 26) /* Cores/package */ /* %ebx */ @@ -648,7 +648,7 @@ #define CPUID_DATP_TCTYPE_S 5 /* Store only TLB */ #define CPUID_DATP_TCLEVEL __BITS(7, 5) /* TLB level (start at 1) */ #define CPUID_DATP_FULLASSOC __BIT(8) /* Full associative */ -#define CPUID_DATP_SHAREING __BITS(25, 14) /* shareing */ +#define CPUID_DATP_SHARING __BITS(25, 14) /* sharing */ /* * Intel Hybrid Information Enumeration.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Tue Feb 1 05:27:40 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: s/shareing/sharing/. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.188 -r1.189 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Sat Jan 29 08:18:22 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add Intel Hybrid Information Enumeration (CPUID Fn_001a). To generate a diff of this commit: cvs rdiff -u -r1.187 -r1.188 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.187 src/sys/arch/x86/include/specialreg.h:1.188 --- src/sys/arch/x86/include/specialreg.h:1.187 Mon Jan 17 20:56:02 2022 +++ src/sys/arch/x86/include/specialreg.h Sat Jan 29 08:18:22 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.187 2022/01/17 20:56:02 andvar Exp $ */ +/* $NetBSD: specialreg.h,v 1.188 2022/01/29 08:18:22 msaitoh Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -650,6 +650,15 @@ #define CPUID_DATP_FULLASSOC __BIT(8) /* Full associative */ #define CPUID_DATP_SHAREING __BITS(25, 14) /* shareing */ +/* + * Intel Hybrid Information Enumeration. + * CPUID Fn_001a + */ +/* %eax */ +#define CPUID_HYBRID_NATIVEID __BITS(23, 0) /* Native model ID */ +#define CPUID_HYBRID_CORETYPE __BITS(31, 24) /* Core type */ +#define CPUID_HYBRID_CORETYPE_ATOM 0x20 /* Atom */ +#define CPUID_HYBRID_CORETYPE_CORE 0x40 /* Core */ /* * Intel extended features.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Sat Jan 29 08:18:22 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add Intel Hybrid Information Enumeration (CPUID Fn_001a). To generate a diff of this commit: cvs rdiff -u -r1.187 -r1.188 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: msaitoh
Date: Sat Jan 15 10:59:40 UTC 2022
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Add Some definitions from AMD APM:
- CPUID Fn8001 %ecx bit 30 AddrMaskExt.
- CPUID Fn8008 %ebx bit 13 INT_WBINVD.
- CPUID Fn8008 %ebx bit 19 IbrsSameMode.
- CPUID Fn8008 %ebx bit 20 EferLmsleUnsupported.
- CPUID Fn8008 %ebx bit 28 PSFD.
- CPUID Fn8008 %edx bit 30 as "B30". Not documented.
- CPUID Fn801f %eax bit 8 SecureTSC.
- CPUID Fn801f %eax bit 24 VmsaRegProt.
- Tested by nonaka@.
To generate a diff of this commit:
cvs rdiff -u -r1.185 -r1.186 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.185 src/sys/arch/x86/include/specialreg.h:1.186
--- src/sys/arch/x86/include/specialreg.h:1.185 Sat Jan 15 10:09:15 2022
+++ src/sys/arch/x86/include/specialreg.h Sat Jan 15 10:59:40 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.185 2022/01/15 10:09:15 msaitoh Exp $ */
+/* $NetBSD: specialreg.h,v 1.186 2022/01/15 10:59:40 msaitoh Exp $ */
/*
* Copyright (c) 2014-2020 The NetBSD Foundation, Inc.
@@ -730,6 +730,7 @@
#define CPUID_PTSC __BIT(27) /* PerfTsc */
#define CPUID_L2IPERFC __BIT(28) /* L2I performance counter Extension */
#define CPUID_MWAITX __BIT(29) /* MWAITX/MONITORX support */
+#define CPUID_ADDRMASKEXT __BIT(30) /* Breakpoint Addressing Mask ext. */
#define CPUID_AMD_FLAGS4 "\20" \
"\1" "LAHF" "\2" "CMPLEGACY" "\3" "SVM" "\4" "EAPIC" \
@@ -740,7 +741,7 @@
"\21" "FMA4" "\22" "TCE" "\23" "B18" "\24" "NodeID" \
"\25" "B20" "\26" "TBM" "\27" "TopoExt" "\30" "PCExtC" \
"\31" "PCExtNB" "\32" "StrmPM" "\33" "DBExt" "\34" "PerfTsc" \
- "\35" "L2IPERFC" "\36" "MWAITX" "\37" "B30" "\40" "B31"
+ "\35" "L2IPERFC" "\36" "MWAITX" "\37" "AddrMaskExt" "\40" "B31"
/*
* Advanced Power Management.
@@ -788,22 +789,29 @@
#define CPUID_CAPEX_MCOMMIT __BIT(8) /* MCOMMIT instruction */
#define CPUID_CAPEX_WBNOINVD __BIT(9) /* WBNOINVD instruction */
#define CPUID_CAPEX_IBPB __BIT(12) /* Speculation Control IBPB */
+#define CPUID_CAPEX_INT_WBINVD __BIT(13) /* Interruptable WB[NO]INVD */
#define CPUID_CAPEX_IBRS __BIT(14) /* Speculation Control IBRS */
#define CPUID_CAPEX_STIBP __BIT(15) /* Speculation Control STIBP */
#define CPUID_CAPEX_IBRS_ALWAYSON __BIT(16) /* IBRS always on mode */
#define CPUID_CAPEX_STIBP_ALWAYSON __BIT(17) /* STIBP always on mode */
#define CPUID_CAPEX_PREFER_IBRS __BIT(18) /* IBRS preferred */
+#define CPUID_CAPEX_IBRS_SAMEMODE __BIT(19) /* IBRS same speculation limits */
+#define CPUID_CAPEX_EFER_LSMSLE_UN __BIT(20) /* EFER.LMSLE is unsupported */
#define CPUID_CAPEX_SSBD __BIT(24) /* Speculation Control SSBD */
#define CPUID_CAPEX_VIRT_SSBD __BIT(25) /* Virt Spec Control SSBD */
#define CPUID_CAPEX_SSB_NO __BIT(26) /* SSBD not required */
+#define CPUID_CAPEX_PSFD __BIT(28) /* Predictive Store Froward Dis */
#define CPUID_CAPEX_FLAGS "\20" \
"\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" \
"\5RDPRU" "\7B6" \
"\11MCOMMIT" "\12WBNOINVD" "\13B10" \
- "\15IBPB" "\16B13" "\17IBRS" "\20STIBP" \
- "\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS" "\24B19" \
- "\31SSBD" "\32VIRT_SSBD" "\33SSB_NO"
+ "\15IBPB" "\16INT_WBINVD" "\17IBRS" "\20STIBP" \
+ "\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS" \
+ "\24IBRS_SAMEMODE" \
+ "\25EFER_LSMSLE_UN" \
+ "\31SSBD" "\32VIRT_SSBD" "\33SSB_NO" \
+ "\35PSFD"
/* %ecx */
#define CPUID_CAPEX_PerfTscSize __BITS(17,16)
@@ -833,6 +841,7 @@
#define CPUID_AMD_SVM_V_VMSAVE_VMLOAD __BIT(15) /* Virtual VM{SAVE/LOAD} */
#define CPUID_AMD_SVM_vGIF __BIT(16) /* Virtualized GIF */
#define CPUID_AMD_SVM_GMET __BIT(17) /* Guest Mode Execution Trap */
+#define CPUID_AMD_SVM_SSSCHECK __BIT(19) /* Shadow Stack restrictions */
#define CPUID_AMD_SVM_SPEC_CTRL __BIT(20) /* SPEC_CTRL virtualization */
#define CPUID_AMD_SVM_TLBICTL __BIT(24) /* TLB Intercept Control */
@@ -843,9 +852,10 @@
"\11" "B08" "\12" "B09" "\13" "PauseFilter" "\14" "B11" \
"\15" "PFThreshold" "\16" "AVIC" "\17" "B14" \
"\20" "V_VMSAVE_VMLOAD" \
- "\21" "VGIF" "\22" "GMET" \
+ "\21" "VGIF" "\22" "GMET" "\24SSSCHECK" \
"\25" "SPEC_CTRL" \
- "\31" "TLBICTL"
+ "\31" "TLBICTL" \
+ "\35B28"
/*
* AMD Cache Topology Information.
@@ -872,6 +882,7 @@
#define CPUID_AMD_ENCMEM_SEVES __BIT(3) /* SEV Encrypted State */
#define CPUID_AMD_ENCMEM_SEV_SNP __BIT(4) /* Secure Nested Paging */
#define CPUID_AMD_ENCMEM_VMPL __BIT(5) /* Virtual Machine Privilege Lvl */
+#define CPUID_AMD_ENCMEM_SECTSC __BIT(8) /* Secure TSC */
#define CPUID_AMD_ENCMEM_HECC __BIT(10) /
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Sat Jan 15 10:59:40 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add Some definitions from AMD APM: - CPUID Fn8001 %ecx bit 30 AddrMaskExt. - CPUID Fn8008 %ebx bit 13 INT_WBINVD. - CPUID Fn8008 %ebx bit 19 IbrsSameMode. - CPUID Fn8008 %ebx bit 20 EferLmsleUnsupported. - CPUID Fn8008 %ebx bit 28 PSFD. - CPUID Fn8008 %edx bit 30 as "B30". Not documented. - CPUID Fn801f %eax bit 8 SecureTSC. - CPUID Fn801f %eax bit 24 VmsaRegProt. - Tested by nonaka@. To generate a diff of this commit: cvs rdiff -u -r1.185 -r1.186 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Sat Jan 15 10:09:15 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Whitespace. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.184 -r1.185 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.184 src/sys/arch/x86/include/specialreg.h:1.185 --- src/sys/arch/x86/include/specialreg.h:1.184 Sat Jan 15 09:58:23 2022 +++ src/sys/arch/x86/include/specialreg.h Sat Jan 15 10:09:15 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.184 2022/01/15 09:58:23 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.185 2022/01/15 10:09:15 msaitoh Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -781,28 +781,28 @@ */ /* %ebx */ -#define CPUID_CAPEX_CLZERO __BIT(0) /* CLZERO instruction */ -#define CPUID_CAPEX_IRPERF __BIT(1) /* InstRetCntMsr */ -#define CPUID_CAPEX_XSAVEERPTR __BIT(2) /* RstrFpErrPtrs by XRSTOR */ -#define CPUID_CAPEX_RDPRU __BIT(4) /* RDPRU instruction */ -#define CPUID_CAPEX_MCOMMIT __BIT(8) /* MCOMMIT instruction */ -#define CPUID_CAPEX_WBNOINVD __BIT(9) /* WBNOINVD instruction */ -#define CPUID_CAPEX_IBPB __BIT(12) /* Speculation Control IBPB */ -#define CPUID_CAPEX_IBRS __BIT(14) /* Speculation Control IBRS */ -#define CPUID_CAPEX_STIBP __BIT(15) /* Speculation Control STIBP */ -#define CPUID_CAPEX_IBRS_ALWAYSON __BIT(16) /* IBRS always on mode */ -#define CPUID_CAPEX_STIBP_ALWAYSON __BIT(17) /* STIBP always on mode */ -#define CPUID_CAPEX_PREFER_IBRS __BIT(18) /* IBRS preferred */ -#define CPUID_CAPEX_SSBD __BIT(24) /* Speculation Control SSBD */ -#define CPUID_CAPEX_VIRT_SSBD __BIT(25) /* Virt Spec Control SSBD */ -#define CPUID_CAPEX_SSB_NO __BIT(26) /* SSBD not required */ - -#define CPUID_CAPEX_FLAGS "\20" \ - "\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" \ - "\5RDPRU" "\7B6" \ - "\11MCOMMIT" "\12WBNOINVD" "\13B10" \ - "\15IBPB" "\16B13" "\17IBRS" "\20STIBP" \ - "\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS" "\24B19" \ +#define CPUID_CAPEX_CLZERO __BIT(0) /* CLZERO instruction */ +#define CPUID_CAPEX_IRPERF __BIT(1) /* InstRetCntMsr */ +#define CPUID_CAPEX_XSAVEERPTR __BIT(2) /* RstrFpErrPtrs by XRSTOR */ +#define CPUID_CAPEX_RDPRU __BIT(4) /* RDPRU instruction */ +#define CPUID_CAPEX_MCOMMIT __BIT(8) /* MCOMMIT instruction */ +#define CPUID_CAPEX_WBNOINVD __BIT(9) /* WBNOINVD instruction */ +#define CPUID_CAPEX_IBPB __BIT(12) /* Speculation Control IBPB */ +#define CPUID_CAPEX_IBRS __BIT(14) /* Speculation Control IBRS */ +#define CPUID_CAPEX_STIBP __BIT(15) /* Speculation Control STIBP */ +#define CPUID_CAPEX_IBRS_ALWAYSON __BIT(16) /* IBRS always on mode */ +#define CPUID_CAPEX_STIBP_ALWAYSON __BIT(17) /* STIBP always on mode */ +#define CPUID_CAPEX_PREFER_IBRS __BIT(18) /* IBRS preferred */ +#define CPUID_CAPEX_SSBD __BIT(24) /* Speculation Control SSBD */ +#define CPUID_CAPEX_VIRT_SSBD __BIT(25) /* Virt Spec Control SSBD */ +#define CPUID_CAPEX_SSB_NO __BIT(26) /* SSBD not required */ + +#define CPUID_CAPEX_FLAGS "\20" \ + "\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" \ + "\5RDPRU" "\7B6" \ + "\11MCOMMIT" "\12WBNOINVD" "\13B10" \ + "\15IBPB" "\16B13" "\17IBRS" "\20STIBP" \ + "\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS" "\24B19" \ "\31SSBD" "\32VIRT_SSBD" "\33SSB_NO" /* %ecx */
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Sat Jan 15 10:09:15 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Whitespace. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.184 -r1.185 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Sat Jan 15 09:58:23 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Move CPUID_CAPEX_FLAGS next to %eax because it's for %eax. To generate a diff of this commit: cvs rdiff -u -r1.183 -r1.184 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.183 src/sys/arch/x86/include/specialreg.h:1.184 --- src/sys/arch/x86/include/specialreg.h:1.183 Sat Jan 15 09:55:13 2022 +++ src/sys/arch/x86/include/specialreg.h Sat Jan 15 09:58:23 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.183 2022/01/15 09:55:13 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.184 2022/01/15 09:58:23 msaitoh Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -797,11 +797,6 @@ #define CPUID_CAPEX_VIRT_SSBD __BIT(25) /* Virt Spec Control SSBD */ #define CPUID_CAPEX_SSB_NO __BIT(26) /* SSBD not required */ -/* %ecx */ -#define CPUID_CAPEX_PerfTscSize __BITS(17,16) -#define CPUID_CAPEX_ApicIdSize __BITS(15,12) -#define CPUID_CAPEX_NC __BITS(7,0) - #define CPUID_CAPEX_FLAGS "\20" \ "\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" \ "\5RDPRU" "\7B6" \ @@ -810,6 +805,11 @@ "\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS" "\24B19" \ "\31SSBD" "\32VIRT_SSBD" "\33SSB_NO" +/* %ecx */ +#define CPUID_CAPEX_PerfTscSize __BITS(17,16) +#define CPUID_CAPEX_ApicIdSize __BITS(15,12) +#define CPUID_CAPEX_NC __BITS(7,0) + /* * AMD SVM Revision and Feature. * CPUID Fn8000_000a
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Sat Jan 15 09:58:23 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Move CPUID_CAPEX_FLAGS next to %eax because it's for %eax. To generate a diff of this commit: cvs rdiff -u -r1.183 -r1.184 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Sat Jan 15 09:55:14 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: No functional change. - Modify comment. Add comment. Fix typo. Mainly taken from dragonfly. - Use __BIT(). To generate a diff of this commit: cvs rdiff -u -r1.182 -r1.183 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.182 src/sys/arch/x86/include/specialreg.h:1.183 --- src/sys/arch/x86/include/specialreg.h:1.182 Fri Jan 14 15:46:41 2022 +++ src/sys/arch/x86/include/specialreg.h Sat Jan 15 09:55:13 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.182 2022/01/14 15:46:41 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.183 2022/01/15 09:55:13 msaitoh Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -97,29 +97,29 @@ /* * CR4 */ -#define CR4_VME 0x0001 /* virtual 8086 mode extension enable */ -#define CR4_PVI 0x0002 /* protected mode virtual interrupt enable */ -#define CR4_TSD 0x0004 /* restrict RDTSC instruction to cpl 0 */ -#define CR4_DE 0x0008 /* debugging extension */ -#define CR4_PSE 0x0010 /* large (4MB) page size enable */ -#define CR4_PAE 0x0020 /* physical address extension enable */ -#define CR4_MCE 0x0040 /* machine check enable */ -#define CR4_PGE 0x0080 /* page global enable */ -#define CR4_PCE 0x0100 /* enable RDPMC instruction for all cpls */ -#define CR4_OSFXSR 0x0200 /* enable fxsave/fxrestor and SSE */ -#define CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */ -#define CR4_UMIP 0x0800 /* user-mode instruction prevention */ +#define CR4_VME 0x0001 /* Virtual 8086 mode extension enable */ +#define CR4_PVI 0x0002 /* Protected mode virtual interrupt enable */ +#define CR4_TSD 0x0004 /* Restrict RDTSC instruction to cpl 0 */ +#define CR4_DE 0x0008 /* Debugging extension */ +#define CR4_PSE 0x0010 /* Large (4MB) page size enable */ +#define CR4_PAE 0x0020 /* Physical address extension enable */ +#define CR4_MCE 0x0040 /* Machine check enable */ +#define CR4_PGE 0x0080 /* Page global enable */ +#define CR4_PCE 0x0100 /* Enable RDPMC instruction for all cpls */ +#define CR4_OSFXSR 0x0200 /* Enable fxsave/fxrestor and SSE */ +#define CR4_OSXMMEXCPT 0x0400 /* Enable unmasked SSE exceptions */ +#define CR4_UMIP 0x0800 /* User Mode Instruction Prevention */ #define CR4_LA57 0x1000 /* 57-bit linear addresses */ -#define CR4_VMXE 0x2000 /* enable VMX operations */ -#define CR4_SMXE 0x4000 /* enable SMX operations */ -#define CR4_FSGSBASE 0x0001 /* enable *FSBASE and *GSBASE instructions */ -#define CR4_PCIDE 0x0002 /* enable Process Context IDentifiers */ -#define CR4_OSXSAVE 0x0004 /* enable xsave and xrestore */ -#define CR4_SMEP 0x0010 /* enable SMEP support */ -#define CR4_SMAP 0x0020 /* enable SMAP support */ -#define CR4_PKE 0x0040 /* enable Protection Keys for user pages */ -#define CR4_CET 0x0080 /* enable CET */ -#define CR4_PKS 0x0100 /* enable Protection Keys for kern pages */ +#define CR4_VMXE 0x2000 /* Enable VMX operations */ +#define CR4_SMXE 0x4000 /* Enable SMX operations */ +#define CR4_FSGSBASE 0x0001 /* Enable *FSBASE and *GSBASE instructions */ +#define CR4_PCIDE 0x0002 /* Enable Process Context IDentifiers */ +#define CR4_OSXSAVE 0x0004 /* Enable xsave and xrestore */ +#define CR4_SMEP 0x0010 /* Enable SMEP support */ +#define CR4_SMAP 0x0020 /* Enable SMAP support */ +#define CR4_PKE 0x0040 /* Enable Protection Keys for user pages */ +#define CR4_CET 0x0080 /* Enable CET */ +#define CR4_PKS 0x0100 /* Enable Protection Keys for kern pages */ /* * Extended Control Register XCR0 @@ -172,17 +172,17 @@ #define XSAVE_MAX_COMPONENT XSAVE_Hi16_ZMM /* - * CPUID "features" bits + * "features" bits. + * CPUID Fn0001 */ - -/* Fn0001 %edx features */ +/* %edx */ #define CPUID_FPU 0x0001 /* processor has an FPU? */ #define CPUID_VME 0x0002 /* has virtual mode (%cr4's VME/PVI) */ #define CPUID_DE 0x0004 /* has debugging extension */ #define CPUID_PSE 0x0008 /* has 4MB page size extension */ #define CPUID_TSC 0x0010 /* has time stamp counter */ #define CPUID_MSR 0x0020 /* has model specific registers */ -#define CPUID_PAE 0x0040 /* has phys address extension */ +#define CPUID_PAE 0x0040 /* has physical address extension */ #define CPUID_MCE 0x0080 /* has machine check exception */ #define CPUID_CX8 0x0100 /* has CMPXCHG8B instruction */ #define CPUID_APIC 0x0200 /* has enabled APIC */ @@ -193,17 +193,17 @@ #define CPUID_CMOV 0x8000 /* has CMOVcc instruction */ #define CPUID_PAT 0x0001 /* Page Attrib
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Sat Jan 15 09:55:14 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: No functional change. - Modify comment. Add comment. Fix typo. Mainly taken from dragonfly. - Use __BIT(). To generate a diff of this commit: cvs rdiff -u -r1.182 -r1.183 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Fri Jan 14 15:46:41 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add Architectural LBR and Linear Address Masking. To generate a diff of this commit: cvs rdiff -u -r1.181 -r1.182 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Fri Jan 14 15:46:41 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add Architectural LBR and Linear Address Masking. To generate a diff of this commit: cvs rdiff -u -r1.181 -r1.182 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.181 src/sys/arch/x86/include/specialreg.h:1.182 --- src/sys/arch/x86/include/specialreg.h:1.181 Fri Jan 14 15:45:53 2022 +++ src/sys/arch/x86/include/specialreg.h Fri Jan 14 15:46:41 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.181 2022/01/14 15:45:53 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.182 2022/01/14 15:46:41 msaitoh Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -497,6 +497,7 @@ #define CPUID_SEF_HYBRID __BIT(15) /* Hybrid part */ #define CPUID_SEF_TSXLDTRK __BIT(16) /* TSX suspend load addr tracking */ #define CPUID_SEF_PCONFIG __BIT(18) /* Platform CONFIGuration */ +#define CPUID_SEF_ARCH_LBR __BIT(19) /* Architectural LBR */ #define CPUID_SEF_CET_IBT __BIT(20) /* CET Indirect Branch Tracking */ #define CPUID_SEF_IBRS __BIT(26) /* IBRS / IBPB Speculation Control */ #define CPUID_SEF_STIBP __BIT(27) /* STIBP Speculation Control */ @@ -510,7 +511,7 @@ "\5" "FSREP_MOV" \ "\11VP2INTERSECT" "\12SRBDS_CTRL" "\13MD_CLEAR" \ "\16TSX_FORCE_ABORT" "\17SERIALIZE" "\20HYBRID" \ - "\21" "TSXLDTRK" "\23" "PCONFIG" \ + "\21" "TSXLDTRK" "\23" "PCONFIG" "\24" "ARCH_LBR" \ "\25" "CET_IBT" \ "\33" "IBRS" "\34" "STIBP" \ "\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\37CORE_CAP" "\40" "SSBD" @@ -522,11 +523,14 @@ #define CPUID_SEF_FSRSB __BIT(11) /* fast short REP STOSB */ #define CPUID_SEF_FSRCS __BIT(12) /* fast short REP CMPSB, REP SCASB */ #define CPUID_SEF_HRESET __BIT(22) /* HREST & IA32_HRESET_ENABLE MSR */ +#define CPUID_SEF_LAM __BIT(26) /* Linear Address Masking */ #define CPUID_SEF1_FLAGS_A "\20" \ "\5" "AVXVNNI" "\6" "AVX512_BF16"\ "\13" "FZLRMS" "\14" "FSRSB" \ - "\15" "FSRCS" "\27" "HRESET" + "\15" "FSRCS" "\27" "HRESET" \ + "\31" "LAM" + /* %ecx = 1, %ebx */ #define CPUID_SEF_PPIN __BIT(0) /* IA32_PPIN & IA32_PPIN_CTL MSRs */
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Fri Jan 14 15:45:53 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Both Intel and AMD says the name of CPUID 0x01 %edx bit 19 is "CLFSH". To generate a diff of this commit: cvs rdiff -u -r1.180 -r1.181 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Fri Jan 14 15:45:53 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Both Intel and AMD says the name of CPUID 0x01 %edx bit 19 is "CLFSH". To generate a diff of this commit: cvs rdiff -u -r1.180 -r1.181 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.180 src/sys/arch/x86/include/specialreg.h:1.181 --- src/sys/arch/x86/include/specialreg.h:1.180 Thu Jan 13 16:03:38 2022 +++ src/sys/arch/x86/include/specialreg.h Fri Jan 14 15:45:53 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.180 2022/01/13 16:03:38 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.181 2022/01/14 15:45:53 msaitoh Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -211,7 +211,7 @@ "\5" "TSC" "\6" "MSR" "\7" "PAE" "\10" "MCE" \ "\11" "CX8" "\12" "APIC" "\13" "B10" "\14" "SEP" \ "\15" "MTRR" "\16" "PGE" "\17" "MCA" "\20" "CMOV" \ - "\21" "PAT" "\22" "PSE36" "\23" "PN" "\24" "CLFLUSH" \ + "\21" "PAT" "\22" "PSE36" "\23" "PN" "\24" "CLFSH" \ "\25" "B20" "\26" "DS" "\27" "ACPI" "\30" "MMX" \ "\31" "FXSR" "\32" "SSE" "\33" "SSE2" "\34" "SS" \ "\35" "HTT" "\36" "TM" "\37" "IA64" "\40" "PBE"
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Thu Jan 13 16:03:38 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add some CPUID bits from the latest Intel SDM. - Last Branch Record. - Thread Director. - AVX version of VNNI. - Fast short REP MOV. - HRESET. - PPIN. To generate a diff of this commit: cvs rdiff -u -r1.179 -r1.180 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.179 src/sys/arch/x86/include/specialreg.h:1.180 --- src/sys/arch/x86/include/specialreg.h:1.179 Thu Jan 13 00:21:41 2022 +++ src/sys/arch/x86/include/specialreg.h Thu Jan 13 16:03:38 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.179 2022/01/13 00:21:41 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.180 2022/01/13 16:03:38 msaitoh Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -137,13 +137,14 @@ #define XCR0_CET_U 0x0800 /* User CET state */ #define XCR0_CET_S 0x1000 /* Kern CET state */ #define XCR0_HDC 0x2000 /* Hardware Duty Cycle state */ +#define XCR0_LBR 0x8000 /* Last Branch Record */ #define XCR0_HWP 0x0001 /* Hardware P-states */ #define XCR0_FLAGS1 "\20" \ "\1" "x87" "\2" "SSE" "\3" "AVX" "\4" "BNDREGS" \ "\5" "BNDCSR" "\6" "Opmask" "\7" "ZMM_Hi256" "\10" "Hi16_ZMM" \ "\11" "PT" "\12" "PKRU" "\14" "CET_U" \ - "\15" "CET_S" "\16" "HDC" \ + "\15" "CET_S" "\16" "HDC" "\20" "LBR" \ "\21" "HWP" /* @@ -370,6 +371,7 @@ #define CPUID_DSPM_HWP_FAST __BIT(18) /* Fast access for IA32_HWP_REQUEST */ #define CPUID_DSPM_HW_FEEDBACK __BIT(19) /* HW_FEEDBACK*, IA32_PACKAGE_TERM* */ #define CPUID_DSPM_HWP_IGNIDL __BIT(20) /* Ignore Idle Logical Processor HWP */ +#define CPUID_DSPM_TD __BIT(23) /* Thread Director */ #define CPUID_DSPM_FLAGS "\20" \ "\1" "DTS" "\2" "IDA" "\3" "ARAT" \ @@ -377,7 +379,7 @@ "\11" "HWP_NOTIFY" "\12" "HWP_ACTWIN" "\13" "HWP_EPP" "\14" "HWP_PLR" \ "\16" "HDC" "\17" "TBM3" "\20" "HWP_CAP" \ "\21" "HWP_PECI" "\22" "HWP_FLEX" "\23" "HWP_FAST" "\24HW_FEEDBACK" \ - "\25" "HWP_IGNIDL" + "\25" "HWP_IGNIDL""\30" "TD" /* * Intel/AMD Digital Thermal Sensor and @@ -385,8 +387,11 @@ */ #define CPUID_DSPM_HWF __BIT(0) /* MSR_APERF/MSR_MPERF available */ #define CPUID_DSPM_EPB __BIT(3) /* Energy Performance Bias */ +#define CPUID_DSPM_NTDC __BITS(15, 8) /* Number of Thread Director Classes */ -#define CPUID_DSPM_FLAGS1 "\20" "\1" "HWF" "\4" "EPB" +#define CPUID_DSPM_FLAGS1 "\177\20"\ + "b\0HWF\0" "b\3EPB\0" \ + "f\10\10NTDC\0" /* * Intel/AMD Structured Extended Feature leaf Fn_0007 @@ -511,9 +516,23 @@ "\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\37CORE_CAP" "\40" "SSBD" /* %ecx = 1, %eax */ +#define CPUID_SEF_AVXVNNI __BIT(4) /* AVX version of VNNI */ #define CPUID_SEF_AVX512_BF16 __BIT(5) -#define CPUID_SEF1_FLAGS_A "\20" \ -"\6" "AVX512_BF16" +#define CPUID_SEF_FZLRMS __BIT(10) /* fast zero-length REP MOVSB */ +#define CPUID_SEF_FSRSB __BIT(11) /* fast short REP STOSB */ +#define CPUID_SEF_FSRCS __BIT(12) /* fast short REP CMPSB, REP SCASB */ +#define CPUID_SEF_HRESET __BIT(22) /* HREST & IA32_HRESET_ENABLE MSR */ + +#define CPUID_SEF1_FLAGS_A "\20" \ + "\5" "AVXVNNI" "\6" "AVX512_BF16"\ + "\13" "FZLRMS" "\14" "FSRSB" \ + "\15" "FSRCS" "\27" "HRESET" +/* %ecx = 1, %ebx */ +#define CPUID_SEF_PPIN __BIT(0) /* IA32_PPIN & IA32_PPIN_CTL MSRs */ + +#define CPUID_SEF1_FLAGS_B "\20"\ +"\1" "PPIN" + /* * Intel CPUID Architectural Performance Monitoring Fn000a *
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Thu Jan 13 16:03:38 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add some CPUID bits from the latest Intel SDM. - Last Branch Record. - Thread Director. - AVX version of VNNI. - Fast short REP MOV. - HRESET. - PPIN. To generate a diff of this commit: cvs rdiff -u -r1.179 -r1.180 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Thu Jan 13 00:21:41 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Use __BIT(). KNF. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.178 -r1.179 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.178 src/sys/arch/x86/include/specialreg.h:1.179 --- src/sys/arch/x86/include/specialreg.h:1.178 Thu Sep 30 15:54:55 2021 +++ src/sys/arch/x86/include/specialreg.h Thu Jan 13 00:21:41 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.178 2021/09/30 15:54:55 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.179 2022/01/13 00:21:41 msaitoh Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -139,12 +139,12 @@ #define XCR0_HDC 0x2000 /* Hardware Duty Cycle state */ #define XCR0_HWP 0x0001 /* Hardware P-states */ -#define XCR0_FLAGS1 "\20" \ - "\1" "x87" "\2" "SSE" "\3" "AVX" \ - "\4" "BNDREGS" "\5" "BNDCSR" "\6" "Opmask" \ - "\7" "ZMM_Hi256" "\10" "Hi16_ZMM" "\11" "PT" \ - "\12" "PKRU" "\14" "CET_U" "\15" "CET_S" \ - "\16" "HDC" "\21" "HWP" +#define XCR0_FLAGS1 "\20" \ + "\1" "x87" "\2" "SSE" "\3" "AVX" "\4" "BNDREGS" \ + "\5" "BNDCSR" "\6" "Opmask" "\7" "ZMM_Hi256" "\10" "Hi16_ZMM" \ + "\11" "PT" "\12" "PKRU" "\14" "CET_U" \ + "\15" "CET_S" "\16" "HDC" \ + "\21" "HWP" /* * Known FPU bits, only these get enabled. The save area is sized for all the @@ -205,14 +205,14 @@ #define CPUID_TM 0x2000 /* thermal monitor (TCC) */ #define CPUID_PBE 0x8000 /* Pending Break Enable */ -#define CPUID_FLAGS1 "\20" \ - "\1" "FPU" "\2" "VME" "\3" "DE" "\4" "PSE" \ - "\5" "TSC" "\6" "MSR" "\7" "PAE" "\10" "MCE" \ - "\11" "CX8" "\12" "APIC" "\13" "B10" "\14" "SEP" \ - "\15" "MTRR" "\16" "PGE" "\17" "MCA" "\20" "CMOV" \ +#define CPUID_FLAGS1 "\20" \ + "\1" "FPU" "\2" "VME" "\3" "DE" "\4" "PSE" \ + "\5" "TSC" "\6" "MSR" "\7" "PAE" "\10" "MCE" \ + "\11" "CX8" "\12" "APIC" "\13" "B10" "\14" "SEP" \ + "\15" "MTRR" "\16" "PGE" "\17" "MCA" "\20" "CMOV" \ "\21" "PAT" "\22" "PSE36" "\23" "PN" "\24" "CLFLUSH" \ - "\25" "B20" "\26" "DS" "\27" "ACPI" "\30" "MMX" \ - "\31" "FXSR" "\32" "SSE" "\33" "SSE2" "\34" "SS" \ + "\25" "B20" "\26" "DS" "\27" "ACPI" "\30" "MMX" \ + "\31" "FXSR" "\32" "SSE" "\33" "SSE2" "\34" "SS" \ "\35" "HTT" "\36" "TM" "\37" "IA64" "\40" "PBE" /* Blacklists of CPUID flags - used to mask certain features */ @@ -259,14 +259,14 @@ #define CPUID2_RDRAND 0x4000 /* RDRAND (hardware random number) */ #define CPUID2_RAZ 0x8000 /* RAZ. Indicates guest state. */ -#define CPUID2_FLAGS1 "\20" \ - "\1" "SSE3" "\2" "PCLMULQDQ" "\3" "DTES64" "\4" "MONITOR" \ - "\5" "DS-CPL" "\6" "VMX" "\7" "SMX" "\10" "EST" \ - "\11" "TM2" "\12" "SSSE3" "\13" "CID" "\14" "SDBG" \ - "\15" "FMA" "\16" "CX16" "\17" "xTPR" "\20" "PDCM" \ - "\21" "B16" "\22" "PCID" "\23" "DCA" "\24" "SSE41" \ - "\25" "SSE42" "\26" "X2APIC" "\27" "MOVBE" "\30" "POPCNT" \ - "\31" "DEADLINE" "\32" "AES" "\33" "XSAVE" "\34" "OSXSAVE" \ +#define CPUID2_FLAGS1 "\20" \ + "\1" "SSE3" "\2" "PCLMULQDQ" "\3" "DTES64" "\4" "MONITOR" \ + "\5" "DS-CPL" "\6" "VMX" "\7" "SMX" "\10" "EST" \ + "\11" "TM2" "\12" "SSSE3" "\13" "CID" "\14" "SDBG" \ + "\15" "FMA" "\16" "CX16" "\17" "xTPR" "\20" "PDCM" \ + "\21" "B16" "\22" "PCID" "\23" "DCA" "\24" "SSE41" \ + "\25" "SSE42" "\26" "X2APIC" "\27" "MOVBE" "\30" "POPCNT" \ + "\31" "DEADLINE" "\32" "AES" "\33" "XSAVE" "\34" "OSXSAVE" \ "\35" "AVX" "\36" "F16C" "\37" "RDRAND" "\40" "RAZ" /* CPUID Fn0001 %eax */ @@ -351,19 +351,19 @@ * Intel/AMD Digital Thermal Sensor and * Power Management, Fn_0006 - %eax. */ -#define CPUID_DSPM_DTS __BIT(0) /* Digital Thermal Sensor */ -#define CPUID_DSPM_IDA __BIT(1) /* Intel Dynamic Acceleration */ -#define CPUID_DSPM_ARAT __BIT(2) /* Always Running APIC Timer */ -#define CPUID_DSPM_PLN __BIT(4) /* Power Limit Notification */ -#define CPUID_DSPM_ECMD __BIT(5) /* Clock Modulation Extension */ -#define CPUID_DSPM_PTM __BIT(6) /* Package Level Thermal Management */ -#define CPUID_DSPM_HWP __BIT(7) /* HWP */ +#define CPUID_DSPM_DTS __BIT(0) /* Digital Thermal Sensor */ +#define CPUID_DSPM_IDA __BIT(1) /* Intel Dynamic Acceleration */ +#define CPUID_DSPM_ARAT __BIT(2) /* Always Running APIC Timer */ +#define CPUID_DSPM_PLN __BIT(4) /* Power Limit Notification */ +#define CPUID_DSPM_ECMD __BIT(5) /* Clock Modulation Extension */ +#define CPUID_DSPM_PTM __BIT(6) /* Package Level Thermal Management */ +#define CPUID_DSPM_HWP __BIT(7) /* HWP */ #define CPUID_DSPM_HWP_NOTIFY __BIT(8) /* HWP Notification */ -#define CPUID_DSPM_HWP_ACTWIN __BIT(9) /* HWP Activity Window */ -#define CPUID_DSPM_HWP_EPP __BIT(10) /* HWP Energy Performance P
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Thu Jan 13 00:21:41 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Use __BIT(). KNF. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.178 -r1.179 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Thu Dec 9 14:33:19 UTC 2021 Modified Files: src/sys/arch/x86/include: cacheinfo.h Log Message: Print TLB message consistently to improve readability. Example: cpu0: L2 cache: 256KB 64B/line 4-way cpu0: L3 cache: 4MB 64B/line 16-way cpu0: 64B prefetching -cpu0: ITLB: 64 4KB entries 8-way, 2M/4M: 8 entries +cpu0: ITLB: 64 4KB entries 8-way, 8 2M/4M entries cpu0: DTLB: 64 4KB entries 4-way, 4 1GB entries 4-way cpu0: L2 STLB: 1536 4KB entries 6-way cpu0: Initial APIC ID 0 To generate a diff of this commit: cvs rdiff -u -r1.30 -r1.31 src/sys/arch/x86/include/cacheinfo.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/cacheinfo.h diff -u src/sys/arch/x86/include/cacheinfo.h:1.30 src/sys/arch/x86/include/cacheinfo.h:1.31 --- src/sys/arch/x86/include/cacheinfo.h:1.30 Thu Oct 7 13:04:18 2021 +++ src/sys/arch/x86/include/cacheinfo.h Thu Dec 9 14:33:19 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: cacheinfo.h,v 1.30 2021/10/07 13:04:18 msaitoh Exp $ */ +/* $NetBSD: cacheinfo.h,v 1.31 2021/12/09 14:33:19 msaitoh Exp $ */ #ifndef _X86_CACHEINFO_H_ #define _X86_CACHEINFO_H_ @@ -224,39 +224,39 @@ __CI_TBL(CAI_DTLB2,0x04,4, 8, 4 __CI_TBL(CAI_DTLB2,0x05,4, 32, 4 * 1024 * 1024, NULL), \ __CI_TBL(CAI_ITLB2,0x0b,4, 4, 4 * 1024 * 1024, NULL), \ __CI_TBL(CAI_ITLB, 0x4f, 0xff, 32,4 * 1024, NULL), \ -__CI_TBL(CAI_ITLB, 0x50, 0xff, 64,4 * 1024, "4K/4M: 64 entries"), \ -__CI_TBL(CAI_ITLB, 0x51, 0xff, 64,4 * 1024, "4K/4M: 128 entries"),\ -__CI_TBL(CAI_ITLB, 0x52, 0xff, 64,4 * 1024, "4K/4M: 256 entries"),\ -__CI_TBL(CAI_ITLB2,0x55, 0xff, 64,4 * 1024, "2M/4M: 7 entries"), \ +__CI_TBL(CAI_ITLB, 0x50, 0xff, 64,4 * 1024, "64 4K/4M entries"), \ +__CI_TBL(CAI_ITLB, 0x51, 0xff, 64,4 * 1024, "128 4K/4M entries"),\ +__CI_TBL(CAI_ITLB, 0x52, 0xff, 64,4 * 1024, "256 4K/4M entries"),\ +__CI_TBL(CAI_ITLB2,0x55, 0xff, 64,4 * 1024, "7 2M/4M entries"), \ __CI_TBL(CAI_DTLB2,0x56,4, 16, 4 * 1024 * 1024, NULL), \ __CI_TBL(CAI_DTLB, 0x57,4, 16,4 * 1024, NULL), \ __CI_TBL(CAI_DTLB, 0x59, 0xff, 16,4 * 1024, NULL), \ -__CI_TBL(CAI_DTLB2,0x5a, 0xff, 64,4 * 1024, "2M/4M: 32 entries (L0)"), \ -__CI_TBL(CAI_DTLB, 0x5b, 0xff, 64,4 * 1024, "4K/4M: 64 entries"), \ -__CI_TBL(CAI_DTLB, 0x5c, 0xff, 64,4 * 1024, "4K/4M: 128 entries"),\ -__CI_TBL(CAI_DTLB, 0x5d, 0xff, 64,4 * 1024, "4K/4M: 256 entries"),\ +__CI_TBL(CAI_DTLB2,0x5a, 0xff, 64,4 * 1024, "32 2M/4M entries (L0)"), \ +__CI_TBL(CAI_DTLB, 0x5b, 0xff, 64,4 * 1024, "64 4K/4M entries"), \ +__CI_TBL(CAI_DTLB, 0x5c, 0xff, 64,4 * 1024, "128 4K/4M entries"),\ +__CI_TBL(CAI_DTLB, 0x5d, 0xff, 64,4 * 1024, "256 4K/4M entries"),\ __CI_TBL(CAI_ITLB, 0x61, 0xff, 48,4 * 1024, NULL), \ __CI_TBL(CAI_L1_1GBDTLB,0x63, 4, 4,1024*1024 * 1024, NULL), \ __CI_TBL(CAI_DTLB, 0x64,4,512,4 * 1024, NULL), \ __CI_TBL(CAI_ITLB, 0x6a,8, 64,4 * 1024, NULL), \ __CI_TBL(CAI_DTLB, 0x6b,8,256,4 * 1024, NULL), \ -__CI_TBL(CAI_L2_DTLB2, 0x6c,8,128, 0, "2M/4M: 128 entries"),\ +__CI_TBL(CAI_L2_DTLB2, 0x6c,8,128, 0, "128 2M/4M entries"),\ __CI_TBL(CAI_L1_1GBDTLB,0x6d,0xff, 16,1024*1024 * 1024, NULL), \ -__CI_TBL(CAI_ITLB2,0x76, 0xff, 8, 4 * 1024 * 1024, "2M/4M: 8 entries"), \ +__CI_TBL(CAI_ITLB2,0x76, 0xff, 8, 4 * 1024 * 1024, "8 2M/4M entries"), \ __CI_TBL(CAI_DTLB, 0xa0, 0xff, 32,4 * 1024, NULL), \ __CI_TBL(CAI_ITLB, 0xb0,4,128,4 * 1024, NULL), \ -__CI_TBL(CAI_ITLB2,0xb1,4, 64, 0, "8 2M/4 4M entries"), \ +__CI_TBL(CAI_ITLB2,0xb1,4, 64, 0, "8 2M & 4 4M entries"), \ __CI_TBL(CAI_ITLB, 0xb2,4, 64,4 * 1024, NULL), \ __CI_TBL(CAI_DTLB, 0xb3,4,128,4 * 1024, NULL), \ __CI_TBL(CAI_DTLB, 0xb4,4,256,4 * 1024, NULL), \ __CI_TBL(CAI_ITLB, 0xb5,8, 64,4 * 1024, NULL), \ __CI_TBL(CAI_ITLB, 0xb6,8,128,4 * 1024, NULL), \ __CI_TBL(CAI_DTLB, 0xba,4, 64,4 * 1024, NULL), \ -__CI_TBL(CAI_DTLB2,0xc0,4, 8,4 * 1024, "4K/4M: 8 entries"), \ -__CI_TBL(CAI_L2_STLB2, 0xc1,8,1024, 4 * 1024, "4K/2M: 1024 entries"), \ -__CI_TBL(CAI_DTLB2,0xc2,4, 16,4 * 1024, "4K/2M: 16 entries"), \ +__CI_TBL(CAI_DTLB2,0xc0,4, 8,4 * 1024, "8 4K/4M entries"), \ +__CI_TBL(CAI_L2_STLB2, 0xc1,8,1024, 4 * 1024, "1024 4K/2M entries"), \ +__CI_TBL(CAI_DTLB2,0xc2,4, 16,4 * 1024, "16 4K/2M entries"), \ __CI_TBL(CAI_L2_STLB, 0xc3,6,1536, 4 * 1024, NULL), \ -__CI_TBL(CAI_DTLB2,
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Thu Dec 9 14:33:19 UTC 2021 Modified Files: src/sys/arch/x86/include: cacheinfo.h Log Message: Print TLB message consistently to improve readability. Example: cpu0: L2 cache: 256KB 64B/line 4-way cpu0: L3 cache: 4MB 64B/line 16-way cpu0: 64B prefetching -cpu0: ITLB: 64 4KB entries 8-way, 2M/4M: 8 entries +cpu0: ITLB: 64 4KB entries 8-way, 8 2M/4M entries cpu0: DTLB: 64 4KB entries 4-way, 4 1GB entries 4-way cpu0: L2 STLB: 1536 4KB entries 6-way cpu0: Initial APIC ID 0 To generate a diff of this commit: cvs rdiff -u -r1.30 -r1.31 src/sys/arch/x86/include/cacheinfo.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Thu Sep 30 15:54:55 UTC 2021 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Print CPUID_PBE (Pending Break Enable) with "PBE". To generate a diff of this commit: cvs rdiff -u -r1.177 -r1.178 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Thu Sep 30 15:54:55 UTC 2021 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Print CPUID_PBE (Pending Break Enable) with "PBE". To generate a diff of this commit: cvs rdiff -u -r1.177 -r1.178 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.177 src/sys/arch/x86/include/specialreg.h:1.178 --- src/sys/arch/x86/include/specialreg.h:1.177 Sat Jul 10 17:08:37 2021 +++ src/sys/arch/x86/include/specialreg.h Thu Sep 30 15:54:55 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.177 2021/07/10 17:08:37 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.178 2021/09/30 15:54:55 msaitoh Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -213,7 +213,7 @@ "\21" "PAT" "\22" "PSE36" "\23" "PN" "\24" "CLFLUSH" \ "\25" "B20" "\26" "DS" "\27" "ACPI" "\30" "MMX" \ "\31" "FXSR" "\32" "SSE" "\33" "SSE2" "\34" "SS" \ - "\35" "HTT" "\36" "TM" "\37" "IA64" "\40" "SBF" + "\35" "HTT" "\36" "TM" "\37" "IA64" "\40" "PBE" /* Blacklists of CPUID flags - used to mask certain features */ #ifdef XENPV
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Sun Nov 17 15:31:05 UTC 2019 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add the following bit definitions from the latest Intel SDM: - CET shadow stack - Fast Short REP MOV - Hybrid part - CET Indirect Branch Tracking To generate a diff of this commit: cvs rdiff -u -r1.157 -r1.158 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Sun Nov 17 15:31:05 UTC 2019 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add the following bit definitions from the latest Intel SDM: - CET shadow stack - Fast Short REP MOV - Hybrid part - CET Indirect Branch Tracking To generate a diff of this commit: cvs rdiff -u -r1.157 -r1.158 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.157 src/sys/arch/x86/include/specialreg.h:1.158 --- src/sys/arch/x86/include/specialreg.h:1.157 Tue Nov 12 18:00:13 2019 +++ src/sys/arch/x86/include/specialreg.h Sun Nov 17 15:31:05 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.157 2019/11/12 18:00:13 maxv Exp $ */ +/* $NetBSD: specialreg.h,v 1.158 2019/11/17 15:31:05 msaitoh Exp $ */ /* * Copyright (c) 2014-2019 The NetBSD Foundation, Inc. @@ -447,6 +447,7 @@ #define CPUID_SEF_OSPKE __BIT(4) /* OS has set CR4.PKE to ena. protec. keys */ #define CPUID_SEF_WAITPKG __BIT(5) /* TPAUSE,UMONITOR,UMWAIT */ #define CPUID_SEF_AVX512_VBMI2 __BIT(6) /* AVX-512 Vector Byte Manipulation 2 */ +#define CPUID_SEF_CET_SS __BIT(7) /* CET shadow stack */ #define CPUID_SEF_GFNI __BIT(8) #define CPUID_SEF_VAES __BIT(9) #define CPUID_SEF_VPCLMULQDQ __BIT(10) @@ -462,7 +463,7 @@ #define CPUID_SEF_FLAGS1 "\177\20" \ "b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0" \ - "b\4OSPKE\0" "b\5WAITPKG\0" "b\6AVX512_VBMI2\0" \ + "b\4OSPKE\0" "b\5WAITPKG\0" "b\6AVX512_VBMI2\0" "b\7CET_SS\0" \ "b\10GFNI\0" "b\11VAES\0" "b\12VPCLMULQDQ\0" "b\13AVX512_VNNI\0"\ "b\14AVX512_BITALG\0" "b\16AVX512_VPOPCNTDQ\0" \ "f\21\5MAWAU\0" \ @@ -473,8 +474,11 @@ /* %edx */ #define CPUID_SEF_AVX512_4VNNIW __BIT(2) #define CPUID_SEF_AVX512_4FMAPS __BIT(3) +#define CPUID_SEF_FSREP_MOV __BIT(4) /* Fast Short REP MOV */ #define CPUID_SEF_MD_CLEAR __BIT(10) #define CPUID_SEF_TSX_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */ +#define CPUID_SEF_HYBRID __BIT(15) /* Hybrid part */ +#define CPUID_SEF_CET_IBT __BIT(20) /* CET Indirect Branch Tracking */ #define CPUID_SEF_IBRS __BIT(26) /* IBRS / IBPB Speculation Control */ #define CPUID_SEF_STIBP __BIT(27) /* STIBP Speculation Control */ #define CPUID_SEF_L1D_FLUSH __BIT(28) /* IA32_FLUSH_CMD MSR */ @@ -484,8 +488,10 @@ #define CPUID_SEF_FLAGS2 "\20" \ "\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \ + "\5" "FSREP_MOV" \ "\13" "MD_CLEAR" \ - "\16" "TSX_FORCE_ABORT"\ + "\16" "TSX_FORCE_ABORT" "\20" "HYBRID" \ + "\25" "CET_IBT" \ "\33" "IBRS" "\34" "STIBP" \ "\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\37CORE_CAP" "\40" "SSBD"
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: msaitoh
Date: Wed Oct 30 05:35:36 UTC 2019
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
- GMET is not bit 11 but 17.
- Add unknown CPUID Fn8000_000a %edx bit 20.
To generate a diff of this commit:
cvs rdiff -u -r1.155 -r1.156 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.155 src/sys/arch/x86/include/specialreg.h:1.156
--- src/sys/arch/x86/include/specialreg.h:1.155 Tue Oct 8 03:16:21 2019
+++ src/sys/arch/x86/include/specialreg.h Wed Oct 30 05:35:36 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.155 2019/10/08 03:16:21 msaitoh Exp $ */
+/* $NetBSD: specialreg.h,v 1.156 2019/10/30 05:35:36 msaitoh Exp $ */
/*
* Copyright (c) 2014-2019 The NetBSD Foundation, Inc.
@@ -755,19 +755,20 @@
#define CPUID_AMD_SVM_FlushByASID 0x0040
#define CPUID_AMD_SVM_DecodeAssist 0x0080
#define CPUID_AMD_SVM_PauseFilter 0x0400
-#define CPUID_AMD_SVM_GMET 0x0800
#define CPUID_AMD_SVM_PFThreshold 0x1000 /* PAUSE filter threshold */
#define CPUID_AMD_SVM_AVIC 0x2000 /* AMD Virtual intr. ctrl */
#define CPUID_AMD_SVM_V_VMSAVE_VMLOAD 0x8000 /* Virtual VM{SAVE/LOAD} */
#define CPUID_AMD_SVM_vGIF 0x0001 /* Virtualized GIF */
+#define CPUID_AMD_SVM_GMET 0x0002
#define CPUID_AMD_SVM_FLAGS "\20" \
"\1" "NP" "\2" "LbrVirt" "\3" "SVML" "\4" "NRIPS" \
"\5" "TSCRate" "\6" "VMCBCleanBits" \
"\7" "FlushByASID" "\10" "DecodeAssist" \
- "\11" "B08" "\12" "B09" "\13" "PauseFilter" "\14" "GMET" \
+ "\11" "B08" "\12" "B09" "\13" "PauseFilter" "\14" "B11" \
"\15" "PFThreshold" "\16" "AVIC" "\17" "B14" \
"\20" "V_VMSAVE_VMLOAD" \
- "\21" "VGIF"
+ "\21" "VGIF" "\22" "GMET" \
+ "\25" "B20"
/*
* AMD Fn8000_0001d Cache Topology Information.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Wed Oct 30 05:35:36 UTC 2019 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: - GMET is not bit 11 but 17. - Add unknown CPUID Fn8000_000a %edx bit 20. To generate a diff of this commit: cvs rdiff -u -r1.155 -r1.156 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: manu Date: Fri Oct 18 00:54:48 UTC 2019 Modified Files: src/sys/arch/x86/include: efi.h Log Message: Add UEFI boot services and I/O method protoypes To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/sys/arch/x86/include/efi.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: manu
Date: Fri Oct 18 00:54:48 UTC 2019
Modified Files:
src/sys/arch/x86/include: efi.h
Log Message:
Add UEFI boot services and I/O method protoypes
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/x86/include/efi.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/efi.h
diff -u src/sys/arch/x86/include/efi.h:1.8 src/sys/arch/x86/include/efi.h:1.9
--- src/sys/arch/x86/include/efi.h:1.8 Sun Oct 22 00:59:28 2017
+++ src/sys/arch/x86/include/efi.h Fri Oct 18 00:54:48 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: efi.h,v 1.8 2017/10/22 00:59:28 maya Exp $ */
+/* $NetBSD: efi.h,v 1.9 2019/10/18 00:54:48 manu Exp $ */
/*-
* Copyright (c) 2004 Marcel Moolenaar
@@ -63,6 +63,12 @@ enum efi_reset {
typedef uint16_t efi_char;
typedef unsigned long efi_status;
+#if defined(__amd64__)
+typedef uint64_t uintn;
+#elif defined(__i386__)
+typedef uint32_t uintn;
+#endif
+
struct efi_cfgtbl {
struct uuid ct_uuid;
void *ct_data;
@@ -149,6 +155,133 @@ struct efi_rt {
efi_char *);
};
+typedef uintn efi_tpl;
+typedef void *efi_event;
+typedef void (*efi_event_notify)(efi_event, void *);
+typedef void *efi_handle;
+typedef struct {
+ uint8_t type;
+ uint8_t subtype;
+ uint8_t ldnegth[2];
+} efi_device_path;
+
+struct efi_bs {
+ struct efi_tblhdr bs_hdr;
+#define EFI_BS_SIG 0x56524553544f4f42UL
+ efi_tpl (*bs_raisetpl)(efi_tpl);
+ void(*bs_restoretpl)(efi_tpl);
+ efi_status (*bs_allocatepages)(uint32_t, uint32_t,
+ uintn, paddr_t *);
+ efi_status (*bs_freepages)(paddr_t, uintn);
+ efi_status (*bs_getmemorymap)(uintn *, struct efi_md *,
+ uintn *, uintn *, uint32_t *);
+ efi_status (*bs_allocatepool)(uint32_t, uintn, void **);
+ efi_status (*bs_freepool)(void *);
+ efi_status (*bs_createevent)(uint32_t, efi_tpl, efi_event_notify,
+ void *, efi_event *);
+ efi_status (*bs_settimer)(efi_event, uint32_t, uint64_t);
+ efi_status (*bs_waitforevent)(uintn, efi_event *, uintn *);
+ efi_status (*bs_signalevent)(efi_event);
+ efi_status (*bs_closeevent)(efi_event);
+ efi_status (*bs_checkevent)(efi_event);
+ efi_status (*bs_installprotocolinterface)(efi_handle *,
+ struct uuid *, uint32_t, void *);
+ efi_status (*bs_reinstallprotocolinterface)(efi_handle *,
+ struct uuid *, void *, void *);
+ efi_status (*bs_uninstallprotocolinterface)(efi_handle *,
+ struct uuid *, void *);
+ efi_status (*bs_handleprotocol)(efi_handle,
+ struct uuid *, void **);
+ efi_status (*bs_pchandleprotocol)(efi_handle,
+ struct uuid *, void **);
+ efi_status (*bs_registerprotocolnotify)(struct uuid *, efi_event,
+ void **);
+ efi_status (*bs_locatehandle)(uint32_t, struct uuid *, void *,
+ uintn *, efi_handle *);
+ efi_status (*bs_locatedevicepath)(struct uuid *, efi_device_path **,
+ efi_handle *);
+ efi_status (*bs_installconfigurationtable)(struct uuid *, void *);
+ efi_status (*bs_loadimage)(uint8_t, efi_handle, efi_device_path *,
+ void *, uintn, efi_handle *);
+ efi_status (*bs_startimage)(efi_handle, uintn *, efi_char **);
+ efi_status (*bs_exit)(efi_handle, efi_status, uintn, efi_char *);
+ efi_status (*bs_unloadimage)(efi_handle);
+ efi_status (*bs_exitbootservices)(efi_handle, uintn);
+ efi_status (*bs_getnextmonotoniccount)(uint64_t *);
+ efi_status (*bs_stall)(uintn);
+ efi_status (*bs_setwatchdogtimer)(uintn, uint64_t,
+ uintn, efi_char *);
+ efi_status (*bs_connectcontroller)(efi_handle, efi_handle *,
+ efi_device_path *, uint8_t);
+ efi_status (*bs_disconnectcontroller)(efi_handle, efi_handle,
+ efi_handle);
+ efi_status (*bs_openprotocol)(efi_handle, struct uuid *, void **,
+ efi_handle, efi_handle, uint32_t);
+ efi_status (*bs_closeprotocol)(efi_handle, struct uuid *,
+ efi_handle, efi_handle);
+ efi_status (*bs_openprotocolinformation)(efi_handle, efi_handle,
+ uint32_t, uint32_t);
+ efi_status (*bs_protocolsperhandle)(efi_handle,
+ struct uuid ***, uintn *);
+ efi_status (*bs_locatehandlebuffer)(uint32_t, struct uuid *,
+ void *, uintn *, efi_handle **);
+ efi_status (*bs_locateprotocol)(struct uuid *, void *, void **);
+ efi_status (*bs_installmultipleprotocolinterfaces)(efi_handle *,
+ ...);
+ efi_status (*bs_uninstallmultipleprotocolinterfaces)(efi_handle,
+ ...);
+ efi_status (*bs_calculatecrc32)(void *, uintn, uint32_t *);
+ efi_status (*bs_copyme
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: maxv Date: Wed Oct 9 17:28:46 UTC 2019 Modified Files: src/sys/arch/x86/include: pte.h Log Message: Add new bits. To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/x86/include/pte.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/pte.h diff -u src/sys/arch/x86/include/pte.h:1.2 src/sys/arch/x86/include/pte.h:1.3 --- src/sys/arch/x86/include/pte.h:1.2 Sat Oct 5 07:30:03 2019 +++ src/sys/arch/x86/include/pte.h Wed Oct 9 17:28:46 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: pte.h,v 1.2 2019/10/05 07:30:03 maxv Exp $ */ +/* $NetBSD: pte.h,v 1.3 2019/10/09 17:28:46 maxv Exp $ */ /* * Copyright (c) 2010 The NetBSD Foundation, Inc. @@ -39,12 +39,14 @@ #define PGC_UC (PTE_PWT | PTE_PCD) /* hard UC */ /* - * page protection exception bits + * Page protection exception bits */ - -#define PGEX_P 0x01 /* protection violation (vs. no mapping) */ -#define PGEX_W 0x02 /* exception during a write cycle */ -#define PGEX_U 0x04 /* exception while in user mode (upl) */ -#define PGEX_X 0x10 /* exception during instruction fetch */ +#define PGEX_P 0x0001 /* the page was present */ +#define PGEX_W 0x0002 /* exception during a write cycle */ +#define PGEX_U 0x0004 /* exception while in user mode */ +#define PGEX_RSVD 0x0008 /* a reserved bit was set in the page tables */ +#define PGEX_X 0x0010 /* exception during instruction fetch */ +#define PGEX_PK 0x0020 /* access disallowed by protection key */ +#define PGEX_SGX 0x8000 /* violation of sgx-specific access rights */ #endif /* _X86_PTE_H */
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: maxv Date: Wed Oct 9 17:28:46 UTC 2019 Modified Files: src/sys/arch/x86/include: pte.h Log Message: Add new bits. To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/x86/include/pte.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Tue Oct 8 03:16:21 UTC 2019 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Fix AMD Fn8000_0001f %eax bit 0's name. To generate a diff of this commit: cvs rdiff -u -r1.154 -r1.155 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.154 src/sys/arch/x86/include/specialreg.h:1.155 --- src/sys/arch/x86/include/specialreg.h:1.154 Thu Oct 3 15:21:44 2019 +++ src/sys/arch/x86/include/specialreg.h Tue Oct 8 03:16:21 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.154 2019/10/03 15:21:44 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.155 2019/10/08 03:16:21 msaitoh Exp $ */ /* * Copyright (c) 2014-2019 The NetBSD Foundation, Inc. @@ -792,7 +792,7 @@ #define CPUID_AMD_ENCMEM_VTE __BIT(16) /* Virtual Transparent Encryption */ #define CPUID_AMD_ENCMEM_FLAGS "\20" \ - "\1" "NP" "\2" "SEV" "\3" "PageFlushMsr" "\4" "SEV-ES" \ + "\1" "SME" "\2" "SEV" "\3" "PageFlushMsr" "\4" "SEV-ES" \ "\21" "VTE" /*
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Tue Oct 8 03:16:21 UTC 2019 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Fix AMD Fn8000_0001f %eax bit 0's name. To generate a diff of this commit: cvs rdiff -u -r1.154 -r1.155 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: maxv Date: Sat Oct 5 07:30:03 UTC 2019 Modified Files: src/sys/arch/x86/include: pmap.h pte.h Log Message: Switch to the new PTE naming. No binary diff (tested with MKREPRO). To generate a diff of this commit: cvs rdiff -u -r1.102 -r1.103 src/sys/arch/x86/include/pmap.h cvs rdiff -u -r1.1 -r1.2 src/sys/arch/x86/include/pte.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: maxv
Date: Sat Oct 5 07:30:03 UTC 2019
Modified Files:
src/sys/arch/x86/include: pmap.h pte.h
Log Message:
Switch to the new PTE naming. No binary diff (tested with MKREPRO).
To generate a diff of this commit:
cvs rdiff -u -r1.102 -r1.103 src/sys/arch/x86/include/pmap.h
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/x86/include/pte.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/pmap.h
diff -u src/sys/arch/x86/include/pmap.h:1.102 src/sys/arch/x86/include/pmap.h:1.103
--- src/sys/arch/x86/include/pmap.h:1.102 Wed Aug 7 06:23:48 2019
+++ src/sys/arch/x86/include/pmap.h Sat Oct 5 07:30:03 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.h,v 1.102 2019/08/07 06:23:48 maxv Exp $ */
+/* $NetBSD: pmap.h,v 1.103 2019/10/05 07:30:03 maxv Exp $ */
/*
* Copyright (c) 1997 Charles D. Cranor and Washington University.
@@ -315,8 +315,8 @@ struct pmap {
*/
extern u_long PDPpaddr;
-extern pd_entry_t pmap_pg_g; /* do we support PG_G? */
-extern pd_entry_t pmap_pg_nx; /* do we support PG_NX? */
+extern pd_entry_t pmap_pg_g; /* do we support PTE_G? */
+extern pd_entry_t pmap_pg_nx; /* do we support PTE_NX? */
extern int pmap_largepages;
extern long nkptp[PTP_LEVELS];
@@ -526,7 +526,7 @@ kvtopte(vaddr_t va)
KASSERT(va >= VM_MIN_KERNEL_ADDRESS);
pde = L2_BASE + pl2_i(va);
- if (*pde & PG_PS)
+ if (*pde & PTE_PS)
return ((pt_entry_t *)pde);
return (PTE_BASE + pl1_i(va));
@@ -560,7 +560,7 @@ xpmap_ptetomach(pt_entry_t *pte)
va = ((va & XPTE_MASK) >> XPTE_SHIFT) | (vaddr_t) PTE_BASE;
up_pte = (pt_entry_t *) va;
- return (paddr_t) (((*up_pte) & PG_FRAME) + (((vaddr_t) pte) & (~PG_FRAME & ~VA_SIGN_MASK)));
+ return (paddr_t) (((*up_pte) & PTE_FRAME) + (((vaddr_t) pte) & (~PTE_FRAME & ~VA_SIGN_MASK)));
}
/* Xen helpers to change bits of a pte */
Index: src/sys/arch/x86/include/pte.h
diff -u src/sys/arch/x86/include/pte.h:1.1 src/sys/arch/x86/include/pte.h:1.2
--- src/sys/arch/x86/include/pte.h:1.1 Tue Jul 6 20:50:35 2010
+++ src/sys/arch/x86/include/pte.h Sat Oct 5 07:30:03 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: pte.h,v 1.1 2010/07/06 20:50:35 cegger Exp $ */
+/* $NetBSD: pte.h,v 1.2 2019/10/05 07:30:03 maxv Exp $ */
/*
* Copyright (c) 2010 The NetBSD Foundation, Inc.
@@ -33,10 +33,10 @@
#define _X86_PTE_H
/* Cacheability bits when we are using PAT */
-#define PGC_WB 0 /* The default */
-#define PGC_WC PG_WT /* WT and CD is WC */
-#define PGC_UCMINUS PG_N/* UC but mtrr can override */
-#define PGC_UC (PG_WT | PG_N) /* hard UC */
+#define PGC_WB 0 /* The default */
+#define PGC_WC PTE_PWT /* WT and CD is WC */
+#define PGC_UCMINUS PTE_PCD /* UC but mtrr can override */
+#define PGC_UC (PTE_PWT | PTE_PCD) /* hard UC */
/*
* page protection exception bits
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Thu Sep 26 06:42:53 UTC 2019 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Define CPUID_CAPEX_FLAGS's bit 10 correctly. To generate a diff of this commit: cvs rdiff -u -r1.152 -r1.153 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Thu Sep 26 06:42:53 UTC 2019 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Define CPUID_CAPEX_FLAGS's bit 10 correctly. To generate a diff of this commit: cvs rdiff -u -r1.152 -r1.153 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.152 src/sys/arch/x86/include/specialreg.h:1.153 --- src/sys/arch/x86/include/specialreg.h:1.152 Mon Sep 9 05:28:32 2019 +++ src/sys/arch/x86/include/specialreg.h Thu Sep 26 06:42:52 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.152 2019/09/09 05:28:32 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.153 2019/09/26 06:42:52 msaitoh Exp $ */ /* * Copyright (c) 2014-2019 The NetBSD Foundation, Inc. @@ -740,7 +740,7 @@ #define CPUID_CAPEX_FLAGS "\20" \ "\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" \ "\5RDPRU" "\7B6" \ - "\11MCOMMIT" "\12WBNOINVD" "\12B10" \ + "\11MCOMMIT" "\12WBNOINVD" "\13B10" \ "\15IBPB" "\16B13" "\17IBRS" "\20STIBP" \ "\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS" "\24B19" \ "\31SSBD" "\32VIRT_SSBD" "\33SSB_NO"
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Mon Sep 9 05:28:32 UTC 2019 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add MCOMMIT instruction. To generate a diff of this commit: cvs rdiff -u -r1.151 -r1.152 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Mon Sep 9 05:28:32 UTC 2019 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add MCOMMIT instruction. To generate a diff of this commit: cvs rdiff -u -r1.151 -r1.152 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.151 src/sys/arch/x86/include/specialreg.h:1.152 --- src/sys/arch/x86/include/specialreg.h:1.151 Fri Aug 30 13:11:28 2019 +++ src/sys/arch/x86/include/specialreg.h Mon Sep 9 05:28:32 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.151 2019/08/30 13:11:28 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.152 2019/09/09 05:28:32 msaitoh Exp $ */ /* * Copyright (c) 2014-2019 The NetBSD Foundation, Inc. @@ -725,6 +725,7 @@ #define CPUID_CAPEX_IRPERF __BIT(1) /* InstRetCntMsr */ #define CPUID_CAPEX_XSAVEERPTR __BIT(2) /* RstrFpErrPtrs by XRSTOR */ #define CPUID_CAPEX_RDPRU __BIT(4) /* RDPRU instruction */ +#define CPUID_CAPEX_MCOMMIT __BIT(8) /* MCOMMIT instruction */ #define CPUID_CAPEX_WBNOINVD __BIT(9) /* WBNOINVD instruction */ #define CPUID_CAPEX_IBPB __BIT(12) /* Speculation Control IBPB */ #define CPUID_CAPEX_IBRS __BIT(14) /* Speculation Control IBRS */ @@ -739,7 +740,7 @@ #define CPUID_CAPEX_FLAGS "\20" \ "\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" \ "\5RDPRU" "\7B6" \ - "\11B8" "\12WBNOINVD" "\12B10" \ + "\11MCOMMIT" "\12WBNOINVD" "\12B10" \ "\15IBPB" "\16B13" "\17IBRS" "\20STIBP" \ "\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS" "\24B19" \ "\31SSBD" "\32VIRT_SSBD" "\33SSB_NO"
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: maxv Date: Sat Sep 7 11:09:03 UTC 2019 Modified Files: src/sys/arch/x86/include: cpufunc.h Log Message: Add a memory barrier on wrmsr, because some MSRs control memory access rights (we don't use them though). Also add barriers on fninit and clts for safety. To generate a diff of this commit: cvs rdiff -u -r1.34 -r1.35 src/sys/arch/x86/include/cpufunc.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: maxv
Date: Sat Sep 7 11:09:03 UTC 2019
Modified Files:
src/sys/arch/x86/include: cpufunc.h
Log Message:
Add a memory barrier on wrmsr, because some MSRs control memory access
rights (we don't use them though). Also add barriers on fninit and clts
for safety.
To generate a diff of this commit:
cvs rdiff -u -r1.34 -r1.35 src/sys/arch/x86/include/cpufunc.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cpufunc.h
diff -u src/sys/arch/x86/include/cpufunc.h:1.34 src/sys/arch/x86/include/cpufunc.h:1.35
--- src/sys/arch/x86/include/cpufunc.h:1.34 Fri Jul 5 17:08:55 2019
+++ src/sys/arch/x86/include/cpufunc.h Sat Sep 7 11:09:03 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.h,v 1.34 2019/07/05 17:08:55 maxv Exp $ */
+/* $NetBSD: cpufunc.h,v 1.35 2019/09/07 11:09:03 maxv Exp $ */
/*
* Copyright (c) 1998, 2007, 2019 The NetBSD Foundation, Inc.
@@ -271,7 +271,7 @@ union savefpu;
static inline void
fninit(void)
{
- __asm volatile ("fninit");
+ __asm volatile ("fninit" ::: "memory");
}
static inline void
@@ -303,7 +303,7 @@ fnstsw(uint16_t *val)
static inline void
clts(void)
{
- __asm volatile ("clts");
+ __asm volatile ("clts" ::: "memory");
}
void stts(void);
@@ -433,6 +433,7 @@ wrmsr(u_int msr, uint64_t val)
"wrmsr"
:
: "a" (low), "d" (high), "c" (msr)
+ : "memory"
);
}
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Fri Aug 30 13:11:28 UTC 2019 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add definitions of AMD's CPUID Fn8000_0008 %ebx. To generate a diff of this commit: cvs rdiff -u -r1.150 -r1.151 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.150 src/sys/arch/x86/include/specialreg.h:1.151 --- src/sys/arch/x86/include/specialreg.h:1.150 Fri Jul 26 10:03:40 2019 +++ src/sys/arch/x86/include/specialreg.h Fri Aug 30 13:11:28 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.150 2019/07/26 10:03:40 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.151 2019/08/30 13:11:28 msaitoh Exp $ */ /* * Copyright (c) 2014-2019 The NetBSD Foundation, Inc. @@ -712,6 +712,38 @@ "\11" "TSC" "\12" "CPB" "\13" "EffFreq" "\14" "PROCFI" \ "\15" "PROCPR" "\16" "CONNSTBY" "\17" "RAPL" +/* + * AMD Processor Capacity Parameters and Extended Features + * CPUID Fn8000_0008 + * %eax: Long Mode Size Identifiers + * %ebx: Extended Feature Identifiers + * %ecx: Size Identifiers + */ + +/* %ebx */ +#define CPUID_CAPEX_CLZERO __BIT(0) /* CLZERO instruction */ +#define CPUID_CAPEX_IRPERF __BIT(1) /* InstRetCntMsr */ +#define CPUID_CAPEX_XSAVEERPTR __BIT(2) /* RstrFpErrPtrs by XRSTOR */ +#define CPUID_CAPEX_RDPRU __BIT(4) /* RDPRU instruction */ +#define CPUID_CAPEX_WBNOINVD __BIT(9) /* WBNOINVD instruction */ +#define CPUID_CAPEX_IBPB __BIT(12) /* Speculation Control IBPB */ +#define CPUID_CAPEX_IBRS __BIT(14) /* Speculation Control IBRS */ +#define CPUID_CAPEX_STIBP __BIT(15) /* Speculation Control STIBP */ +#define CPUID_CAPEX_IBRS_ALWAYSON __BIT(16) /* IBRS always on mode */ +#define CPUID_CAPEX_STIBP_ALWAYSON __BIT(17) /* STIBP always on mode */ +#define CPUID_CAPEX_PREFER_IBRS __BIT(18) /* IBRS preferred */ +#define CPUID_CAPEX_SSBD __BIT(24) /* Speculation Control SSBD */ +#define CPUID_CAPEX_VIRT_SSBD __BIT(25) /* Virt Spec Control SSBD */ +#define CPUID_CAPEX_SSB_NO __BIT(26) /* SSBD not required */ + +#define CPUID_CAPEX_FLAGS "\20" \ + "\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" \ + "\5RDPRU" "\7B6" \ + "\11B8" "\12WBNOINVD" "\12B10" \ + "\15IBPB" "\16B13" "\17IBRS" "\20STIBP" \ + "\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS" "\24B19" \ + "\31SSBD" "\32VIRT_SSBD" "\33SSB_NO" + /* AMD Fn800a %edx features (SVM features) */ #define CPUID_AMD_SVM_NP 0x0001 #define CPUID_AMD_SVM_LbrVirt 0x0002
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Fri Aug 30 13:11:28 UTC 2019 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add definitions of AMD's CPUID Fn8000_0008 %ebx. To generate a diff of this commit: cvs rdiff -u -r1.150 -r1.151 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Wed Jul 24 10:45:47 UTC 2019 Modified Files: src/sys/arch/x86/include: cacheinfo.h Log Message: It seems that AMD zen2's CPUID 0x8006 leaf's spec has changed. The EDX register's acsociativity field has 9. In the latest available document, it's a reserved value. I have no access to zen2's document, but many websites say that the acsociativity is 16. Add it. To generate a diff of this commit: cvs rdiff -u -r1.26 -r1.27 src/sys/arch/x86/include/cacheinfo.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/cacheinfo.h diff -u src/sys/arch/x86/include/cacheinfo.h:1.26 src/sys/arch/x86/include/cacheinfo.h:1.27 --- src/sys/arch/x86/include/cacheinfo.h:1.26 Mon Mar 12 07:35:45 2018 +++ src/sys/arch/x86/include/cacheinfo.h Wed Jul 24 10:45:47 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: cacheinfo.h,v 1.26 2018/03/12 07:35:45 msaitoh Exp $ */ +/* $NetBSD: cacheinfo.h,v 1.27 2019/07/24 10:45:47 msaitoh Exp $ */ #ifndef _X86_CACHEINFO_H_ #define _X86_CACHEINFO_H_ @@ -362,6 +362,7 @@ __CI_TBL(0, 0x02,2, 0, 0, NULL), \ __CI_TBL(0, 0x04,4, 0, 0, NULL), \ __CI_TBL(0, 0x06,8, 0, 0, NULL), \ __CI_TBL(0, 0x08, 16, 0, 0, NULL), \ +__CI_TBL(0, 0x09, 16, 0, 0, NULL), \ __CI_TBL(0, 0x0a, 32, 0, 0, NULL), \ __CI_TBL(0, 0x0b, 48, 0, 0, NULL), \ __CI_TBL(0, 0x0c, 64, 0, 0, NULL), \
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Wed Jul 24 10:45:47 UTC 2019 Modified Files: src/sys/arch/x86/include: cacheinfo.h Log Message: It seems that AMD zen2's CPUID 0x8006 leaf's spec has changed. The EDX register's acsociativity field has 9. In the latest available document, it's a reserved value. I have no access to zen2's document, but many websites say that the acsociativity is 16. Add it. To generate a diff of this commit: cvs rdiff -u -r1.26 -r1.27 src/sys/arch/x86/include/cacheinfo.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Sat Jul 13 09:28:03 UTC 2019 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Define some new bits of CPUID Fn8000_0007 %edx AMD Advanced Power Management leaf. To generate a diff of this commit: cvs rdiff -u -r1.148 -r1.149 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Sat Jul 13 09:28:03 UTC 2019 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Define some new bits of CPUID Fn8000_0007 %edx AMD Advanced Power Management leaf. To generate a diff of this commit: cvs rdiff -u -r1.148 -r1.149 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.148 src/sys/arch/x86/include/specialreg.h:1.149 --- src/sys/arch/x86/include/specialreg.h:1.148 Wed Jun 26 12:29:00 2019 +++ src/sys/arch/x86/include/specialreg.h Sat Jul 13 09:28:03 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.148 2019/06/26 12:29:00 mgorny Exp $ */ +/* $NetBSD: specialreg.h,v 1.149 2019/07/13 09:28:03 msaitoh Exp $ */ /* * Copyright (c) 2014-2019 The NetBSD Foundation, Inc. @@ -701,12 +701,16 @@ #define CPUID_APM_TSC 0x0100 /* TSC invariant */ #define CPUID_APM_CPB 0x0200 /* Core performance boost */ #define CPUID_APM_EFF 0x0400 /* Effective Frequency (read-only) */ - -#define CPUID_APM_FLAGS "\20" \ - "\1" "TS" "\2" "FID" "\3" "VID" "\4" "TTP" \ - "\5" "HTC" "\6" "STC" "\7" "100" "\10" "HWP" \ - "\11" "TSC" "\12" "CPB" "\13" "EffFreq" "\14" "B11" \ - "\15" "B12" +#define CPUID_APM_PROCFI 0x0800 /* Proc Feedback Interface */ +#define CPUID_APM_PROCPR 0x1000 /* Proc Power Reporting */ +#define CPUID_APM_CONNSTBY 0x2000 /* Connected Standby */ +#define CPUID_APM_RAPL 0x4000 /* Running Average Power Limit */ + +#define CPUID_APM_FLAGS "\20" \ + "\1" "TS" "\2" "FID" "\3" "VID" "\4" "TTP" \ + "\5" "HTC" "\6" "STC" "\7" "100" "\10" "HWP" \ + "\11" "TSC" "\12" "CPB" "\13" "EffFreq" "\14" "PROCFI" \ + "\15" "PROCPR" "\16" "CONNSTBY" "\17" "RAPL" /* AMD Fn800a %edx features (SVM features) */ #define CPUID_AMD_SVM_NP 0x0001
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: nonaka
Date: Fri Jun 21 02:08:55 UTC 2019
Modified Files:
src/sys/arch/x86/include: bootinfo.h
Log Message:
PR/54147: Increase BOOTINFO_MAXSIZE to 16Kib.
Some systems require a larger bootinfo size for memory descriptors.
To generate a diff of this commit:
cvs rdiff -u -r1.29 -r1.30 src/sys/arch/x86/include/bootinfo.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/bootinfo.h
diff -u src/sys/arch/x86/include/bootinfo.h:1.29 src/sys/arch/x86/include/bootinfo.h:1.30
--- src/sys/arch/x86/include/bootinfo.h:1.29 Fri Apr 13 11:24:34 2018
+++ src/sys/arch/x86/include/bootinfo.h Fri Jun 21 02:08:55 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: bootinfo.h,v 1.29 2018/04/13 11:24:34 nonaka Exp $ */
+/* $NetBSD: bootinfo.h,v 1.30 2019/06/21 02:08:55 nonaka Exp $ */
/*
* Copyright (c) 1997
@@ -251,7 +251,7 @@ struct btinfo_efimemmap {
#ifdef _KERNEL
-#define BOOTINFO_MAXSIZE 8192
+#define BOOTINFO_MAXSIZE 16384
#ifndef _LOCORE
/*
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: nonaka Date: Fri Jun 21 02:08:55 UTC 2019 Modified Files: src/sys/arch/x86/include: bootinfo.h Log Message: PR/54147: Increase BOOTINFO_MAXSIZE to 16Kib. Some systems require a larger bootinfo size for memory descriptors. To generate a diff of this commit: cvs rdiff -u -r1.29 -r1.30 src/sys/arch/x86/include/bootinfo.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Thu Jun 13 15:10:27 UTC 2019 Modified Files: src/sys/arch/x86/include: i82489reg.h Log Message: Indent consistently. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.17 -r1.18 src/sys/arch/x86/include/i82489reg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/i82489reg.h diff -u src/sys/arch/x86/include/i82489reg.h:1.17 src/sys/arch/x86/include/i82489reg.h:1.18 --- src/sys/arch/x86/include/i82489reg.h:1.17 Thu Jun 13 07:44:27 2019 +++ src/sys/arch/x86/include/i82489reg.h Thu Jun 13 15:10:27 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: i82489reg.h,v 1.17 2019/06/13 07:44:27 msaitoh Exp $ */ +/* $NetBSD: i82489reg.h,v 1.18 2019/06/13 15:10:27 msaitoh Exp $ */ /*- * Copyright (c) 1998, 2008 The NetBSD Foundation, Inc. @@ -35,36 +35,36 @@ * "local" APIC. */ -#define LAPIC_ID 0x020 /* ID. (xAPIC: RW, x2APIC: RO) */ +#define LAPIC_ID 0x020 /* ID. (xAPIC: RW, x2APIC: RO) */ # define LAPIC_ID_MASK 0xff00 # define LAPIC_ID_SHIFT 24 -#define LAPIC_VERS 0x030 /* Version. RO */ +#define LAPIC_VERS 0x030 /* Version. RO */ # define LAPIC_VERSION_MASK 0x00ff # define LAPIC_VERSION_LVT_MASK 0x00ff # define LAPIC_VERSION_LVT_SHIFT 16 # define LAPIC_VERSION_DIRECTED_EOI 0x0100 # define LAPIC_VERSION_EXTAPIC_SPACE 0x8000 -#define LAPIC_TPRI 0x080 /* Task Prio. RW */ +#define LAPIC_TPRI 0x080 /* Task Prio. RW */ # define LAPIC_TPRI_MASK 0x00ff # define LAPIC_TPRI_INT_MASK 0x00f0 # define LAPIC_TPRI_SUB_MASK 0x000f -#define LAPIC_APRI 0x090 /* Arbitration prio (xAPIC: RO, x2APIC: NA) */ +#define LAPIC_APRI 0x090 /* Arbitration prio (xAPIC: RO, x2APIC: NA) */ # define LAPIC_APRI_MASK 0x00ff -#define LAPIC_PPRI 0x0a0 /* Processor prio. RO */ -#define LAPIC_EOI 0x0b0 /* End Int. W */ -#define LAPIC_RRR 0x0c0 /* Remote read (xAPIC: RO, x2APIC: NA) */ -#define LAPIC_LDR 0x0d0 /* Logical dest. (xAPIC: RW, x2APIC: RO) */ +#define LAPIC_PPRI 0x0a0 /* Processor prio. RO */ +#define LAPIC_EOI 0x0b0 /* End Int. W */ +#define LAPIC_RRR 0x0c0 /* Remote read (xAPIC: RO, x2APIC: NA) */ +#define LAPIC_LDR 0x0d0 /* Logical dest. (xAPIC: RW, x2APIC: RO) */ -#define LAPIC_DFR 0x0e0 /* Dest. format (xAPIC: RW, x2APIC: NA) */ +#define LAPIC_DFR 0x0e0 /* Dest. format (xAPIC: RW, x2APIC: NA) */ # define LAPIC_DFR_MASK 0xf000 # define LAPIC_DFR_FLAT 0xf000 # define LAPIC_DFR_CLUSTER 0x -#define LAPIC_SVR 0x0f0 /* Spurious intvec RW */ +#define LAPIC_SVR 0x0f0 /* Spurious intvec RW */ # define LAPIC_SVR_VECTOR_MASK 0x00ff # define LAPIC_SVR_VEC_FIX 0x000f # define LAPIC_SVR_VEC_PROG 0x00f0 @@ -74,14 +74,14 @@ # define LAPIC_SVR_FDIS 0x0200 # define LAPIC_SVR_EOI_BC_DIS 0x1000 -#define LAPIC_ISR 0x100 /* In-Service Status RO */ -#define LAPIC_TMR 0x180 /* Trigger Mode RO */ -#define LAPIC_IRR 0x200 /* Interrupt Req RO */ -#define LAPIC_ESR 0x280 /* Err status. RW */ +#define LAPIC_ISR 0x100 /* In-Service Status RO */ +#define LAPIC_TMR 0x180 /* Trigger Mode RO */ +#define LAPIC_IRR 0x200 /* Interrupt Req RO */ +#define LAPIC_ESR 0x280 /* Err status. RW */ -#define LAPIC_LVT_CMCI 0x2f0 /* Loc.vec (CMCI) RW */ +#define LAPIC_LVT_CMCI 0x2f0 /* Loc.vec (CMCI) RW */ -#define LAPIC_ICRLO 0x300 /* Int. cmd. (xAPIC: RW, x2APIC: RW64) */ +#define LAPIC_ICRLO 0x300 /* Int. cmd. (xAPIC: RW, x2APIC: RW64) */ # define LAPIC_DLMODE_MASK 0x0700 /* Delivery Mode */ # define LAPIC_DLMODE_FIXED 0x # define LAPIC_DLMODE_LOW 0x0100 /* N/A in x2APIC mode */ @@ -111,17 +111,17 @@ # define LAPIC_DEST_ALLINCL 0x0008 # define LAPIC_DEST_ALLEXCL 0x000c -#define LAPIC_ICRHI 0x310 /* Int. cmd. (xAPIC: RW, x2APIC: NA) */ +#define LAPIC_ICRHI 0x310 /* Int. cmd. (xAPIC: RW, x2APIC: NA) */ -#define LAPIC_LVTT 0x320 /* Loc.vec.(timer) RW */ +#define LAPIC_LVTT 0x320 /* Loc.vec.(timer) RW */ # define LAPIC_LVTT_VEC_MASK 0x00ff # define LAPIC_LVTT_DS 0x1000 # define LAPIC_LVTT_M 0x0001 # define LAPIC_LVTT_TM 0x0002 -#define LAPIC_TMINT 0x330 /* Loc.vec (Thermal) RW */ -#define LAPIC_PCINT 0x340 /* Loc.vec (Perf Mon) RW */ -#define LAPIC_LVINT0 0x350 /* Loc.vec (LINT0) RW */ +#define LAPIC_TMINT 0x330 /* Loc.vec (Thermal) RW */ +#define LAPIC_PCINT 0x340 /* Loc.vec (Perf Mon) RW */ +#define LAPIC_LVINT0 0x350 /* Loc.vec (LINT0) RW */ # define LAPIC_LVT_DM_MASK 0x0700 # define LAPIC_LVT_DM_FIXED 0x # define LAPIC_LVT_DM_SMI 0x0200 @@ -134,12 +134,12 @@ # define LAPIC_INP_POL 0x2000 # define LAPIC_PEND_SEND 0x1000 -#define LAPIC_LVINT1 0x360 /* Loc.vec (LINT1) RW */ -#define LAPIC_LVERR 0x370 /* Loc.vec (ERROR) RW */ -#define LAPIC_ICR_TIMER 0x380 /* Initial count RW */ -#define LAPIC_CCR_TIMER 0x390 /* Current count RO */ +#define LAPIC_LVINT1 0x360 /
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Thu Jun 13 15:10:27 UTC 2019 Modified Files: src/sys/arch/x86/include: i82489reg.h Log Message: Indent consistently. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.17 -r1.18 src/sys/arch/x86/include/i82489reg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Thu Jun 13 07:44:27 UTC 2019 Modified Files: src/sys/arch/x86/include: i82489reg.h Log Message: Modify LAPIC_LVT_CMCI's comment to be consistent with other LVT's. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.16 -r1.17 src/sys/arch/x86/include/i82489reg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/i82489reg.h diff -u src/sys/arch/x86/include/i82489reg.h:1.16 src/sys/arch/x86/include/i82489reg.h:1.17 --- src/sys/arch/x86/include/i82489reg.h:1.16 Fri Apr 28 01:23:58 2017 +++ src/sys/arch/x86/include/i82489reg.h Thu Jun 13 07:44:27 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: i82489reg.h,v 1.16 2017/04/28 01:23:58 nonaka Exp $ */ +/* $NetBSD: i82489reg.h,v 1.17 2019/06/13 07:44:27 msaitoh Exp $ */ /*- * Copyright (c) 1998, 2008 The NetBSD Foundation, Inc. @@ -79,7 +79,7 @@ #define LAPIC_IRR 0x200 /* Interrupt Req RO */ #define LAPIC_ESR 0x280 /* Err status. RW */ -#define LAPIC_LVT_CMCI 0x2f0 /* LVT CMCI RW */ +#define LAPIC_LVT_CMCI 0x2f0 /* Loc.vec (CMCI) RW */ #define LAPIC_ICRLO 0x300 /* Int. cmd. (xAPIC: RW, x2APIC: RW64) */ # define LAPIC_DLMODE_MASK 0x0700 /* Delivery Mode */
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Thu Jun 13 07:44:27 UTC 2019 Modified Files: src/sys/arch/x86/include: i82489reg.h Log Message: Modify LAPIC_LVT_CMCI's comment to be consistent with other LVT's. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.16 -r1.17 src/sys/arch/x86/include/i82489reg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
