Module Name:src
Committed By: riastradh
Date: Sun Apr 7 22:59:13 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: clock_machdep.c
Log Message:
riscv: Schedule next hardclock tick in the future, not the past.
If we have missed hardclock ticks, schedule up to one tick
Module Name:src
Committed By: riastradh
Date: Sun Apr 7 22:59:13 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: clock_machdep.c
Log Message:
riscv: Schedule next hardclock tick in the future, not the past.
If we have missed hardclock ticks, schedule up to one tick
Module Name:src
Committed By: riastradh
Date: Sun Apr 7 22:52:53 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: cpu.c
Log Message:
riscv: Make sure cpu0->ci_cpu_freq is initialized by cpu_attach.
Otherwise this stays zero, which screws up cpu_ipi_wait.
To generate
Module Name:src
Committed By: riastradh
Date: Sun Apr 7 22:52:53 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: cpu.c
Log Message:
riscv: Make sure cpu0->ci_cpu_freq is initialized by cpu_attach.
Otherwise this stays zero, which screws up cpu_ipi_wait.
To generate
Module Name:src
Committed By: skrll
Date: Sat Apr 6 13:41:03 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: copy.S
Log Message:
Fix riscv32 build
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/riscv/copy.S
Please note that diffs are
Module Name:src
Committed By: skrll
Date: Sat Apr 6 13:41:03 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: copy.S
Log Message:
Fix riscv32 build
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/riscv/copy.S
Please note that diffs are
Module Name:src
Committed By: skrll
Date: Mon Apr 1 16:24:01 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: trap.c
Log Message:
Return the correct error from {fetch,store}_user_data and fix
futex_wake_op_op: [0.273033s] Failed:
Module Name:src
Committed By: skrll
Date: Mon Apr 1 16:24:01 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: trap.c
Log Message:
Return the correct error from {fetch,store}_user_data and fix
futex_wake_op_op: [0.273033s] Failed:
Module Name:src
Committed By: skrll
Date: Thu Feb 8 18:25:58 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: bus_dma.c
Log Message:
Define _RISCV_NEED_BUS_DMA_BOUNCE.
Pointed out as being needed by jmcneill. Thanks!
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: skrll
Date: Thu Feb 8 18:25:58 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: bus_dma.c
Log Message:
Define _RISCV_NEED_BUS_DMA_BOUNCE.
Pointed out as being needed by jmcneill. Thanks!
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: skrll
Date: Fri Jan 19 09:09:39 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: autoconf.c
Log Message:
Use fdt_cpu_rootconf
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/riscv/autoconf.c
Please note
Module Name:src
Committed By: skrll
Date: Fri Jan 19 09:09:39 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: autoconf.c
Log Message:
Use fdt_cpu_rootconf
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/riscv/autoconf.c
Please note
Module Name:src
Committed By: skrll
Date: Thu Jan 18 07:41:50 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: clock_machdep.c riscv_machdep.c
Log Message:
Provide a working delay(9)
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7
Module Name:src
Committed By: skrll
Date: Thu Jan 18 07:41:50 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: clock_machdep.c riscv_machdep.c
Log Message:
Provide a working delay(9)
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7
Module Name:src
Committed By: msaitoh
Date: Thu Jan 18 03:36:24 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: kobj_machdep.c
Log Message:
s/FALLTHOUGH/FALLTHROUGH/ in comment.
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6
Module Name:src
Committed By: msaitoh
Date: Thu Jan 18 03:36:24 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: kobj_machdep.c
Log Message:
s/FALLTHOUGH/FALLTHROUGH/ in comment.
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6
Module Name:src
Committed By: skrll
Date: Fri Dec 22 08:41:59 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: db_interface.c riscv_machdep.c
Log Message:
Minor stylistic changes. NFCI.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5
Module Name:src
Committed By: skrll
Date: Fri Dec 22 08:41:59 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: db_interface.c riscv_machdep.c
Log Message:
Minor stylistic changes. NFCI.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5
Module Name:src
Committed By: skrll
Date: Thu Sep 7 12:48:49 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: trap.c
Log Message:
Handle CAUSE_LOAD_PAGE_FAULT in trap_pagefault_fixup
To generate a diff of this commit:
cvs rdiff -u -r1.23 -r1.24
Module Name:src
Committed By: skrll
Date: Thu Sep 7 12:48:49 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: trap.c
Log Message:
Handle CAUSE_LOAD_PAGE_FAULT in trap_pagefault_fixup
To generate a diff of this commit:
cvs rdiff -u -r1.23 -r1.24
Module Name:src
Committed By: skrll
Date: Mon Aug 28 11:12:42 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: cpu.c
Log Message:
Remove duplicate .ci_cpl initialiser.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/riscv/cpu.c
Please
Module Name:src
Committed By: skrll
Date: Mon Aug 28 11:12:42 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: cpu.c
Log Message:
Remove duplicate .ci_cpl initialiser.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/riscv/cpu.c
Please
Module Name:src
Committed By: rin
Date: Thu Aug 24 05:46:55 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: riscv_machdep.c
Log Message:
riscv: cpu_setmcontext: Do not unconditionally update tp register
Conserve tp register for _UC_CPU and update later if _UC_TLSBASE
Module Name:src
Committed By: rin
Date: Thu Aug 24 05:46:55 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: riscv_machdep.c
Log Message:
riscv: cpu_setmcontext: Do not unconditionally update tp register
Conserve tp register for _UC_CPU and update later if _UC_TLSBASE
Module Name:src
Committed By: rin
Date: Tue Aug 22 07:11:15 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: trap.c
Log Message:
riscv/trap.c: Dump cause register for unhandled page fault
To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23
Module Name:src
Committed By: rin
Date: Tue Aug 22 07:11:15 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: trap.c
Log Message:
riscv/trap.c: Dump cause register for unhandled page fault
To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23
Module Name:src
Committed By: rin
Date: Tue Aug 22 07:10:39 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: trap.c
Log Message:
riscv/trap.c: Handle userland breakpoint exception
Now, gdb 13 works for riscv64 to some extent :)
To generate a diff of this commit:
cvs
Module Name:src
Committed By: rin
Date: Tue Aug 22 07:10:39 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: trap.c
Log Message:
riscv/trap.c: Handle userland breakpoint exception
Now, gdb 13 works for riscv64 to some extent :)
To generate a diff of this commit:
cvs
Module Name:src
Committed By: skrll
Date: Wed Jul 26 06:13:44 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: clock_machdep.c
Log Message:
Attach the clock event counter for each cpu^Whart.
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6
Module Name:src
Committed By: skrll
Date: Wed Jul 26 06:13:44 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: clock_machdep.c
Log Message:
Attach the clock event counter for each cpu^Whart.
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6
Module Name:src
Committed By: rin
Date: Mon Jul 10 07:04:20 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: autoconf.c riscv_machdep.c
Log Message:
riscv: Add FDT-based initrd, rndseed, and efirng support.
Can be used from our in-tree bootrisv64.efi.
To generate a
Module Name:src
Committed By: rin
Date: Mon Jul 10 07:04:20 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: autoconf.c riscv_machdep.c
Log Message:
riscv: Add FDT-based initrd, rndseed, and efirng support.
Can be used from our in-tree bootrisv64.efi.
To generate a
Module Name:src
Committed By: skrll
Date: Sat Jun 24 07:23:07 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: cpu.c
Log Message:
Always initialise ci_tlb_info in cpu_info_store[0].
Fixes non-MP boot for me.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3
Module Name:src
Committed By: skrll
Date: Sat Jun 24 07:23:07 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: cpu.c
Log Message:
Always initialise ci_tlb_info in cpu_info_store[0].
Fixes non-MP boot for me.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3
Module Name:src
Committed By: skrll
Date: Sat Jun 10 09:18:50 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: spl.S
Log Message:
Remove magic numbers. NFCI.
Copyright maintenance while I'm here.
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7
Module Name:src
Committed By: skrll
Date: Sat Jun 10 09:18:50 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: spl.S
Log Message:
Remove magic numbers. NFCI.
Copyright maintenance while I'm here.
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7
Module Name:src
Committed By: skrll
Date: Sat Jun 10 07:02:26 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: pmap_machdep.c
Log Message:
Whitespace.
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/riscv/riscv/pmap_machdep.c
Please note
Module Name:src
Committed By: skrll
Date: Sat Jun 10 07:02:26 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: pmap_machdep.c
Log Message:
Whitespace.
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/riscv/riscv/pmap_machdep.c
Please note
Module Name:src
Committed By: skrll
Date: Sun May 28 12:56:56 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: riscv_machdep.c
Log Message:
Second arg to fdt_memory_remove_range is a size so pass dtbsize and not
dtb + dtbsize
To generate a diff of this commit:
cvs
Module Name:src
Committed By: skrll
Date: Sun May 28 12:56:56 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: riscv_machdep.c
Log Message:
Second arg to fdt_memory_remove_range is a size so pass dtbsize and not
dtb + dtbsize
To generate a diff of this commit:
cvs
Module Name:src
Committed By: skrll
Date: Sun May 14 09:14:30 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: riscv_machdep.c
Log Message:
Check for RB_HALT in cpu_reboot.
To generate a diff of this commit:
cvs rdiff -u -r1.26 -r1.27
Module Name:src
Committed By: skrll
Date: Sun May 14 09:14:30 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: riscv_machdep.c
Log Message:
Check for RB_HALT in cpu_reboot.
To generate a diff of this commit:
cvs rdiff -u -r1.26 -r1.27
Module Name:src
Committed By: riastradh
Date: Wed Mar 1 08:18:24 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: cpu_switch.S
Log Message:
riscv: Optimization: Omit needless membar when triggering softint.
When we are triggering a softint, it can't already hold any
Module Name:src
Committed By: riastradh
Date: Wed Mar 1 08:18:24 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: cpu_switch.S
Log Message:
riscv: Optimization: Omit needless membar when triggering softint.
When we are triggering a softint, it can't already hold any
Module Name:src
Committed By: riastradh
Date: Thu Feb 23 14:56:23 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: cpu_switch.S
Log Message:
riscv: Add missing barriers in cpu_switchto.
Details in comments.
PR kern/57240
To generate a diff of this commit:
cvs rdiff
Module Name:src
Committed By: riastradh
Date: Thu Feb 23 14:56:23 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: cpu_switch.S
Log Message:
riscv: Add missing barriers in cpu_switchto.
Details in comments.
PR kern/57240
To generate a diff of this commit:
cvs rdiff
Module Name:src
Committed By: skrll
Date: Sun Dec 4 16:29:35 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: cpu_switch.S
Log Message:
Restore t5 and t6 from the correct locations in exception_kernexit.
>From Simon.
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: skrll
Date: Sun Dec 4 16:29:35 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: cpu_switch.S
Log Message:
Restore t5 and t6 from the correct locations in exception_kernexit.
>From Simon.
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: skrll
Date: Sun Dec 4 16:23:48 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: vm_machdep.c
Log Message:
ASSERT that md_astpending it zero for the new lwp.
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7
Module Name:src
Committed By: skrll
Date: Sun Dec 4 16:23:48 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: vm_machdep.c
Log Message:
ASSERT that md_astpending it zero for the new lwp.
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7
Module Name:src
Committed By: skrll
Date: Sat Nov 19 09:55:11 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
Fix CONSADDR and save a label
To generate a diff of this commit:
cvs rdiff -u -r1.39 -r1.40 src/sys/arch/riscv/riscv/locore.S
Please
Module Name:src
Committed By: skrll
Date: Sat Nov 19 09:55:11 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
Fix CONSADDR and save a label
To generate a diff of this commit:
cvs rdiff -u -r1.39 -r1.40 src/sys/arch/riscv/riscv/locore.S
Please
Module Name:src
Committed By: simonb
Date: Thu Nov 17 13:11:08 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: riscv_machdep.c
Log Message:
Use updated defines for the user-mode sstatus value.
To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25
Module Name:src
Committed By: simonb
Date: Thu Nov 17 13:11:08 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: riscv_machdep.c
Log Message:
Use updated defines for the user-mode sstatus value.
To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25
Module Name:src
Committed By: simonb
Date: Mon Oct 31 12:50:49 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: bus_space_generic.S
Log Message:
In bus_space_write_{1,2,4,8} store the correct register in write to device.
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: simonb
Date: Mon Oct 31 12:50:49 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: bus_space_generic.S
Log Message:
In bus_space_write_{1,2,4,8} store the correct register in write to device.
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: simonb
Date: Mon Oct 31 12:49:18 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: bus_space_generic.S
Log Message:
Fix tyop in END for generic_bs_r_8.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2
Module Name:src
Committed By: simonb
Date: Mon Oct 31 12:49:18 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: bus_space_generic.S
Log Message:
Fix tyop in END for generic_bs_r_8.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2
Module Name:src
Committed By: skrll
Date: Tue Oct 18 04:24:54 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: riscv_machdep.c
Log Message:
remove a stray comment
To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/riscv/riscv/riscv_machdep.c
Module Name:src
Committed By: skrll
Date: Tue Oct 18 04:24:54 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: riscv_machdep.c
Log Message:
remove a stray comment
To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/riscv/riscv/riscv_machdep.c
Module Name:src
Committed By: skrll
Date: Sun Oct 16 08:43:44 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: pmap_machdep.c
Log Message:
tlb_update_addr gets called with the KERNEL_PID (ASID) so handle this
case.
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: skrll
Date: Sun Oct 16 08:43:44 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: pmap_machdep.c
Log Message:
tlb_update_addr gets called with the KERNEL_PID (ASID) so handle this
case.
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: skrll
Date: Sun Oct 16 06:19:16 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: riscv_machdep.c
Log Message:
Re-orgnaise a litte. From Simon.
To generate a diff of this commit:
cvs rdiff -u -r1.21 -r1.22
Module Name:src
Committed By: skrll
Date: Sun Oct 16 06:19:16 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: riscv_machdep.c
Log Message:
Re-orgnaise a litte. From Simon.
To generate a diff of this commit:
cvs rdiff -u -r1.21 -r1.22
Module Name:src
Committed By: skrll
Date: Sun Oct 16 06:03:14 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
Use a local label
To generate a diff of this commit:
cvs rdiff -u -r1.37 -r1.38 src/sys/arch/riscv/riscv/locore.S
Please note that
Module Name:src
Committed By: skrll
Date: Sun Oct 16 06:03:14 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
Use a local label
To generate a diff of this commit:
cvs rdiff -u -r1.37 -r1.38 src/sys/arch/riscv/riscv/locore.S
Please note that
Module Name:src
Committed By: skrll
Date: Sun Oct 16 05:56:50 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
More register re-org
To generate a diff of this commit:
cvs rdiff -u -r1.36 -r1.37 src/sys/arch/riscv/riscv/locore.S
Please note that
Module Name:src
Committed By: skrll
Date: Sun Oct 16 05:56:50 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
More register re-org
To generate a diff of this commit:
cvs rdiff -u -r1.36 -r1.37 src/sys/arch/riscv/riscv/locore.S
Please note that
Module Name:src
Committed By: skrll
Date: Sun Oct 16 05:48:15 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
Fix after register re-org
To generate a diff of this commit:
cvs rdiff -u -r1.35 -r1.36 src/sys/arch/riscv/riscv/locore.S
Please note
Module Name:src
Committed By: skrll
Date: Sun Oct 16 05:48:15 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
Fix after register re-org
To generate a diff of this commit:
cvs rdiff -u -r1.35 -r1.36 src/sys/arch/riscv/riscv/locore.S
Please note
Module Name:src
Committed By: skrll
Date: Sat Oct 15 16:58:16 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
More register use re-org.
To generate a diff of this commit:
cvs rdiff -u -r1.34 -r1.35 src/sys/arch/riscv/riscv/locore.S
Please note
Module Name:src
Committed By: skrll
Date: Sat Oct 15 16:58:16 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
More register use re-org.
To generate a diff of this commit:
cvs rdiff -u -r1.34 -r1.35 src/sys/arch/riscv/riscv/locore.S
Please note
Module Name:src
Committed By: skrll
Date: Sat Oct 15 16:34:29 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
Shuffle some register usage
To generate a diff of this commit:
cvs rdiff -u -r1.33 -r1.34 src/sys/arch/riscv/riscv/locore.S
Please
Module Name:src
Committed By: skrll
Date: Sat Oct 15 16:34:29 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
Shuffle some register usage
To generate a diff of this commit:
cvs rdiff -u -r1.33 -r1.34 src/sys/arch/riscv/riscv/locore.S
Please
Module Name:src
Committed By: skrll
Date: Sat Oct 15 16:29:56 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
Comment re-arragement
To generate a diff of this commit:
cvs rdiff -u -r1.32 -r1.33 src/sys/arch/riscv/riscv/locore.S
Please note that
Module Name:src
Committed By: skrll
Date: Sat Oct 15 16:29:56 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
Comment re-arragement
To generate a diff of this commit:
cvs rdiff -u -r1.32 -r1.33 src/sys/arch/riscv/riscv/locore.S
Please note that
Module Name:src
Committed By: skrll
Date: Sat Oct 15 16:20:32 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
Remove unnecessary register assignments
To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/riscv/riscv/locore.S
Module Name:src
Committed By: skrll
Date: Sat Oct 15 16:20:32 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
Remove unnecessary register assignments
To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/riscv/riscv/locore.S
Module Name:src
Committed By: skrll
Date: Fri Oct 14 08:10:22 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
Pretty print
To generate a diff of this commit:
cvs rdiff -u -r1.30 -r1.31 src/sys/arch/riscv/riscv/locore.S
Please note that diffs
Module Name:src
Committed By: skrll
Date: Fri Oct 14 08:10:22 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
Pretty print
To generate a diff of this commit:
cvs rdiff -u -r1.30 -r1.31 src/sys/arch/riscv/riscv/locore.S
Please note that diffs
Module Name:src
Committed By: simonb
Date: Wed Oct 12 07:53:56 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: db_machdep.c
Log Message:
Nuke funny trailing whitespace.
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/riscv/riscv/db_machdep.c
Module Name:src
Committed By: simonb
Date: Wed Oct 12 07:53:56 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: db_machdep.c
Log Message:
Nuke funny trailing whitespace.
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/riscv/riscv/db_machdep.c
Module Name:src
Committed By: skrll
Date: Thu Sep 29 06:51:17 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: exec_machdep.c vm_machdep.c
Log Message:
Remove unnecessary include of .
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3
Module Name:src
Committed By: skrll
Date: Thu Sep 29 06:51:17 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: exec_machdep.c vm_machdep.c
Log Message:
Remove unnecessary include of .
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3
Module Name:src
Committed By: skrll
Date: Wed Sep 21 07:07:34 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: trap.c
Log Message:
Add some causes and convenience macros
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/riscv/riscv/trap.c
Module Name:src
Committed By: skrll
Date: Wed Sep 21 07:07:34 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: trap.c
Log Message:
Add some causes and convenience macros
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/riscv/riscv/trap.c
Module Name:src
Committed By: skrll
Date: Tue Sep 20 06:53:37 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: riscv_machdep.c
Log Message:
Whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/riscv/riscv/riscv_machdep.c
Please note
Module Name:src
Committed By: skrll
Date: Tue Sep 20 06:53:37 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: riscv_machdep.c
Log Message:
Whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/riscv/riscv/riscv_machdep.c
Please note
Module Name:src
Committed By: skrll
Date: Tue Sep 20 06:48:29 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: riscv_machdep.c
Log Message:
KNF
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/riscv/riscv/riscv_machdep.c
Please note that
Module Name:src
Committed By: skrll
Date: Tue Sep 20 06:48:29 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: riscv_machdep.c
Log Message:
KNF
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/riscv/riscv/riscv_machdep.c
Please note that
Module Name:src
Committed By: skrll
Date: Sat Oct 30 07:18:47 UTC 2021
Modified Files:
src/sys/arch/riscv/riscv: pmap_machdep.c
Log Message:
Fix thinko in tlb_record_asids memset size calculation.
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10
Module Name:src
Committed By: skrll
Date: Sat Oct 30 07:18:47 UTC 2021
Modified Files:
src/sys/arch/riscv/riscv: pmap_machdep.c
Log Message:
Fix thinko in tlb_record_asids memset size calculation.
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10
Module Name:src
Committed By: skrll
Date: Thu Oct 7 07:13:35 UTC 2021
Modified Files:
src/sys/arch/riscv/riscv: pmap_machdep.c riscv_machdep.c syscall.c
trap.c
Log Message:
Hacky build fixes
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9
Module Name:src
Committed By: skrll
Date: Thu Oct 7 07:13:35 UTC 2021
Modified Files:
src/sys/arch/riscv/riscv: pmap_machdep.c riscv_machdep.c syscall.c
trap.c
Log Message:
Hacky build fixes
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9
Hi Matt,
On Tue, Mar 31, 2015 at 01:30:50AM +, Matt Thomas wrote:
When the cpu gets an exception from kernel mode, the sscratch register will be
0 and curlwp will be in the tp register. When the cpu gets an exception
from
user mode, the sscratch register will be a pointer to the current
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