Module Name:src
Committed By: msaitoh
Date: Mon Aug 20 08:53:48 UTC 2018
Modified Files:
src/sys/arch/x86/include: specialreg.h
src/sys/arch/x86/x86: procfs_machdep.c
Log Message:
OK'd by maxv:
- Add cpuid 7 edx L1D_FLUSH bit.
- Add IA32_ARCH_SKIP_L1DFL_VMENTRY bit
Module Name:src
Committed By: maxv
Date: Sat Aug 18 08:45:55 UTC 2018
Modified Files:
src/sys/arch/x86/x86: pmap.c
Log Message:
Simplify the conditions. Fixes compilation of native amd64 without direct
map.
To generate a diff of this commit:
cvs rdiff -u -r1.302 -r1.303
Module Name:src
Committed By: maxv
Date: Sun Aug 12 11:51:42 UTC 2018
Modified Files:
src/sys/arch/x86/x86: pmap.c
Log Message:
Reduce the minefield: zero out the pdir only once, at the beginning of
the function. This eliminates one assumption on the order of the VM
areas.
Module Name:src
Committed By: maxv
Date: Sun Aug 12 10:45:27 UTC 2018
Modified Files:
src/sys/arch/x86/x86: pmap.c
Log Message:
Take the last area into account, there is a hole before it.
To generate a diff of this commit:
cvs rdiff -u -r1.296 -r1.297 src/sys/arch/x86/x8
Module Name:src
Committed By: maxv
Date: Sun Aug 12 05:43:42 UTC 2018
Modified Files:
src/sys/arch/x86/x86: errata.c
Log Message:
enable the two errata for AMD Family 16h, tested by mrg@, thanks
To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/x
Module Name:src
Committed By: maxv
Date: Tue Aug 7 10:50:12 UTC 2018
Modified Files:
src/sys/arch/x86/include: specialreg.h
src/sys/arch/x86/x86: errata.c
Log Message:
Add five errata for AMD Family 17h (Ryzen etc), tested by Patrick Welche,
thanks. Also add two e
Module Name:src
Committed By: maxv
Date: Thu Jul 26 08:22:19 UTC 2018
Modified Files:
src/sys/arch/x86/x86: cpu.c pmap.c
Log Message:
Remove useless/outdated comments. No functional change.
To generate a diff of this commit:
cvs rdiff -u -r1.159 -r1.160 src/sys/arch/x86/
Module Name:src
Committed By: para
Date: Wed Jul 25 19:10:41 UTC 2018
Modified Files:
src/sys/arch/x86/pci: amdzentemp.c
Log Message:
adjust for possible 49K offset
presence of this offset is indicated by a set 19th bit which is shifted away
this brings the temperature to
Module Name:src
Committed By: maxv
Date: Sat Jul 21 21:26:30 UTC 2018
Modified Files:
src/sys/arch/x86/x86: pmap.c
Log Message:
I realized the changes I made broke the !aslr conf, so enable aslr by
default now rather than later (and rather than adding more ifdefs).
Now th
Module Name:src
Committed By: kre
Date: Sat Jul 21 14:46:41 UTC 2018
Modified Files:
src/sys/arch/x86/x86: cpu_rng.c
Log Message:
Unbreak build. Fake out (ie: remove) rdtsc() which does not
exist on XEN (or not yet anyway).
This change needs to be reverted when a proper
Module Name:src
Committed By: pgoyette
Date: Mon Jul 16 07:07:30 UTC 2018
Modified Files:
src/sys/arch/x86/include: cpu.h
Log Message:
More rearrangement of struct cpu_info to keep all the un-conditional
members at fixed locations.
Should address my PR kern/52919
OK maxv
Module Name:src
Committed By: maxv
Date: Sun Jul 15 08:47:43 UTC 2018
Modified Files:
src/sys/arch/x86/include: cpu.h
Log Message:
Hum. Move the __HAVE_DIRECT_MAP block a little below, otherwise dynamically
loaded kernel modules use a wrong offset for some ci_* fields. Fou
Module Name:src
Committed By: maxv
Date: Sun Jul 15 06:14:21 UTC 2018
Modified Files:
src/sys/arch/x86/x86: tprof_amdpmi.c tprof_pmi.c
Removed Files:
src/sys/arch/x86/include: tprof.h
Log Message:
Remove unused x86/include/tprof.h, there should be no need for this
Module Name:src
Committed By: maxv
Date: Sat Jul 14 14:46:41 UTC 2018
Modified Files:
src/sys/arch/x86/x86: via_padlock.c
Log Message:
Add splhigh() around the FPU code, we don't want to be preempted in the
middle, this could corrupt the FPU state and trigger undefined beh
Module Name:src
Committed By: maxv
Date: Sat Jul 14 14:34:32 UTC 2018
Modified Files:
src/sys/arch/x86/x86: patch.c
Log Message:
Remove ifdef GPROF.
To generate a diff of this commit:
cvs rdiff -u -r1.34 -r1.35 src/sys/arch/x86/x86/patch.c
Please note that diffs are not
Module Name:src
Committed By: maxv
Date: Thu Jul 12 18:39:09 UTC 2018
Modified Files:
src/sys/arch/x86/x86: cpu.c
Log Message:
Oh. Don't call svs_pdir_switch if SVS is disabled, that's not needed.
I was playing around with PMCs, and was wondering why some cache misses
wer
Module Name:src
Committed By: msaitoh
Date: Wed Jul 11 03:36:32 UTC 2018
Modified Files:
src/sys/arch/x86/x86: coretemp.c
Log Message:
- Detect and set Atom's Tj(max) to 90 if it's not the 45nm D400/D500/N400
series (90 for Diamondville and 100 for Pineview). From FreeBS
Module Name:src
Committed By: maxv
Date: Tue Jul 10 06:44:49 UTC 2018
Modified Files:
src/sys/arch/x86/pci: pci_machdep.c
Log Message:
Fix bug, SPINOUT() is not supposed to take the value given to BACKOFF().
Here the exponential backoff is wrecked.
To generate a diff of
Module Name:src
Committed By: kamil
Date: Sun Jul 8 14:46:23 UTC 2018
Modified Files:
src/sys/arch/x86/x86: mpbios.c
Log Message:
Revert previous
Misalignment access handling patches are now discussed on tech-kern.
Requested by and .
To generate a diff of this commit
Module Name:src
Committed By: kamil
Date: Sat Jul 7 23:05:50 UTC 2018
Modified Files:
src/sys/arch/x86/x86: mpbios.c
Log Message:
Remove unaligned access to mpbios_page[]
Replace unaligned pointer dereference with a more portable construct that
is free from Undefined Beh
Module Name:src
Committed By: maya
Date: Wed Jul 4 07:55:57 UTC 2018
Modified Files:
src/sys/arch/x86/include: specialreg.h
src/sys/arch/x86/x86: identcpu.c
Log Message:
Disable MWAIT/MONITOR on Apollo Lake CPUs to workaround APL30 errata.
We use MWAIT/MONITOR to
Module Name:src
Committed By: kamil
Date: Tue Jul 3 11:45:54 UTC 2018
Modified Files:
src/sys/arch/x86/x86: intr.c
Log Message:
Avoid unportable signed integer left shift in intr_calculatemasks()
Detected with Kernel Undefined Behavior Sanitizer.
There were at least two
Module Name:src
Committed By: maxv
Date: Sun Jul 1 08:32:41 UTC 2018
Modified Files:
src/sys/arch/x86/x86: fpu.c vm_machdep.c
Log Message:
Use a variable-sized memcpy, instead of copying the PCB and then adding
the extra bytes. The PCB embeds the biggest static FPU state,
Module Name:src
Committed By: maxv
Date: Sun Jul 1 07:59:30 UTC 2018
Modified Files:
src/sys/arch/x86/x86: identcpu.c
Log Message:
Optimize FNSAVE. The size of its save area is 108 bytes, so don't set
x86_fpu_save_size = 512, because otherwise we uselessly memset extra
by
Module Name:src
Committed By: maxv
Date: Sun Jul 1 07:18:56 UTC 2018
Modified Files:
src/sys/arch/x86/x86: fpu.c
Log Message:
Use a switch, we can (and will) optimize each case separately. No
functional change.
To generate a diff of this commit:
cvs rdiff -u -r1.44 -r1.
Module Name:src
Committed By: maxv
Date: Fri Jun 29 19:34:35 UTC 2018
Modified Files:
src/sys/arch/x86/x86: fpu.c
Log Message:
Add more KASSERTs.
Should help PR/53399.
To generate a diff of this commit:
cvs rdiff -u -r1.43 -r1.44 src/sys/arch/x86/x86/fpu.c
Please note
Module Name:src
Committed By: jakllsch
Date: Sat Jun 23 16:09:53 UTC 2018
Modified Files:
src/sys/arch/x86/pci: pci_machdep.c
Log Message:
Disable all contemporary mode 1 quirks.
To generate a diff of this commit:
cvs rdiff -u -r1.81 -r1.82 src/sys/arch/x86/pci/pci_machd
Module Name:src
Committed By: jakllsch
Date: Sat Jun 23 16:05:05 UTC 2018
Modified Files:
src/sys/arch/x86/pci: pci_machdep.c
Log Message:
If mode 1 enable check fails, give mode 1 a second chance by trying to
use it to locate a PCI Host Bridge or device from vendor that p
Module Name:src
Committed By: maxv
Date: Sat Jun 23 10:06:02 UTC 2018
Modified Files:
src/sys/arch/x86/x86: fpu.c
Log Message:
Add XXX in fpuinit_mxcsr_mask.
To generate a diff of this commit:
cvs rdiff -u -r1.42 -r1.43 src/sys/arch/x86/x86/fpu.c
Please note that diffs
Module Name:src
Committed By: maxv
Date: Sat Jun 23 10:02:39 UTC 2018
Modified Files:
src/sys/arch/x86/x86: identcpu.c
Log Message:
Reorder the code a little. On Xen, return earlier, we don't need to do
the XSAVE-related initialization if we don't support XSAVE.
To gener
Module Name:src
Committed By: christos
Date: Fri Jun 22 23:00:54 UTC 2018
Modified Files:
src/sys/arch/x86/x86: identcpu.c
Log Message:
Handle more Vortex CPU's from Andrius V.
While here refactor the code to make it smaller.
To generate a diff of this commit:
cvs rdiff
Module Name:src
Committed By: maxv
Date: Wed Jun 20 11:57:22 UTC 2018
Modified Files:
src/sys/arch/x86/x86: pmap.c
Log Message:
Use PMAP_DIRECT_UNMAP.
To generate a diff of this commit:
cvs rdiff -u -r1.290 -r1.291 src/sys/arch/x86/x86/pmap.c
Please note that diffs are
Module Name:src
Committed By: maxv
Date: Tue Jun 19 09:25:13 UTC 2018
Modified Files:
src/sys/arch/x86/x86: fpu.c
Log Message:
When using EagerFPU, create the fpu state in execve at IPL_HIGH.
A preemption could occur in the middle, and we don't want that to happen,
becaus
Module Name:src
Committed By: maxv
Date: Tue Jun 19 07:23:45 UTC 2018
Modified Files:
src/sys/arch/x86/x86: vm_machdep.c
Log Message:
Explicitly clear l2's pcb_fpcpu when forking.
A context switch (preemption) could occur between
fpusave_lwp(l1, true);
and
Module Name:src
Committed By: maxv
Date: Mon Jun 18 20:20:27 UTC 2018
Modified Files:
src/sys/arch/x86/x86: fpu.c
Log Message:
Add more KASSERTs, see if they help PR/53383.
To generate a diff of this commit:
cvs rdiff -u -r1.37 -r1.38 src/sys/arch/x86/x86/fpu.c
Please n
Module Name:src
Committed By: maxv
Date: Sun Jun 17 07:13:02 UTC 2018
Modified Files:
src/sys/arch/x86/x86: identcpu.c
Log Message:
Enable eager fpu automatically at boot time if the cpu is affected. Intel
hasn't published a list of its affected products, but it appears th
Module Name:src
Committed By: maxv
Date: Sun Jun 17 06:03:41 UTC 2018
Modified Files:
src/sys/arch/x86/x86: fpu.c
Log Message:
No, I meant to put the panic in fpudna not fputrap. Also appease it: panic
only if the fpu already has a state. We're fine with getting a DNA, wha
Module Name:src
Committed By: maxv
Date: Sat Jun 16 17:11:13 UTC 2018
Modified Files:
src/sys/arch/x86/x86: fpu.c x86_machdep.c
Log Message:
Need IPIs when enabling eager fpu switch, to clear each fpu and get us
started. Otherwise it is possible that the first context swit
Module Name:src
Committed By: maxv
Date: Sat Jun 16 05:52:17 UTC 2018
Modified Files:
src/sys/arch/x86/x86: fpu.c
Log Message:
Actually, don't do anything if we switch to a kernel thread. When the cpu
switches back to a user thread the fpu is restored, so no point calling
Module Name:src
Committed By: maxv
Date: Thu Jun 14 18:00:16 UTC 2018
Modified Files:
src/sys/arch/x86/x86: fpu.c
Log Message:
Install the FPU state on the current CPU in setregs (execve).
To generate a diff of this commit:
cvs rdiff -u -r1.33 -r1.34 src/sys/arch/x86/x86
Module Name:src
Committed By: thorpej
Date: Thu Jun 7 13:35:31 UTC 2018
Modified Files:
src/sys/arch/x86/x86: x86_autoconf.c
Log Message:
In device_register(), if the device is an "iic" child of "imcsmb",
attach a I2C_PROP_INDIRECT_DEVICE_WHITELIST property that limits
th
Module Name:src
Committed By: maxv
Date: Sun Jun 3 10:13:54 UTC 2018
Modified Files:
src/sys/arch/x86/pci: ichlpcib.c
Log Message:
Constify lpcib_devices[] so that it lands in .rodata (1584 bytes).
To generate a diff of this commit:
cvs rdiff -u -r1.51 -r1.52 src/sys/ar
Module Name:src
Committed By: msaitoh
Date: Thu May 31 03:29:01 UTC 2018
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Fix the bit location of SSBD in the macro for snprintb.
To generate a diff of this commit:
cvs rdiff -u -r1.125 -r1.126 src/sys/a
Module Name:src
Committed By: maxv
Date: Mon May 28 20:18:58 UTC 2018
Modified Files:
src/sys/arch/x86/x86: spectre.c
Log Message:
Mmh, don't automatically set enabled=1 for SpectreV4, the actual mitigation
is not yet applied by default. Just so people can test.
To gener
Module Name:src
Committed By: maxv
Date: Wed May 23 10:21:43 UTC 2018
Modified Files:
src/sys/arch/x86/x86: fpu.c
Log Message:
Add a comment about recent AMD CPUs.
To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/x86/x86/fpu.c
Please note that
Module Name:src
Committed By: maxv
Date: Wed May 23 10:00:27 UTC 2018
Modified Files:
src/sys/arch/x86/x86: fpu.c
Log Message:
Clarify and extend the fix for the AMD FPU leaks. We were clearing the x87
state only on FXRSTOR, but the same problem exists on XRSTOR, so clear
Module Name:src
Committed By: maxv
Date: Wed May 23 07:34:40 UTC 2018
Modified Files:
src/sys/arch/x86/x86: fpu.c
Log Message:
style
To generate a diff of this commit:
cvs rdiff -u -r1.28 -r1.29 src/sys/arch/x86/x86/fpu.c
Please note that diffs are not public domain; th
Module Name:src
Committed By: maxv
Date: Wed May 23 07:24:38 UTC 2018
Modified Files:
src/sys/arch/x86/include: cpu_extended_state.h specialreg.h
Log Message:
Clean up the FPU headers.
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/x86/include
Module Name:src
Committed By: msaitoh
Date: Wed May 23 05:04:39 UTC 2018
Modified Files:
src/sys/arch/x86/x86: procfs_machdep.c
Log Message:
Add SSBD bit for Intel.
To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/x86/x86/procfs_machdep.c
Plea
Module Name:src
Committed By: maxv
Date: Tue May 22 17:14:47 UTC 2018
Modified Files:
src/sys/arch/x86/include: specialreg.h
src/sys/arch/x86/x86: spectre.c
Log Message:
Extend the AMD NONARCH method to family 17h. The AMD spec states that for
17h care must be take
Module Name:src
Committed By: maxv
Date: Tue May 22 16:44:43 UTC 2018
Modified Files:
src/sys/arch/x86/x86: spectre.c
Log Message:
Simplify the sysctl handlers.
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/x86/x86/spectre.c
Please note that
Module Name:src
Committed By: maxv
Date: Tue May 22 16:36:19 UTC 2018
Modified Files:
src/sys/arch/x86/x86: spectre.c
Log Message:
Forgot switch cases for AMD.
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/x86/x86/spectre.c
Please note that
Module Name:src
Committed By: maxv
Date: Tue May 22 10:20:05 UTC 2018
Modified Files:
src/sys/arch/x86/include: specialreg.h
src/sys/arch/x86/x86: spectre.c
Log Message:
Implement a mitigation for SpectreV4 on AMD families 15h and 16h. We use
a non-architectural MS
Module Name:src
Committed By: maxv
Date: Tue May 22 09:25:58 UTC 2018
Modified Files:
src/sys/arch/x86/x86: spectre.c x86_machdep.c
Log Message:
Several changes:
- Move the sysctl initialization code into spectre.c. This way each
variable is local. Rename the variable
Module Name:src
Committed By: maxv
Date: Tue May 22 07:24:08 UTC 2018
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Add RSBA. When set, it indicates that the CPU is vulnerable to SpectreV2
via the RSB.
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: maxv
Date: Tue May 22 07:11:54 UTC 2018
Modified Files:
src/sys/arch/x86/include: specialreg.h
src/sys/arch/x86/x86: spectre.c x86_machdep.c
Log Message:
Mitigation for SpectreV4, based on SSBD. The following sysctl branches
are added:
Module Name:src
Committed By: maxv
Date: Tue May 22 06:31:05 UTC 2018
Modified Files:
src/sys/arch/x86/x86: spectre.c x86_machdep.c
Log Message:
Reorder and rename, to make the code less SpectreV2-specific.
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 sr
Module Name:src
Committed By: jakllsch
Date: Sat May 19 16:55:59 UTC 2018
Modified Files:
src/sys/arch/x86/include: pmap.h
Log Message:
remove some remaining uvm_emap(9)-related function prototypes
To generate a diff of this commit:
cvs rdiff -u -r1.78 -r1.79 src/sys/arc
Module Name:src
Committed By: jakllsch
Date: Sat May 19 16:51:32 UTC 2018
Modified Files:
src/sys/arch/x86/x86: x86_tlb.c
Log Message:
remove more vestiges of uvm_emap_*(), to fix x86 kernel linking
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch
Module Name:src
Committed By: pgoyette
Date: Tue May 1 10:15:27 UTC 2018
Modified Files:
src/sys/arch/x86/conf: files.x86
Log Message:
Make MPVERBOSE a defparam rather than defflag. It has multiple
non-zero usages within mpacpi.c
To generate a diff of this commit:
cvs
Module Name:src
Committed By: nonaka
Date: Mon Apr 16 09:12:52 UTC 2018
Modified Files:
src/sys/arch/x86/pci: if_vmx.c
Log Message:
vmx(4): compute if_ibytes using rxq->vxrxq_stats.vmrxs_ibytes.
To generate a diff of this commit:
cvs rdiff -u -r1.23 -r1.24 src/sys/arch/x
Module Name:src
Committed By: nonaka
Date: Mon Apr 16 09:10:42 UTC 2018
Modified Files:
src/sys/arch/x86/pci: if_vmx.c
Log Message:
vmx(4): handled SIOCZIFDATA.
To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/x86/pci/if_vmx.c
Please note that
Module Name:src
Committed By: nonaka
Date: Mon Apr 16 03:21:43 UTC 2018
Modified Files:
src/sys/arch/x86/pci: if_vmx.c
Log Message:
vmx(4): Fix calculation of interface statistics counter.
To generate a diff of this commit:
cvs rdiff -u -r1.21 -r1.22 src/sys/arch/x86/pci
Module Name:src
Committed By: nonaka
Date: Fri Apr 13 11:24:34 UTC 2018
Modified Files:
src/sys/arch/x86/include: bootinfo.h
Log Message:
x86: Increase BOOTINFO_MAXSIZE to 8Kib.
Proposed on port-i386 and port-amd64 with no objections:
http://mail-index.netbsd.org/port-i38
Module Name:src
Committed By: msaitoh
Date: Thu Apr 12 10:30:24 UTC 2018
Modified Files:
src/sys/arch/x86/x86: cpu_ucode_intel.c
Log Message:
Add cpu_ucode_intel_verify() to verify microcode image. Currently, we don't
verify extended signatures'checksum. I have no any ima
Module Name:src
Committed By: nonaka
Date: Wed Apr 11 10:34:20 UTC 2018
Modified Files:
src/sys/arch/x86/pci: pci_machdep.c
Log Message:
efiboot reports parent ppb bus/device/function of booted network inteface.
To generate a diff of this commit:
cvs rdiff -u -r1.79 -r1.
Module Name:src
Committed By: kamil
Date: Sun Apr 8 14:21:23 UTC 2018
Modified Files:
src/sys/arch/x86/x86: dbregs.c
Log Message:
Add paranoid code to X86 Debug Registers
Reset certain bits in DR6 and DR7 in x86_dbregs_setup_initdbstate().
Reset X86_BREAKPOINT_CONDITION
Module Name:src
Committed By: maxv
Date: Thu Apr 5 15:04:29 UTC 2018
Modified Files:
src/sys/arch/x86/x86: spectre.c
Log Message:
Set the "method" string at boot time too.
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/x86/x86/spectre.c
Pleas
Module Name:src
Committed By: maxv
Date: Thu Apr 5 14:14:27 UTC 2018
Modified Files:
src/sys/arch/x86/x86: dbregs.c
Log Message:
Hum, don't let userland set bit 13, because this can crash the kernel.
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/ar
Module Name:src
Committed By: maxv
Date: Thu Apr 5 14:11:20 UTC 2018
Modified Files:
src/sys/arch/x86/x86: dbregs.c
Log Message:
Fix the check, should be >=.
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/x86/x86/dbregs.c
Please note that diff
Module Name:src
Committed By: maxv
Date: Wed Apr 4 16:23:27 UTC 2018
Modified Files:
src/sys/arch/x86/x86: spectre.c x86_machdep.c
Log Message:
Add machdep.spectre_v2.method, a string that tells which method is
active.
To generate a diff of this commit:
cvs rdiff -u -r1
Module Name:src
Committed By: maxv
Date: Sat Mar 31 08:43:52 UTC 2018
Modified Files:
src/sys/arch/x86/x86: x86_machdep.c
Log Message:
Rename spectreV2 -> spectre_v2, and introduce spectre_v1 (which defaults
to not-mitigated).
This gives the user an easy way to find out w
Module Name:src
Committed By: maxv
Date: Sat Mar 31 08:30:01 UTC 2018
Modified Files:
src/sys/arch/x86/x86: spectre.c
Log Message:
Reorganize to simplify.
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/x86/x86/spectre.c
Please note that diffs a
Module Name:src
Committed By: maxv
Date: Sat Mar 31 07:15:47 UTC 2018
Modified Files:
src/sys/arch/x86/x86: spectre.c
Log Message:
Add #ifdef, for i386 not to panic.
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/x86/x86/spectre.c
Please note t
Module Name:src
Committed By: maxv
Date: Fri Mar 30 19:58:05 UTC 2018
Modified Files:
src/sys/arch/x86/x86: svs.c
Log Message:
Improve the detection. Future generations of Intel CPUs will have a bit to
say they are not affected by Meltdown.
To generate a diff of this com
Module Name:src
Committed By: maxv
Date: Fri Mar 30 19:51:53 UTC 2018
Modified Files:
src/sys/arch/x86/include: cpu.h
src/sys/arch/x86/x86: identcpu.c
Log Message:
Retrieve cpuid.7:%edx.
To generate a diff of this commit:
cvs rdiff -u -r1.89 -r1.90 src/sys/arch/x
Module Name:src
Committed By: maxv
Date: Fri Mar 30 19:49:49 UTC 2018
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Add RDCL_NO and IBRS_ALL.
To generate a diff of this commit:
cvs rdiff -u -r1.119 -r1.120 src/sys/arch/x86/include/specialreg.h
Plea
Module Name:src
Committed By: msaitoh
Date: Fri Mar 30 09:30:57 UTC 2018
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Add Some bit definitions of AMD Fn8001 %edx:
- MMX
- FXSR
To generate a diff of this commit:
cvs rdiff -u -r1.118 -r1.119 sr
Module Name:src
Committed By: msaitoh
Date: Fri Mar 30 09:28:37 UTC 2018
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
>From the latest Intel SDM:
- Add Intel Fn_0006 %eax new bit 14-20 (HWP stuff).
- Intel Fn_0007 %ecx bit 22 is for both RDPI
Module Name:src
Committed By: maxv
Date: Thu Mar 29 07:24:26 UTC 2018
Modified Files:
src/sys/arch/x86/x86: svs.c
Log Message:
Use EOPNOTSUPP instead of EINVAL.
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/x86/x86/svs.c
Please note that dif
Module Name:src
Committed By: maxv
Date: Thu Mar 29 07:15:12 UTC 2018
Modified Files:
src/sys/arch/x86/x86: spectre.c svs.c
Log Message:
Fix sysctl type, should be bool.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/x86/x86/spectre.c
cvs rdiff
Module Name:src
Committed By: maxv
Date: Wed Mar 28 19:50:57 UTC 2018
Modified Files:
src/sys/arch/x86/x86: spectre.c
Log Message:
oldlwp can be NULL, so ensure it isn't.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/x86/x86/spectre.c
Please n
Module Name:src
Committed By: maxv
Date: Wed Mar 28 19:47:54 UTC 2018
Modified Files:
src/sys/arch/x86/x86: cpu_ucode.c
Log Message:
Add 'break', otherwise we're not gonna go very far. While here use a less
error-prone syntax.
To generate a diff of this commit:
cvs rdiff
Module Name:src
Committed By: maxv
Date: Wed Mar 28 14:56:59 UTC 2018
Modified Files:
src/sys/arch/x86/conf: files.x86
src/sys/arch/x86/x86: cpu.c
Added Files:
src/sys/arch/x86/x86: spectre.c
Log Message:
Move the SpectreV2 mitigation code into a dedicated
Module Name:src
Committed By: knakahara
Date: Mon Mar 26 02:30:08 UTC 2018
Modified Files:
src/sys/arch/x86/x86: intr.c
Log Message:
Fix "intrctl list" causes panic while attaching MSI/MSI-X devices.
When there are devices which is already pci_intr_alloc'ed, however is no
Module Name:src
Committed By: christos
Date: Sat Mar 17 20:02:32 UTC 2018
Modified Files:
src/sys/arch/x86/x86: cpu_ucode.c
Log Message:
dedup and handle XEN here.
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/x86/x86/cpu_ucode.c
Please note t
Module Name:src
Committed By: christos
Date: Sat Mar 17 15:56:32 UTC 2018
Modified Files:
src/sys/arch/x86/include: cpu_ucode.h
src/sys/arch/x86/x86: cpu_ucode.c cpu_ucode_amd.c cpu_ucode_intel.c
Log Message:
tuck in all the compat microcode code in one place.
To
Module Name:src
Committed By: ozaki-r
Date: Fri Mar 16 04:48:19 UTC 2018
Modified Files:
src/sys/arch/x86/x86: db_memrw.c
Log Message:
x86: avoid accessing invalid addresses in ddb like arm32
This avoids that a command stops in the middle of an execution if
a fault occurs
Module Name:src
Committed By: maya
Date: Thu Mar 15 23:57:18 UTC 2018
Modified Files:
src/sys/arch/x86/pci/imcsmb: imc.c
Log Message:
Provide a default case also when building imc as builtin.
Fixes ALL kernel build. ok pgoyette.
To generate a diff of this commit:
cvs rd
Module Name:src
Committed By: maxv
Date: Thu Mar 15 09:17:31 UTC 2018
Modified Files:
src/sys/arch/x86/x86: cpu.c
Log Message:
Remove #ifdef XEN (Xen has its own cpu.c), and add a comment.
To generate a diff of this commit:
cvs rdiff -u -r1.151 -r1.152 src/sys/arch/x86/x
Module Name:src
Committed By: ozaki-r
Date: Thu Mar 15 03:45:05 UTC 2018
Modified Files:
src/sys/arch/x86/x86: db_memrw.c
Log Message:
Use db_printf instead of printf in ddb
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/x86/x86/db_memrw.c
Plea
Module Name:src
Committed By: maxv
Date: Wed Mar 14 17:40:41 UTC 2018
Modified Files:
src/sys/arch/x86/x86: cpu.c x86_machdep.c
Log Message:
Spectre V2 mitigation for certain families of AMD CPUs.
A new sysctl is added, machdep.spectreV2.mitigated, that controls whether
S
Module Name:src
Committed By: maxv
Date: Wed Mar 14 15:03:16 UTC 2018
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
... and also add IBPB ...
To generate a diff of this commit:
cvs rdiff -u -r1.116 -r1.117 src/sys/arch/x86/include/specialreg.h
Plea
Module Name:src
Committed By: maxv
Date: Wed Mar 14 14:44:25 UTC 2018
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Add the IBRS and STIBP MSRs.
To generate a diff of this commit:
cvs rdiff -u -r1.115 -r1.116 src/sys/arch/x86/include/specialreg.h
P
Module Name:src
Committed By: maxv
Date: Wed Mar 14 14:15:02 UTC 2018
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Add IC_CFG.DIS_IND: "Disable Indirect Branch Predictor". Available (at
least) on AMD Families 10h, 12h and 16h.
To generate a diff of
Module Name:src
Committed By: maxv
Date: Tue Mar 13 16:52:42 UTC 2018
Modified Files:
src/sys/arch/x86/x86: patch.c
Log Message:
Fix wrong order; first enable WP, then enable interrupts. Otherwise we
might get an interrupt before re-enabling WP, and be rescheduled as a
res
Module Name:src
Committed By: maxv
Date: Tue Mar 13 16:45:52 UTC 2018
Modified Files:
src/sys/arch/x86/x86: svs.c
Log Message:
Mmh, add a missing x86_disable_intr(). My intention there was to ensure
interrupts were disabled before the barriers.
To generate a diff of this
Module Name:src
Committed By: msaitoh
Date: Mon Mar 12 07:35:45 UTC 2018
Modified Files:
src/sys/arch/x86/include: cacheinfo.h
Log Message:
AMD L3 cache association bitfield is not 8bit but 4bit like others association
bitfields.
To generate a diff of this commit:
cvs r
Module Name:src
Committed By: msaitoh
Date: Mon Mar 12 07:12:54 UTC 2018
Modified Files:
src/sys/arch/x86/include: specialreg.h
src/sys/arch/x86/x86: identcpu.c
Log Message:
s/CLFUSH/CLFLUSH/
No functional change.
To generate a diff of this commit:
cvs rdiff -u -
Module Name:src
Committed By: msaitoh
Date: Mon Mar 12 06:20:33 UTC 2018
Modified Files:
src/sys/arch/x86/include: cacheinfo.h
Log Message:
Add 3way and 6way of L2 cache or TLB on AMD CPU.
To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/x86/in
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