CVS commit: [netbsd-9] src/sys/arch/x86/include
Module Name:src
Committed By: martin
Date: Sat Jul 29 09:48:51 UTC 2023
Modified Files:
src/sys/arch/x86/include [netbsd-9]: specialreg.h
Log Message:
Pull up the following revisions, all via patch, requested by msaitoh
in ticket #1669:
sys/arch/x86/include/specialreg.h 1.204-1.206, 1.208
- Add Intel CPUID 0x07 %ecx bit 24 BUS_LOCK_DETECT.
- Add AMD CPUID 0x8008 %ebx bit 30 IBPB_RET and CPUID 0x800a
%edx bit 29 BusLockThreshold.
- Fix typo in comment.
To generate a diff of this commit:
cvs rdiff -u -r1.150.2.14 -r1.150.2.15 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.150.2.14 src/sys/arch/x86/include/specialreg.h:1.150.2.15
--- src/sys/arch/x86/include/specialreg.h:1.150.2.14 Tue Jul 25 09:12:35 2023
+++ src/sys/arch/x86/include/specialreg.h Sat Jul 29 09:48:51 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.150.2.14 2023/07/25 09:12:35 martin Exp $ */
+/* $NetBSD: specialreg.h,v 1.150.2.15 2023/07/29 09:48:51 martin Exp $ */
/*
* Copyright (c) 2014-2020 The NetBSD Foundation, Inc.
@@ -466,6 +466,7 @@
#define CPUID_SEF_MAWAU __BITS(21, 17) /* MAWAU for BND{LD,ST}X */
#define CPUID_SEF_RDPID __BIT(22) /* RDPID and IA32_TSC_AUX */
#define CPUID_SEF_KL __BIT(23) /* Key Locker */
+#define CPUID_SEF_BUS_LOCK_DETECT __BIT(24) /* OS bus-lock detection */
#define CPUID_SEF_CLDEMOTE __BIT(25) /* Cache line demote */
#define CPUID_SEF_MOVDIRI __BIT(27) /* MOVDIRI instruction */
#define CPUID_SEF_MOVDIR64B __BIT(28) /* MOVDIR64B instruction */
@@ -480,7 +481,7 @@
"b\14AVX512_BITALG\0" "b\15TME_EN\0" "b\16AVX512_VPOPCNTDQ\0" \
"b\20LA57\0" \
"f\21\5MAWAU\0" "b\26RDPID\0" "b\27KL\0" \
- "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \
+ "b\30BUS_LOCK_DETECT" "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \
"b\34MOVDIR64B\0" "b\35ENQCMD\0" "b\36SGXLC\0" "b\37PKS\0"
/* %ecx = 0, %edx */
@@ -889,6 +890,7 @@
#define CPUID_CAPEX_CPPC __BIT(27) /* Collaborative Processor Perf. Control */
#define CPUID_CAPEX_PSFD __BIT(28) /* Predictive Store Forward Dis */
#define CPUID_CAPEX_BTC_NO __BIT(29) /* Branch Type Confusion NO */
+#define CPUID_CAPEX_IBPB_RET __BIT(30) /* Clear RET address predictor */
#define CPUID_CAPEX_FLAGS "\20" \
"\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" "\4INVLPGB" \
@@ -899,7 +901,7 @@
"\24IBRS_SAMEMODE" \
"\25EFER_LSMSLE_UN""\30PPIN" \
"\31SSBD" "\32VIRT_SSBD" "\33SSB_NO" "\34CPPC" \
- "\35PSFD" "\36BTC_NO"
+ "\35PSFD" "\36BTC_NO" "\37IBPB_RET"
/* %ecx */
#define CPUID_CAPEX_PerfTscSize __BITS(17,16) /* Perf. tstamp counter size */
@@ -939,6 +941,7 @@
#define CPUID_AMD_SVM_IBSVIRT __BIT(26) /* IBS Virtualization */
#define CPUID_AMD_SVM_XLVTOFFFLTCHG __BIT(27) /* Ext LVToffset FLT changed */
#define CPUID_AMD_SVM_VMCBADRCHKCHG __BIT(28) /* VMCB addr check changed */
+#define CPUID_AMD_SVM_BUSLOCKTHRESH __BIT(29) /* Bus Lock Threshold */
#define CPUID_AMD_SVM_FLAGS "\20" \
@@ -951,7 +954,7 @@
"\21" "VGIF" "\22" "GMET" "\23x2AVIC" "\24SSSCHECK" \
"\25" "SPEC_CTRL" "\26" "ROGPT" "\30HOST_MCE_OVERRIDE" \
"\31" "TLBICTL" "\32VNMI" "\33IBSVIRT" "\34ExtLvtOffsetFaultChg" \
- "\35VmcbAddrChkChg"
+ "\35VmcbAddrChkChg" "\36BusLockThreshold"
/*
* AMD Instruction-Based Sampling Capabilities.
@@ -1065,7 +1068,7 @@
#define CPUID_AMDEXT2_FSRC __BIT(11) /* Fast Short Rep Cmpsb */
#define CPUID_AMDEXT2_PREFETCHCTL __BIT(13) /* Prefetch control MSR */
#define CPUID_AMDEXT2_CPUIDUSRDIS __BIT(17) /* CPUID dis. for non-priv. soft */
-#define CPUID_AMDEXT2_EPSF __BIT(18) /* Enhanced Predective Store Fwd */
+#define CPUID_AMDEXT2_EPSF __BIT(18) /* Enhanced Predictive Store Fwd */
#define CPUID_AMDEXT2_FLAGS "\20" \
"\1NoNestedDataBp" "\2FsGsKernelGsBaseNonSerializing" \
CVS commit: [netbsd-9] src/sys/arch/x86/include
Module Name:src Committed By: martin Date: Sat Jul 29 09:48:51 UTC 2023 Modified Files: src/sys/arch/x86/include [netbsd-9]: specialreg.h Log Message: Pull up the following revisions, all via patch, requested by msaitoh in ticket #1669: sys/arch/x86/include/specialreg.h 1.204-1.206, 1.208 - Add Intel CPUID 0x07 %ecx bit 24 BUS_LOCK_DETECT. - Add AMD CPUID 0x8008 %ebx bit 30 IBPB_RET and CPUID 0x800a %edx bit 29 BusLockThreshold. - Fix typo in comment. To generate a diff of this commit: cvs rdiff -u -r1.150.2.14 -r1.150.2.15 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/include
Module Name:src Committed By: martin Date: Mon Jan 23 13:00:53 UTC 2023 Modified Files: src/sys/arch/x86/include [netbsd-9]: specialreg.h Log Message: Pull up the following revisions, requested by msaitoh in ticket #1574: sys/arch/x86/include/specialreg.h 1.193-1.198 - Add CPUID Fn_0006 %eax bit 24 IA32_THERM_INTERRUPT MSR bit 25 Hardware Feedback Notification support. - Add CPUID Fn_0007 %ecx bit 29 ENQCMD. - Add CPUID Fn_0007 %edx bit 1 SGX-KEYS. - Add CPUID Fn_0007 %edx bit 5 UINTR(User INTeRrupts). - Add CPUID Fn_0007 %edx bit 11 RTM_ALWAYS_ABORT. - Add CPUID Fn_0007 %edx bit 22 AMX_BF16. - Add CPUID Fn_0007 %edx bit 23 AVX512_FP16. - Add CPUID Fn_0007 %edx bit 24 AMX_TILE. - Add CPUID Fn_0007 %edx bit 25 AMX_INT8. - Add CPUID Fn_0007 sub-leaf 1 %edx bit 18 CET_SSS. - Add CPUID Fn_0007 sub-leaf 2 %edx definitions. - Add CPUID Fn_000d sub-leaf 1 %eax bit 4 XFD. - Add CPUID Fn_001d Tile Information. - Add CPUID Fn_001e TMUL Information. - Add CPUID Fn8000_0007 %eax RAS capabilities. - Add CPUID Fn8000_0008 %ebx BTC_NO, - Add cpuid Fn8000_000a x2AVIC, VNMI, IBSVIRT and ROGPT. - Add CPUID Fn8000_001b Instruction-Based Sampling. - Add CPUID Fn8000_001e Processor Topology Information. - Add CPUID Fn8000_001f %eax RPMQUERY, VmplSSS, TscAuxVirt, VmgexitParam, VirtualTomMsr, IbsVirtGuest, SmtProtection, vsmCommPageMSR and NestedVirtSnpMsr. - Add CPUID Fn8000_0021 AMD Extended Features Identification 2. - Add CPUID Fn8000_0022 AMD Extended Performance Monitoring and Debug. - Rename HW_FEEDBACK to HWI (Hardware Feedback Interface). - Rename TSX_FORCE_ABORT to RTM_FORCE_ABORT. - Modify comment. Both Intel and AMD support CPUID Fn000b. - Modify comment. Hybrid Information -> Native Model ID Information. - Use __BIT(). Add comment. Whitespace fix. To generate a diff of this commit: cvs rdiff -u -r1.150.2.11 -r1.150.2.12 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/include
Module Name:src Committed By: martin Date: Mon Jan 23 13:00:53 UTC 2023 Modified Files: src/sys/arch/x86/include [netbsd-9]: specialreg.h Log Message: Pull up the following revisions, requested by msaitoh in ticket #1574: sys/arch/x86/include/specialreg.h 1.193-1.198 - Add CPUID Fn_0006 %eax bit 24 IA32_THERM_INTERRUPT MSR bit 25 Hardware Feedback Notification support. - Add CPUID Fn_0007 %ecx bit 29 ENQCMD. - Add CPUID Fn_0007 %edx bit 1 SGX-KEYS. - Add CPUID Fn_0007 %edx bit 5 UINTR(User INTeRrupts). - Add CPUID Fn_0007 %edx bit 11 RTM_ALWAYS_ABORT. - Add CPUID Fn_0007 %edx bit 22 AMX_BF16. - Add CPUID Fn_0007 %edx bit 23 AVX512_FP16. - Add CPUID Fn_0007 %edx bit 24 AMX_TILE. - Add CPUID Fn_0007 %edx bit 25 AMX_INT8. - Add CPUID Fn_0007 sub-leaf 1 %edx bit 18 CET_SSS. - Add CPUID Fn_0007 sub-leaf 2 %edx definitions. - Add CPUID Fn_000d sub-leaf 1 %eax bit 4 XFD. - Add CPUID Fn_001d Tile Information. - Add CPUID Fn_001e TMUL Information. - Add CPUID Fn8000_0007 %eax RAS capabilities. - Add CPUID Fn8000_0008 %ebx BTC_NO, - Add cpuid Fn8000_000a x2AVIC, VNMI, IBSVIRT and ROGPT. - Add CPUID Fn8000_001b Instruction-Based Sampling. - Add CPUID Fn8000_001e Processor Topology Information. - Add CPUID Fn8000_001f %eax RPMQUERY, VmplSSS, TscAuxVirt, VmgexitParam, VirtualTomMsr, IbsVirtGuest, SmtProtection, vsmCommPageMSR and NestedVirtSnpMsr. - Add CPUID Fn8000_0021 AMD Extended Features Identification 2. - Add CPUID Fn8000_0022 AMD Extended Performance Monitoring and Debug. - Rename HW_FEEDBACK to HWI (Hardware Feedback Interface). - Rename TSX_FORCE_ABORT to RTM_FORCE_ABORT. - Modify comment. Both Intel and AMD support CPUID Fn000b. - Modify comment. Hybrid Information -> Native Model ID Information. - Use __BIT(). Add comment. Whitespace fix. To generate a diff of this commit: cvs rdiff -u -r1.150.2.11 -r1.150.2.12 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.150.2.11 src/sys/arch/x86/include/specialreg.h:1.150.2.12 --- src/sys/arch/x86/include/specialreg.h:1.150.2.11 Sat Oct 15 10:08:40 2022 +++ src/sys/arch/x86/include/specialreg.h Mon Jan 23 13:00:53 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.150.2.11 2022/10/15 10:08:40 martin Exp $ */ +/* $NetBSD: specialreg.h,v 1.150.2.12 2023/01/23 13:00:53 martin Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -124,21 +124,21 @@ /* * Extended Control Register XCR0 */ -#define XCR0_X87 0x0001 /* x87 FPU/MMX state */ -#define XCR0_SSE 0x0002 /* SSE state */ -#define XCR0_YMM_Hi128 0x0004 /* AVX-256 (ymmn registers) */ -#define XCR0_BNDREGS 0x0008 /* Memory protection ext bounds */ -#define XCR0_BNDCSR 0x0010 /* Memory protection ext state */ -#define XCR0_Opmask 0x0020 /* AVX-512 Opmask */ -#define XCR0_ZMM_Hi256 0x0040 /* AVX-512 upper 256 bits low regs */ -#define XCR0_Hi16_ZMM 0x0080 /* AVX-512 512 bits upper registers */ -#define XCR0_PT 0x0100 /* Processor Trace state */ -#define XCR0_PKRU 0x0200 /* Protection Key state */ -#define XCR0_CET_U 0x0800 /* User CET state */ -#define XCR0_CET_S 0x1000 /* Kern CET state */ -#define XCR0_HDC 0x2000 /* Hardware Duty Cycle state */ -#define XCR0_LBR 0x8000 /* Last Branch Record */ -#define XCR0_HWP 0x0001 /* Hardware P-states */ +#define XCR0_X87 __BIT(0) /* x87 FPU/MMX state */ +#define XCR0_SSE __BIT(1) /* SSE state */ +#define XCR0_YMM_Hi128 __BIT(2) /* AVX-256 (ymmn registers) */ +#define XCR0_BNDREGS __BIT(3) /* Memory protection ext bounds */ +#define XCR0_BNDCSR __BIT(4) /* Memory protection ext state */ +#define XCR0_Opmask __BIT(5) /* AVX-512 Opmask */ +#define XCR0_ZMM_Hi256 __BIT(6) /* AVX-512 upper 256 bits low regs */ +#define XCR0_Hi16_ZMM __BIT(7) /* AVX-512 512 bits upper registers */ +#define XCR0_PT __BIT(8) /* Processor Trace state */ +#define XCR0_PKRU __BIT(9) /* Protection Key state */ +#define XCR0_CET_U __BIT(11) /* User CET state */ +#define XCR0_CET_S __BIT(12) /* Kern CET state */ +#define XCR0_HDC __BIT(13) /* Hardware Duty Cycle state */ +#define XCR0_LBR __BIT(15) /* Last Branch Record */ +#define XCR0_HWP __BIT(16) /* Hardware P-states */ #define XCR0_FLAGS1 "\20" \ "\1" "x87" "\2" "SSE" "\3" "AVX" "\4" "BNDREGS" \ @@ -224,38 +224,38 @@ #endif /* %ecx */ -#define CPUID2_SSE3 0x0001 /* Streaming SIMD Extensions 3 */ -#define CPUID2_PCLMULQDQ 0x0002 /* PCLMULQDQ instructions */ -#define CPUID2_DTES64 0x0004 /* 64-bit Debug Trace */ -#define CPUID2_MONITOR 0x0008 /* MONITOR/MWAIT instructions */ -#define CPUID2_DS_CPL 0x0010 /* CPL Qualified Debug Store */ -#define CPUID2_VMX 0x0020 /* Virtual Machine eXtensions */ -#define
CVS commit: [netbsd-9] src/sys/arch/x86/include
Module Name:src Committed By: martin Date: Mon Jan 31 17:42:18 UTC 2022 Modified Files: src/sys/arch/x86/include [netbsd-9]: specialreg.h Log Message: Pull up the following revisions (all via patch), requested by msaitoh in ticket #1417: sys/arch/x86/include/specialreg.h 1.179-1.188 - Add CPUID definitions of Last Branch Record, Thread Director, AVX version of VNNI, Fast short REP MOV, HRESET, PPIN, Architectural LBR, Linear Address Masking and Hybrid Information from the latest Intel SDM. - Add CPUID definitions of AddrMaskExt, INT_WBINVD, IbrsSameMode, EferLmsleUnsupported, PSFD and SecureTSC from AMD APM. - Print CLFSH instead of CLFLUSH because both Intel and AMD documents say so. - Modify comment. Add comment. Fix typo. Use __BIT(). KNF. Sort lines. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.150.2.9 -r1.150.2.10 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.150.2.9 src/sys/arch/x86/include/specialreg.h:1.150.2.10 --- src/sys/arch/x86/include/specialreg.h:1.150.2.9 Wed Dec 8 15:44:16 2021 +++ src/sys/arch/x86/include/specialreg.h Mon Jan 31 17:42:17 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.150.2.9 2021/12/08 15:44:16 martin Exp $ */ +/* $NetBSD: specialreg.h,v 1.150.2.10 2022/01/31 17:42:17 martin Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -97,29 +97,29 @@ /* * CR4 */ -#define CR4_VME 0x0001 /* virtual 8086 mode extension enable */ -#define CR4_PVI 0x0002 /* protected mode virtual interrupt enable */ -#define CR4_TSD 0x0004 /* restrict RDTSC instruction to cpl 0 */ -#define CR4_DE 0x0008 /* debugging extension */ -#define CR4_PSE 0x0010 /* large (4MB) page size enable */ -#define CR4_PAE 0x0020 /* physical address extension enable */ -#define CR4_MCE 0x0040 /* machine check enable */ -#define CR4_PGE 0x0080 /* page global enable */ -#define CR4_PCE 0x0100 /* enable RDPMC instruction for all cpls */ -#define CR4_OSFXSR 0x0200 /* enable fxsave/fxrestor and SSE */ -#define CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */ -#define CR4_UMIP 0x0800 /* user-mode instruction prevention */ +#define CR4_VME 0x0001 /* Virtual 8086 mode extension enable */ +#define CR4_PVI 0x0002 /* Protected mode virtual interrupt enable */ +#define CR4_TSD 0x0004 /* Restrict RDTSC instruction to cpl 0 */ +#define CR4_DE 0x0008 /* Debugging extension */ +#define CR4_PSE 0x0010 /* Large (4MB) page size enable */ +#define CR4_PAE 0x0020 /* Physical address extension enable */ +#define CR4_MCE 0x0040 /* Machine check enable */ +#define CR4_PGE 0x0080 /* Page global enable */ +#define CR4_PCE 0x0100 /* Enable RDPMC instruction for all cpls */ +#define CR4_OSFXSR 0x0200 /* Enable fxsave/fxrestor and SSE */ +#define CR4_OSXMMEXCPT 0x0400 /* Enable unmasked SSE exceptions */ +#define CR4_UMIP 0x0800 /* User Mode Instruction Prevention */ #define CR4_LA57 0x1000 /* 57-bit linear addresses */ -#define CR4_VMXE 0x2000 /* enable VMX operations */ -#define CR4_SMXE 0x4000 /* enable SMX operations */ -#define CR4_FSGSBASE 0x0001 /* enable *FSBASE and *GSBASE instructions */ -#define CR4_PCIDE 0x0002 /* enable Process Context IDentifiers */ -#define CR4_OSXSAVE 0x0004 /* enable xsave and xrestore */ -#define CR4_SMEP 0x0010 /* enable SMEP support */ -#define CR4_SMAP 0x0020 /* enable SMAP support */ -#define CR4_PKE 0x0040 /* enable Protection Keys for user pages */ -#define CR4_CET 0x0080 /* enable CET */ -#define CR4_PKS 0x0100 /* enable Protection Keys for kern pages */ +#define CR4_VMXE 0x2000 /* Enable VMX operations */ +#define CR4_SMXE 0x4000 /* Enable SMX operations */ +#define CR4_FSGSBASE 0x0001 /* Enable *FSBASE and *GSBASE instructions */ +#define CR4_PCIDE 0x0002 /* Enable Process Context IDentifiers */ +#define CR4_OSXSAVE 0x0004 /* Enable xsave and xrestore */ +#define CR4_SMEP 0x0010 /* Enable SMEP support */ +#define CR4_SMAP 0x0020 /* Enable SMAP support */ +#define CR4_PKE 0x0040 /* Enable Protection Keys for user pages */ +#define CR4_CET 0x0080 /* Enable CET */ +#define CR4_PKS 0x0100 /* Enable Protection Keys for kern pages */ /* * Extended Control Register XCR0 @@ -137,14 +137,15 @@ #define XCR0_CET_U 0x0800 /* User CET state */ #define XCR0_CET_S 0x1000 /* Kern CET state */ #define XCR0_HDC 0x2000 /* Hardware Duty Cycle state */ +#define XCR0_LBR 0x8000 /* Last Branch Record */ #define XCR0_HWP 0x0001 /* Hardware P-states */ -#define XCR0_FLAGS1 "\20" \ - "\1" "x87" "\2" "SSE" "\3" "AVX" \ - "\4" "BNDREGS" "\5" "BNDCSR"
CVS commit: [netbsd-9] src/sys/arch/x86/include
Module Name:src Committed By: martin Date: Mon Jan 31 17:42:18 UTC 2022 Modified Files: src/sys/arch/x86/include [netbsd-9]: specialreg.h Log Message: Pull up the following revisions (all via patch), requested by msaitoh in ticket #1417: sys/arch/x86/include/specialreg.h 1.179-1.188 - Add CPUID definitions of Last Branch Record, Thread Director, AVX version of VNNI, Fast short REP MOV, HRESET, PPIN, Architectural LBR, Linear Address Masking and Hybrid Information from the latest Intel SDM. - Add CPUID definitions of AddrMaskExt, INT_WBINVD, IbrsSameMode, EferLmsleUnsupported, PSFD and SecureTSC from AMD APM. - Print CLFSH instead of CLFLUSH because both Intel and AMD documents say so. - Modify comment. Add comment. Fix typo. Use __BIT(). KNF. Sort lines. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.150.2.9 -r1.150.2.10 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/include
Module Name:src Committed By: martin Date: Mon Jul 13 13:33:29 UTC 2020 Modified Files: src/sys/arch/x86/include [netbsd-9]: specialreg.h Log Message: Pull up following revision(s) (requested by msaitoh in ticket #998): sys/arch/x86/include/specialreg.h: revision 1.162 sys/arch/x86/include/specialreg.h: revision 1.164 sys/arch/x86/include/specialreg.h: revision 1.165 sys/arch/x86/include/specialreg.h: revision 1.166 sys/arch/x86/include/specialreg.h: revision 1.167 sys/arch/x86/include/specialreg.h: revision 1.168 - AMD CPUID Fn8000_000a %edx bit 20 is "SPEC_CTRL". - Add some bit definitions of AMD's CPUID Fn8000_001f Encrypted Memory features. - Add AMD INVLPGB/TLBSYNC hypervisor enable in VMCB and TLBSYNC intercept bit. - Modify comment. Add AMD MSR_DE_CFG's bit 1 as DE_CFG_LFENCE_SERIALIZE. This bit makes lfence instruction serializing. Add some definitions from the latest Intel SDM plus small fix: - Add CPUID leaf 6 %eax bit 19 for HW_FEEDBACK* and IA32_PACKAGE_TERM* MSRs. - Add CPUID leaf 7 %ecx bit 31 for Protection Keys. - Add definition of Load only TLB and Store only TLB. - Add IF_PSCHANGE_MC_NO bit of IA32_ARCH_CAPABILITIES - Fix HWP_IGNIDL. Add SRBDS_CTRL bit. style and fix typo To generate a diff of this commit: cvs rdiff -u -r1.150.2.6 -r1.150.2.7 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.150.2.6 src/sys/arch/x86/include/specialreg.h:1.150.2.7 --- src/sys/arch/x86/include/specialreg.h:1.150.2.6 Tue Apr 14 17:15:02 2020 +++ src/sys/arch/x86/include/specialreg.h Mon Jul 13 13:33:29 2020 @@ -1,7 +1,7 @@ -/* $NetBSD: specialreg.h,v 1.150.2.6 2020/04/14 17:15:02 martin Exp $ */ +/* $NetBSD: specialreg.h,v 1.150.2.7 2020/07/13 13:33:29 martin Exp $ */ /* - * Copyright (c) 2014-2019 The NetBSD Foundation, Inc. + * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -294,10 +294,10 @@ ? 0 : (CPUID_TO_EXTMODEL(cpuid) << 4))) /* CPUID Fn0001 %ebx */ -#define CPUID_BRAND_INDEX __BITS(7,0) -#define CPUID_CLFLUSH_SIZE __BITS(15,8) -#define CPUID_HTT_CORES __BITS(23,16) -#define CPUID_LOCAL_APIC_ID __BITS(31,24) +#define CPUID_BRAND_INDEX __BITS(7,0) +#define CPUID_CLFLUSH_SIZE __BITS(15,8) +#define CPUID_HTT_CORES __BITS(23,16) +#define CPUID_LOCAL_APIC_ID __BITS(31,24) /* * Intel Deterministic Cache Parameter Leaf @@ -367,6 +367,7 @@ #define CPUID_DSPM_HWP_PECI __BIT(16) /* HWP PECI override */ #define CPUID_DSPM_HWP_FLEX __BIT(17) /* Flexible HWP */ #define CPUID_DSPM_HWP_FAST __BIT(18) /* Fast access for IA32_HWP_REQUEST */ +#define CPUID_DSPM_HW_FEEDBACK __BIT(19) /* HW_FEEDBACK*, IA32_PACKAGE_TERM* */ #define CPUID_DSPM_HWP_IGNIDL __BIT(20) /* Ignore Idle Logical Processor HWP */ #define CPUID_DSPM_FLAGS "\20" \ @@ -374,8 +375,8 @@ "\5" "PLN" "\6" "ECMD" "\7" "PTM" "\10" "HWP" \ "\11" "HWP_NOTIFY" "\12" "HWP_ACTWIN" "\13" "HWP_EPP" "\14" "HWP_PLR" \ "\16" "HDC" "\17" "TBM3" "\20" "HWP_CAP" \ - "\21" "HWP_PECI" "\22" "HWP_FLEX" "\23" "HWP_FAST" \ - "25" "HWP_IGNIDL" + "\21" "HWP_PECI" "\22" "HWP_FLEX" "\23" "HWP_FAST" "\24HW_FEEDBACK" \ + "\25" "HWP_IGNIDL" /* * Intel/AMD Digital Thermal Sensor and @@ -388,7 +389,7 @@ /* * Intel/AMD Structured Extended Feature leaf Fn_0007 - * %eax == 0: Subleaf 0 + * %ecx == 0: Subleaf 0 * %eax: The Maximum input value for supported subleaf. * %ebx: Feature bits. * %ecx: Feature bits. @@ -460,6 +461,7 @@ #define CPUID_SEF_MOVDIRI __BIT(27) /* MOVDIRI instruction */ #define CPUID_SEF_MOVDIR64B __BIT(28) /* MOVDIR64B instruction */ #define CPUID_SEF_SGXLC __BIT(30) /* SGX Launch Configuration */ +#define CPUID_SEF_PKS __BIT(31) /* Protection Keys */ #define CPUID_SEF_FLAGS1 "\177\20" \ "b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0" \ @@ -469,13 +471,14 @@ "f\21\5MAWAU\0" \ "b\26RDPID\0" \ "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \ - "b\34MOVDIR64B\0" "b\36SGXLC\0" + "b\34MOVDIR64B\0" "b\36SGXLC\0" "b\37PKS\0" /* %edx */ #define CPUID_SEF_AVX512_4VNNIW __BIT(2) #define CPUID_SEF_AVX512_4FMAPS __BIT(3) #define CPUID_SEF_FSREP_MOV __BIT(4) /* Fast Short REP MOV */ #define CPUID_SEF_AVX512_VP2INTERSECT __BIT(8) +#define CPUID_SEF_SRBDS_CTRL __BIT(9) /* IA32_MCU_OPT_CTRL */ #define CPUID_SEF_MD_CLEAR __BIT(10) #define CPUID_SEF_TSX_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */ #define CPUID_SEF_SERIALIZE __BIT(14) @@ -492,7 +495,7 @@ #define CPUID_SEF_FLAGS2 "\20" \ "\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \ "\5" "FSREP_MOV" \ - "\11" "VP2INTERSECT" "\13" "MD_CLEAR" \ + "\11VP2INTERSECT" "\12SRBDS_CTRL" "\13MD_CLEAR" \
CVS commit: [netbsd-9] src/sys/arch/x86/include
Module Name:src Committed By: martin Date: Mon Jul 13 13:33:29 UTC 2020 Modified Files: src/sys/arch/x86/include [netbsd-9]: specialreg.h Log Message: Pull up following revision(s) (requested by msaitoh in ticket #998): sys/arch/x86/include/specialreg.h: revision 1.162 sys/arch/x86/include/specialreg.h: revision 1.164 sys/arch/x86/include/specialreg.h: revision 1.165 sys/arch/x86/include/specialreg.h: revision 1.166 sys/arch/x86/include/specialreg.h: revision 1.167 sys/arch/x86/include/specialreg.h: revision 1.168 - AMD CPUID Fn8000_000a %edx bit 20 is "SPEC_CTRL". - Add some bit definitions of AMD's CPUID Fn8000_001f Encrypted Memory features. - Add AMD INVLPGB/TLBSYNC hypervisor enable in VMCB and TLBSYNC intercept bit. - Modify comment. Add AMD MSR_DE_CFG's bit 1 as DE_CFG_LFENCE_SERIALIZE. This bit makes lfence instruction serializing. Add some definitions from the latest Intel SDM plus small fix: - Add CPUID leaf 6 %eax bit 19 for HW_FEEDBACK* and IA32_PACKAGE_TERM* MSRs. - Add CPUID leaf 7 %ecx bit 31 for Protection Keys. - Add definition of Load only TLB and Store only TLB. - Add IF_PSCHANGE_MC_NO bit of IA32_ARCH_CAPABILITIES - Fix HWP_IGNIDL. Add SRBDS_CTRL bit. style and fix typo To generate a diff of this commit: cvs rdiff -u -r1.150.2.6 -r1.150.2.7 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/include
Module Name:src Committed By: martin Date: Sun Nov 10 13:06:47 UTC 2019 Modified Files: src/sys/arch/x86/include [netbsd-9]: specialreg.h Log Message: Pull up following revision(s) (requested by msaitoh in ticket #407): sys/arch/x86/include/specialreg.h: revision 1.156 - GMET is not bit 11 but 17. - Add unknown CPUID Fn8000_000a %edx bit 20. To generate a diff of this commit: cvs rdiff -u -r1.150.2.2 -r1.150.2.3 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/include
Module Name:src
Committed By: martin
Date: Sun Nov 10 13:06:47 UTC 2019
Modified Files:
src/sys/arch/x86/include [netbsd-9]: specialreg.h
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #407):
sys/arch/x86/include/specialreg.h: revision 1.156
- GMET is not bit 11 but 17.
- Add unknown CPUID Fn8000_000a %edx bit 20.
To generate a diff of this commit:
cvs rdiff -u -r1.150.2.2 -r1.150.2.3 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.150.2.2 src/sys/arch/x86/include/specialreg.h:1.150.2.3
--- src/sys/arch/x86/include/specialreg.h:1.150.2.2 Thu Oct 17 18:56:24 2019
+++ src/sys/arch/x86/include/specialreg.h Sun Nov 10 13:06:46 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.150.2.2 2019/10/17 18:56:24 martin Exp $ */
+/* $NetBSD: specialreg.h,v 1.150.2.3 2019/11/10 13:06:46 martin Exp $ */
/*
* Copyright (c) 2014-2019 The NetBSD Foundation, Inc.
@@ -755,19 +755,20 @@
#define CPUID_AMD_SVM_FlushByASID 0x0040
#define CPUID_AMD_SVM_DecodeAssist 0x0080
#define CPUID_AMD_SVM_PauseFilter 0x0400
-#define CPUID_AMD_SVM_GMET 0x0800
#define CPUID_AMD_SVM_PFThreshold 0x1000 /* PAUSE filter threshold */
#define CPUID_AMD_SVM_AVIC 0x2000 /* AMD Virtual intr. ctrl */
#define CPUID_AMD_SVM_V_VMSAVE_VMLOAD 0x8000 /* Virtual VM{SAVE/LOAD} */
#define CPUID_AMD_SVM_vGIF 0x0001 /* Virtualized GIF */
+#define CPUID_AMD_SVM_GMET 0x0002
#define CPUID_AMD_SVM_FLAGS "\20" \
"\1" "NP" "\2" "LbrVirt" "\3" "SVML" "\4" "NRIPS" \
"\5" "TSCRate" "\6" "VMCBCleanBits" \
"\7" "FlushByASID" "\10" "DecodeAssist" \
- "\11" "B08" "\12" "B09" "\13" "PauseFilter" "\14" "GMET" \
+ "\11" "B08" "\12" "B09" "\13" "PauseFilter" "\14" "B11" \
"\15" "PFThreshold" "\16" "AVIC" "\17" "B14" \
"\20" "V_VMSAVE_VMLOAD" \
- "\21" "VGIF"
+ "\21" "VGIF" "\22" "GMET" \
+ "\25" "B20"
/*
* AMD Fn8000_0001d Cache Topology Information.
CVS commit: [netbsd-9] src/sys/arch/x86/include
Module Name:src
Committed By: martin
Date: Wed Oct 16 17:32:17 UTC 2019
Modified Files:
src/sys/arch/x86/include [netbsd-9]: cpufunc.h
Log Message:
Pull up following revision(s) (requested by maxv in ticket #338):
sys/arch/x86/include/cpufunc.h: revision 1.35
Add a memory barrier on wrmsr, because some MSRs control memory access
rights (we don't use them though). Also add barriers on fninit and clts
for safety.
To generate a diff of this commit:
cvs rdiff -u -r1.34 -r1.34.2.1 src/sys/arch/x86/include/cpufunc.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cpufunc.h
diff -u src/sys/arch/x86/include/cpufunc.h:1.34 src/sys/arch/x86/include/cpufunc.h:1.34.2.1
--- src/sys/arch/x86/include/cpufunc.h:1.34 Fri Jul 5 17:08:55 2019
+++ src/sys/arch/x86/include/cpufunc.h Wed Oct 16 17:32:17 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.h,v 1.34 2019/07/05 17:08:55 maxv Exp $ */
+/* $NetBSD: cpufunc.h,v 1.34.2.1 2019/10/16 17:32:17 martin Exp $ */
/*
* Copyright (c) 1998, 2007, 2019 The NetBSD Foundation, Inc.
@@ -271,7 +271,7 @@ union savefpu;
static inline void
fninit(void)
{
- __asm volatile ("fninit");
+ __asm volatile ("fninit" ::: "memory");
}
static inline void
@@ -303,7 +303,7 @@ fnstsw(uint16_t *val)
static inline void
clts(void)
{
- __asm volatile ("clts");
+ __asm volatile ("clts" ::: "memory");
}
void stts(void);
@@ -433,6 +433,7 @@ wrmsr(u_int msr, uint64_t val)
"wrmsr"
:
: "a" (low), "d" (high), "c" (msr)
+ : "memory"
);
}
CVS commit: [netbsd-9] src/sys/arch/x86/include
Module Name:src Committed By: martin Date: Wed Oct 16 17:32:17 UTC 2019 Modified Files: src/sys/arch/x86/include [netbsd-9]: cpufunc.h Log Message: Pull up following revision(s) (requested by maxv in ticket #338): sys/arch/x86/include/cpufunc.h: revision 1.35 Add a memory barrier on wrmsr, because some MSRs control memory access rights (we don't use them though). Also add barriers on fninit and clts for safety. To generate a diff of this commit: cvs rdiff -u -r1.34 -r1.34.2.1 src/sys/arch/x86/include/cpufunc.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
