[PATCH] spi: spi-sh: add IORESOURCE_MEM_TYPE_MASK decoding for access size
This SPI controller's access size is 32, or 8-bit. The previous driver
supported 32-bit only. So, this patch adds IORESOURCE_MEM_TYPE_MASK
decoding, an then, the driver can handle the SPI controller of 8-bit.
This patch also changes the readl/writel to ioread*/iowrite*.
Signed-off-by: Yoshihiro Shimoda yoshihiro.shimoda...@renesas.com
---
drivers/spi/spi-sh.c | 25 +++--
1 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-sh.c b/drivers/spi/spi-sh.c
index 70c8af9..79442c3 100644
--- a/drivers/spi/spi-sh.c
+++ b/drivers/spi/spi-sh.c
@@ -92,17 +92,26 @@ struct spi_sh_data {
unsigned long cr1;
wait_queue_head_t wait;
spinlock_t lock;
+ int width;
};
static void spi_sh_write(struct spi_sh_data *ss, unsigned long data,
unsigned long offset)
{
- writel(data, ss-addr + offset);
+ if (ss-width == 8)
+ iowrite8(data, ss-addr + (offset 2));
+ else if (ss-width == 32)
+ iowrite32(data, ss-addr + offset);
}
static unsigned long spi_sh_read(struct spi_sh_data *ss, unsigned long offset)
{
- return readl(ss-addr + offset);
+ if (ss-width == 8)
+ return ioread8(ss-addr + (offset 2));
+ else if (ss-width == 32)
+ return ioread32(ss-addr + offset);
+ else
+ return 0;
}
static void spi_sh_set_bit(struct spi_sh_data *ss, unsigned long val,
@@ -464,6 +473,18 @@ static int __devinit spi_sh_probe(struct platform_device
*pdev)
ss = spi_master_get_devdata(master);
dev_set_drvdata(pdev-dev, ss);
+ switch (res-flags IORESOURCE_MEM_TYPE_MASK) {
+ case IORESOURCE_MEM_8BIT:
+ ss-width = 8;
+ break;
+ case IORESOURCE_MEM_32BIT:
+ ss-width = 32;
+ break;
+ default:
+ dev_err(pdev-dev, No support width\n);
+ ret = -ENODEV;
+ goto error1;
+ }
ss-irq = irq;
ss-master = master;
ss-addr = ioremap(res-start, resource_size(res));
--
1.7.1
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Re: [PATCH] spi: spi-sh: add IORESOURCE_MEM_TYPE_MASK decoding for access size
On Thu, Jan 26, 2012 at 05:43:57PM +0900, Shimoda, Yoshihiro wrote:
This SPI controller's access size is 32, or 8-bit. The previous driver
supported 32-bit only. So, this patch adds IORESOURCE_MEM_TYPE_MASK
decoding, an then, the driver can handle the SPI controller of 8-bit.
This patch also changes the readl/writel to ioread*/iowrite*.
Signed-off-by: Yoshihiro Shimoda yoshihiro.shimoda...@renesas.com
---
drivers/spi/spi-sh.c | 25 +++--
1 files changed, 23 insertions(+), 2 deletions(-)
..
static void spi_sh_set_bit(struct spi_sh_data *ss, unsigned long val,
@@ -464,6 +473,18 @@ static int __devinit spi_sh_probe(struct platform_device
*pdev)
ss = spi_master_get_devdata(master);
dev_set_drvdata(pdev-dev, ss);
+ switch (res-flags IORESOURCE_MEM_TYPE_MASK) {
+ case IORESOURCE_MEM_8BIT:
+ ss-width = 8;
+ break;
+ case IORESOURCE_MEM_32BIT:
+ ss-width = 32;
+ break;
+ default:
+ dev_err(pdev-dev, No support width\n);
+ ret = -ENODEV;
+ goto error1;
If the default up to this point has been 32-bit only then it makes sense
for 32 to still remain the default. The 8-bit user is presumably a new
one and therefore has no existing platform data configuration to worry
about, while this change would require existing users to be updated for
the new 32-bit flag to behave the same way they have up until now.
If you wish to do this incrementally then you can of course convert all
of the existing platforms to the new mechanism for 32-bit as well and
then simply error out as above for the undefined width case, but I still
think it makes more sense to have a usable default.
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Re: [PATCH] spi/pl022: Add high priority message pump support
On Wed, Jan 25, 2012 at 3:02 PM, Mark Brown broo...@sirena.org.uk wrote: On Tue, Jan 24, 2012 at 10:14:32PM +0100, Linus Walleij wrote: This switches the PL022 worker to a kthread in order to get hold of a mechanism to control the message pump priority. On low-latency systems elevating the message kthread to realtime priority give a real sleek response curve. This has been confirmed by measurements. Realtime priority elevation for a certain PL022 port can be requested from platform data. It really feels like we should be pulling this into the core - lots of drivers use a workqueue to drive data through the system and they're all going to have exactly the same issue. That reads to me like the entire message queue and transfer pump mechanism from the PL022 driver should be made into generic code. That is the key ingredient from the PL022 driver that has allowed us to get real nice throughput on it. And that observation is correct, but a bit of upfront code. If Grant is in on it I might give it a try. I would make it an opt-in for SPI drivers to have a generic message queue instead of treating messages in a one-by-one manner. So say I add to spi/Kconfig that SPI_MASTER:s can define SPI_MASTER_QUEUE then add a spi_alloc_queued_master() call with some new #ifdef SPI_MASTER_QUEUE functions and fields added to in the struct spi_master to handle this stuff, and compile in the message pump so that these drivers does not implement the .transfer() call, but instead some more fine-grained ones would that fit the bill? Yours, Linus Walleij -- Keep Your Developer Skills Current with LearnDevNow! The most comprehensive online learning library for Microsoft developers is just $99.99! Visual Studio, SharePoint, SQL - plus HTML5, CSS3, MVC3, Metro Style Apps, more. Free future releases when you subscribe now! http://p.sf.net/sfu/learndevnow-d2d ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH] spi/pl022: Add high priority message pump support
On Thu, Jan 26, 2012 at 03:48:59PM +0100, Linus Walleij wrote: On Wed, Jan 25, 2012 at 3:02 PM, Mark Brown broo...@sirena.org.uk wrote: It really feels like we should be pulling this into the core - lots of drivers use a workqueue to drive data through the system and they're all going to have exactly the same issue. That reads to me like the entire message queue and transfer pump mechanism from the PL022 driver should be made into generic code. That is the key ingredient from the PL022 driver that has allowed us to get real nice throughput on it. And that observation is correct, but a bit of upfront code. Probably, yes - lots of drivers seem to have a workqueue of some kind that drives the actual transfers and I strongly suspect that there's a lot of generality there. I have to confess that I had just thought that transfer pump was an obscure bit of jargon in the changelog so it's possible it's doing something device specific but it'd seem surprising TBH. I would make it an opt-in for SPI drivers to have a generic message queue instead of treating messages in a one-by-one manner. That'd certainly be nice - where things use a workqueue they do often just pass the entire request from the caller off to it in one fell swoop so that sounds compatible. -- Keep Your Developer Skills Current with LearnDevNow! The most comprehensive online learning library for Microsoft developers is just $99.99! Visual Studio, SharePoint, SQL - plus HTML5, CSS3, MVC3, Metro Style Apps, more. Free future releases when you subscribe now! http://p.sf.net/sfu/learndevnow-d2d ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH] intel_mid_ssp_spi: Moorestown and Medfield SPI for SSP devices
From: Mathieu SOULARD mathieux.soul...@intel.com
This driver is a fusion of various internal drivers into a single
driver for the SPI slave/master on the Intel Moorestown and Medfield
SSP devices.
Signed-off-by: Mathieu SOULARD mathieux.soul...@intel.com
[Queueing and runtime pm added]
Signed-off-by: Kristen Carlson Accardi kris...@linux.intel.com
[Ported to the -next tree DMA engine, stripped Moorestown, further cleanup]
Signed-off-by: Alan Cox a...@linux.intel.com
---
drivers/spi/Kconfig |8
drivers/spi/Makefile|2
drivers/spi/spi-intel-mid-ssp.c | 1426 +++
drivers/spi/spi-intel-mid-ssp.h | 308
4 files changed, 1743 insertions(+), 1 deletions(-)
create mode 100644 drivers/spi/spi-intel-mid-ssp.c
create mode 100644 drivers/spi/spi-intel-mid-ssp.h
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 3f9a47e..ed8363e 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -163,6 +163,14 @@ config SPI_IMX
This enables using the Freescale i.MX SPI controllers in master
mode.
+config SPI_INTEL_MID_SSP
+ tristate SSP SPI controller driver for Intel MID platforms
(EXPERIMENTAL)
+ depends on SPI_MASTER INTEL_MID_DMAC EXPERIMENTAL
+ help
+ This is the unified SSP SPI slave controller driver for the Intel
+ MID platforms, handling Moorestown Medfield, master slave
+ clock mode.
+
config SPI_LM70_LLP
tristate Parallel port adapter for LM70 eval board (DEVELOPMENT)
depends on PARPORT EXPERIMENTAL
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 61c3261..e81757a 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -58,4 +58,4 @@ obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x0.o
obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o
obj-$(CONFIG_SPI_TXX9) += spi-txx9.o
obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o
-
+obj-$(CONFIG_SPI_INTEL_MID_SSP)+= spi-intel-mid-ssp.o
diff --git a/drivers/spi/spi-intel-mid-ssp.c b/drivers/spi/spi-intel-mid-ssp.c
new file mode 100644
index 000..77bff9f
--- /dev/null
+++ b/drivers/spi/spi-intel-mid-ssp.c
@@ -0,0 +1,1426 @@
+/*
+ * This driver supports Bulverde SSP core used on Intel MID platforms
+ * It supports the SSP of Medfield platforms and handles clock
+ * slave master modes.
+ *
+ * Copyright (c) 2010, Intel Corporation.
+ * Ken Mills ken.k.mi...@intel.com
+ * Sylvain Centelles sylvain.centel...@intel.com
+ * Mathieu SOULARD
+ * Kristen Carlson Accardi kris...@linux.intel.com
+ * Alan Cox a...@linux.intel.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+/*
+ * Note:
+ *
+ * Supports DMA and non-interrupt polled transfers.
+ *
+ */
+
+#include linux/module.h
+#include linux/delay.h
+#include linux/interrupt.h
+#include linux/highmem.h
+#include linux/pci.h
+#include linux/init.h
+#include linux/interrupt.h
+#include linux/dma-mapping.h
+#include linux/intel_mid_dma.h
+#include linux/pm_qos.h
+#include linux/pm_runtime.h
+
+#include linux/spi/spi.h
+#include spi-intel-mid-ssp.h
+
+#define DRIVER_NAME spi-intel-mid-ssp
+
+MODULE_AUTHOR(Ken Mills);
+MODULE_DESCRIPTION(Bulverde SSP core SPI contoller);
+MODULE_LICENSE(GPL);
+
+static const struct pci_device_id pci_ids[];
+
+#ifdef DUMP_RX
+static void dump_trailer(const struct device *dev, char *buf, int len, int sz)
+{
+ int tlen1 = (len sz ? len : sz);
+ int tlen2 = ((len - sz) sz) ? sz : (len - sz);
+ unsigned char *p;
+ static char msg[MAX_SPI_TRANSFER_SIZE];
+
+ memset(msg, '\0', sizeof(msg));
+ p = buf;
+ while (p buf + tlen1)
+ sprintf(msg, %s%02x, msg, (unsigned int)*p++);
+
+ if (tlen2 0) {
+ sprintf(msg, %s ., msg);
+ p = (buf+len) - tlen2;
+ while (p buf + len)
+ sprintf(msg, %s%02x, msg, (unsigned int)*p++);
+ }
+
+ dev_info(dev, DUMP: %p[0:%d ... %d:%d]:%s, buf, tlen1 - 1,
+ len-tlen2, len - 1, msg);
+}
+#endif
+
+static inline u32 is_tx_fifo_empty(struct ssp_driver_context *drv_context)
+{
+ u32 sssr;
+ sssr = read_SSSR(drv_context-ioaddr);
+ if ((sssr SSSR_TFL_MASK) || (sssr SSSR_TNF) == 0)
+ return 0;
+ else
Re: [PATCH] intel_mid_ssp_spi: Moorestown and Medfield SPI for SSP devices
On Thu, Jan 26, 2012 at 10:57 AM, Alan Cox a...@lxorguk.ukuu.org.uk wrote: From: Mathieu SOULARD mathieux.soul...@intel.com This driver is a fusion of various internal drivers into a single driver for the SPI slave/master on the Intel Moorestown and Medfield SSP devices. Signed-off-by: Mathieu SOULARD mathieux.soul...@intel.com [Queueing and runtime pm added] Signed-off-by: Kristen Carlson Accardi kris...@linux.intel.com [Ported to the -next tree DMA engine, stripped Moorestown, further cleanup] Signed-off-by: Alan Cox a...@linux.intel.com --- drivers/spi/Kconfig | 8 drivers/spi/Makefile | 2 drivers/spi/spi-intel-mid-ssp.c | 1426 +++ drivers/spi/spi-intel-mid-ssp.h | 308 Haven't reviewed the patch yet, but I've got a question on this. Are there any other users of this header file? Can I just roll it into the .c file if I pick up the patch? g. -- Keep Your Developer Skills Current with LearnDevNow! The most comprehensive online learning library for Microsoft developers is just $99.99! Visual Studio, SharePoint, SQL - plus HTML5, CSS3, MVC3, Metro Style Apps, more. Free future releases when you subscribe now! http://p.sf.net/sfu/learndevnow-d2d ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH] intel_mid_ssp_spi: Moorestown and Medfield SPI for SSP devices
On Thu, 26 Jan 2012 12:18:41 -0700 Grant Likely grant.lik...@secretlab.ca wrote: On Thu, Jan 26, 2012 at 10:57 AM, Alan Cox a...@lxorguk.ukuu.org.uk wrote: From: Mathieu SOULARD mathieux.soul...@intel.com This driver is a fusion of various internal drivers into a single driver for the SPI slave/master on the Intel Moorestown and Medfield SSP devices. Signed-off-by: Mathieu SOULARD mathieux.soul...@intel.com [Queueing and runtime pm added] Signed-off-by: Kristen Carlson Accardi kris...@linux.intel.com [Ported to the -next tree DMA engine, stripped Moorestown, further cleanup] Signed-off-by: Alan Cox a...@linux.intel.com --- drivers/spi/Kconfig | 8 drivers/spi/Makefile | 2 drivers/spi/spi-intel-mid-ssp.c | 1426 +++ drivers/spi/spi-intel-mid-ssp.h | 308 Haven't reviewed the patch yet, but I've got a question on this. Are there any other users of this header file? Can I just roll it into the .c file if I pick up the patch? They can be rolled together. There is a driver pending for the device in I²S mode but there isn't anything in common. Alan -- Keep Your Developer Skills Current with LearnDevNow! The most comprehensive online learning library for Microsoft developers is just $99.99! Visual Studio, SharePoint, SQL - plus HTML5, CSS3, MVC3, Metro Style Apps, more. Free future releases when you subscribe now! http://p.sf.net/sfu/learndevnow-d2d ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH] spi: spi-sh: add IORESOURCE_MEM_TYPE_MASK decoding for access size
2012/01/26 19:22, Paul Mundt wrote:
On Thu, Jan 26, 2012 at 05:43:57PM +0900, Shimoda, Yoshihiro wrote:
[ snip ]
static void spi_sh_set_bit(struct spi_sh_data *ss, unsigned long val,
@@ -464,6 +473,18 @@ static int __devinit spi_sh_probe(struct
platform_device *pdev)
ss = spi_master_get_devdata(master);
dev_set_drvdata(pdev-dev, ss);
+switch (res-flags IORESOURCE_MEM_TYPE_MASK) {
+case IORESOURCE_MEM_8BIT:
+ss-width = 8;
+break;
+case IORESOURCE_MEM_32BIT:
+ss-width = 32;
+break;
+default:
+dev_err(pdev-dev, No support width\n);
+ret = -ENODEV;
+goto error1;
If the default up to this point has been 32-bit only then it makes sense
for 32 to still remain the default. The 8-bit user is presumably a new
one and therefore has no existing platform data configuration to worry
about, while this change would require existing users to be updated for
the new 32-bit flag to behave the same way they have up until now.
Thank you for your comment.
Unfortunately, the value of IORESOURCE_MEM_8BIT is (03), so existing users
will not enter to the default.
If you wish to do this incrementally then you can of course convert all
of the existing platforms to the new mechanism for 32-bit as well and
then simply error out as above for the undefined width case, but I still
think it makes more sense to have a usable default.
I think so. But, I think I cannot write such a code using IORESOURCE_MEM_*BIT
by the above reason.
At the moment, existing platform which uses this driver is one only. And,
I already sent a patch to modify the resource.
http://marc.info/?l=linux-shm=132756762518679w=2
Best regards,
Yoshihiro Shimoda
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Re: [PATCH] spi: spi-sh: add IORESOURCE_MEM_TYPE_MASK decoding for access size
On Fri, Jan 27, 2012 at 10:14:49AM +0900, Shimoda, Yoshihiro wrote:
2012/01/26 19:22, Paul Mundt wrote:
On Thu, Jan 26, 2012 at 05:43:57PM +0900, Shimoda, Yoshihiro wrote:
[ snip ]
static void spi_sh_set_bit(struct spi_sh_data *ss, unsigned long val,
@@ -464,6 +473,18 @@ static int __devinit spi_sh_probe(struct
platform_device *pdev)
ss = spi_master_get_devdata(master);
dev_set_drvdata(pdev-dev, ss);
+ switch (res-flags IORESOURCE_MEM_TYPE_MASK) {
+ case IORESOURCE_MEM_8BIT:
+ ss-width = 8;
+ break;
+ case IORESOURCE_MEM_32BIT:
+ ss-width = 32;
+ break;
+ default:
+ dev_err(pdev-dev, No support width\n);
+ ret = -ENODEV;
+ goto error1;
If the default up to this point has been 32-bit only then it makes sense
for 32 to still remain the default. The 8-bit user is presumably a new
one and therefore has no existing platform data configuration to worry
about, while this change would require existing users to be updated for
the new 32-bit flag to behave the same way they have up until now.
Thank you for your comment.
Unfortunately, the value of IORESOURCE_MEM_8BIT is (03), so existing users
will not enter to the default.
Ah, ok, I missed that. In that case I suppose your original patch makes
the most sense. We should be able to roll in the platform update patch
early anyways.
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