Re: [RESEND] spi/tegra114: Correct support for cs_change
On 09/23/2013 01:48 PM, Rhyland Klein wrote:
On 9/23/2013 2:51 PM, Stephen Warren wrote:
On 09/18/2013 12:17 PM, Rhyland Klein wrote:
The tegra114 driver wasn't currently handling the cs_change functionality.
It is meant to invert normal behavior, and we were only using it to possibly
delay at the end of a transfer.
...
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
...
@@ -717,7 +718,12 @@ static int tegra_spi_start_transfer_one(struct
spi_device *spi,
else if (req_mode == SPI_MODE_3)
command1 |= SPI_CONTROL_MODE_3;
- tegra_spi_writel(tspi, command1, SPI_COMMAND1);
+ if (tspi-cs_control) {
+ if (tspi-cs_control != spi)
+ tegra_spi_writel(tspi, command1, SPI_COMMAND1);
Do you really need a separate write call there? The value of command1
isn't fully set up there (the CS bits are all set up immediately after),
so won't that glitch the CS lines in some cases?
On our hardware (as far as I've seen), the CS line is normally low. We
I assume you meant normally *active* low, not normally low?
need to generate a falling-edge to trigger the beginning of a SPI
transaction. Doing this write with the default value of SPI_COMMAND1
causes a brief rise and fall of CS, giving us our falling-edge.
That sounds like exactly the glitch I was talking about.
Assuming CS isn't held constantly asserted (low), isn't CS de-asserted
(rises) at the end of transaction n-1, and re-asserted (falls) at the
start of transaction n? If so, I'm not sure why the setup for
transaction n needs to both de-assert and then re-assert it? It seems
like cs_control should be handled at the end of a transaction, not at
the start of the next one.
--
October Webinars: Code for Performance
Free Intel webinars can help you accelerate application performance.
Explore tips for MPI, OpenMP, advanced profiling, and more. Get the most from
the latest Intel processors and coprocessors. See abstracts and register
http://pubads.g.doubleclick.net/gampad/clk?id=60133471iu=/4140/ostg.clktrk
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH 2/2] spi: convert drivers to use bits_per_word_mask
On 07/09/2013 09:47 AM, Michal Simek wrote:
diff --git a/drivers/spi/spi-xilinx.c b/drivers/spi/spi-xilinx.c
index e1d7696..f321bf9 100644 --- a/drivers/spi/spi-xilinx.c +++
b/drivers/spi/spi-xilinx.c @@ -232,21 +232,6 @@ static int
xilinx_spi_setup_transfer(struct spi_device *spi, return 0; }
-static int xilinx_spi_setup(struct spi_device *spi) -{ -/*
always return 0, we can not check the number of bits. - * There
are cases when SPI setup is called before any driver is - *
there, in that case the SPI core defaults to 8 bits, which we -
* do not support in some cases. But if we return an error, the -
* SPI device would not be registered and no driver can get hold
of it - * When the driver is there, it will call SPI setup again
with the -* correct number of bits per transfer. -* If a
driver setups with the wrong bit number, it will fail when - *
it tries to do a transfer - */ - return 0; -} - static void
xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi) { u8 sr; @@
-377,7 +362,6 @@ struct spi_master *xilinx_spi_init(struct device
*dev, struct resource *mem, xspi-bitbang.chipselect =
xilinx_spi_chipselect; xspi-bitbang.setup_transfer =
xilinx_spi_setup_transfer; xspi-bitbang.txrx_bufs =
xilinx_spi_txrx_bufs; - xspi-bitbang.master-setup =
xilinx_spi_setup; init_completion(xspi-done);
if (!request_mem_region(mem-start, resource_size(mem),
This part of this patch is breaking xilinx spi driver because when
spi_bitbang_start is called it goes through some if else... and
because bitbang-txrx_bufs is defined it end up in this code } else
if (!master-setup) { return -EINVAL; }
Probably the best solution is just revert this part of patch. Mark:
What do you think?
Hmm. Why is master-setup required by the bitbang driver, if it's
legal (i.e. the code works) to implement it just by doing nothing?
--
See everything from the browser to the database with AppDynamics
Get end-to-end visibility with application monitoring from AppDynamics
Isolate bottlenecks and diagnose root cause in seconds.
Start your free trial of AppDynamics Pro today!
http://pubads.g.doubleclick.net/gampad/clk?id=48808831iu=/4140/ostg.clktrk
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH 1/2] spi: introduce macros to set bits_per_word_mask
Introduce two macros to make setting up spi_master.bits_per_word_mask
easier, and avoid mistakes like writing BIT(n) instead of BIT(n - 1).
SPI_BPW_MASK is for a single supported value of bits_per_word_mask.
SPI_BPW_RANGE_MASK represents a contiguous set of bit lengths.
Signed-off-by: Stephen Warren swar...@wwwdotorg.org
---
include/linux/spi/spi.h |2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 6ff26c8..1737256 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -308,6 +308,8 @@ struct spi_master {
/* bitmask of supported bits_per_word for transfers */
u32 bits_per_word_mask;
+#define SPI_BPW_MASK(bits) BIT((bits) - 1)
+#define SPI_BPW_RANGE_MASK(min, max) ((BIT(max) - 1) - (BIT(min) - 1))
/* other constraints relevant to this driver */
u16 flags;
--
1.7.10.4
--
Try New Relic Now We'll Send You this Cool Shirt
New Relic is the only SaaS-based application performance monitoring service
that delivers powerful full stack analytics. Optimize and monitor your
browser, app, servers with just a few lines of code. Try New Relic
and get this awesome Nerd Life shirt! http://p.sf.net/sfu/newrelic_d2d_may
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH 2/2] spi: convert drivers to use bits_per_word_mask
Fill in the recently added spi_master.bits_per_word_mask field in as
many drivers as possible. Make related cleanups, such as removing any
redundant error-checking, or empty setup callbacks.
Cc: device-drivers-de...@blackfin.uclinux.org
Cc: Mike Frysinger vap...@gentoo.org
Signed-off-by: Stephen Warren swar...@wwwdotorg.org
---
The only part of this change I'm not 100% sure of is to spi-bfin-*.c;
these used to support any bits_per_word value that was a multiple of 8
or 16. However, the code only has u8_ops and u16_ops, which implies to
me that it actually supports only 8 and 16 bits_per_word, not multiples
of those. However, it'd be good if the maintainers of those files could
confirm this.
---
drivers/spi/spi-altera.c| 12
drivers/spi/spi-ath79.c |4 +---
drivers/spi/spi-atmel.c |9 +
drivers/spi/spi-au1550.c| 12 +---
drivers/spi/spi-bcm63xx.c | 20 +---
drivers/spi/spi-bfin-sport.c| 10 ++
drivers/spi/spi-bfin5xx.c | 21 +
drivers/spi/spi-clps711x.c |7 +--
drivers/spi/spi-coldfire-qspi.c | 11 ++-
drivers/spi/spi-davinci.c |8
drivers/spi/spi-dw.c| 26 --
drivers/spi/spi-ep93xx.c| 11 +--
drivers/spi/spi-fsl-espi.c |9 ++---
drivers/spi/spi-gpio.c |4 +---
drivers/spi/spi-imx.c |6 +++---
drivers/spi/spi-mxs.c |7 +--
drivers/spi/spi-nuc900.c| 13 -
drivers/spi/spi-omap-100k.c | 12 ++--
drivers/spi/spi-omap2-mcspi.c | 13 ++---
drivers/spi/spi-ppc4xx.c| 13 +
drivers/spi/spi-pxa2xx.c| 20 ++--
drivers/spi/spi-s3c64xx.c |3 ++-
drivers/spi/spi-sirf.c |6 ++
drivers/spi/spi-ti-ssp.c| 16 +---
drivers/spi/spi-topcliff-pch.c | 17 +
drivers/spi/spi-txx9.c |8 +---
drivers/spi/spi-xcomm.c | 12 ++--
drivers/spi/spi-xilinx.c| 16
28 files changed, 46 insertions(+), 280 deletions(-)
diff --git a/drivers/spi/spi-altera.c b/drivers/spi/spi-altera.c
index a537f8d..6b7096e 100644
--- a/drivers/spi/spi-altera.c
+++ b/drivers/spi/spi-altera.c
@@ -103,16 +103,6 @@ static void altera_spi_chipsel(struct spi_device *spi, int
value)
}
}
-static int altera_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
-{
- return 0;
-}
-
-static int altera_spi_setup(struct spi_device *spi)
-{
- return 0;
-}
-
static inline unsigned int hw_txbyte(struct altera_spi *hw, int count)
{
if (hw-tx) {
@@ -231,7 +221,6 @@ static int altera_spi_probe(struct platform_device *pdev)
master-bus_num = pdev-id;
master-num_chipselect = 16;
master-mode_bits = SPI_CS_HIGH;
- master-setup = altera_spi_setup;
hw = spi_master_get_devdata(master);
platform_set_drvdata(pdev, hw);
@@ -240,7 +229,6 @@ static int altera_spi_probe(struct platform_device *pdev)
hw-bitbang.master = spi_master_get(master);
if (!hw-bitbang.master)
return err;
- hw-bitbang.setup_transfer = altera_spi_setupxfer;
hw-bitbang.chipselect = altera_spi_chipsel;
hw-bitbang.txrx_bufs = altera_spi_txrx;
diff --git a/drivers/spi/spi-ath79.c b/drivers/spi/spi-ath79.c
index e504b76..5e2d52c 100644
--- a/drivers/spi/spi-ath79.c
+++ b/drivers/spi/spi-ath79.c
@@ -155,9 +155,6 @@ static int ath79_spi_setup(struct spi_device *spi)
{
int status = 0;
- if (spi-bits_per_word 32)
- return -EINVAL;
-
if (!spi-controller_state) {
status = ath79_spi_setup_cs(spi);
if (status)
@@ -226,6 +223,7 @@ static int ath79_spi_probe(struct platform_device *pdev)
pdata = pdev-dev.platform_data;
+ master-bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
master-setup = ath79_spi_setup;
master-cleanup = ath79_spi_cleanup;
if (pdata) {
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 380387a..31cfc87 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -1268,13 +1268,6 @@ static int atmel_spi_setup(struct spi_device *spi)
return -EINVAL;
}
- if (bits 8 || bits 16) {
- dev_dbg(spi-dev,
- setup: invalid bits_per_word %u (8 to 16)\n,
- bits);
- return -EINVAL;
- }
-
/* see notes above re chipselect */
if (!atmel_spi_is_v2(as)
spi-chip_select == 0
@@ -1515,7 +1508,7 @@ static int atmel_spi_probe(struct platform_device *pdev)
/* the spi-mode bits understood by this driver: */
master-mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH
Re: [PATCH] drivers/spi/spi-tegra114.c clean use of devm_ioremap_resource()
On 05/14/2013 04:07 AM, Laurent Navet wrote: Check of 'r' and calls to dev_err are already done in devm_ioremap_resource, so no need to do them twice. I think this duplicates part of a much wider patch series that Wolfram is working on; I CC'd him here. -- AlienVault Unified Security Management (USM) platform delivers complete security visibility with the essential security capabilities. Easily and efficiently configure, manage, and operate all of your security controls from a single console and one unified framework. Download a free trial. http://p.sf.net/sfu/alienvault_d2d ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [RFC 23/42] drivers/spi: don't check resource with devm_ioremap_resource
On 05/10/2013 02:17 AM, Wolfram Sang wrote:
devm_ioremap_resource does sanity checks on the given resource. No need to
duplicate this in the driver.
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
- r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!r) {
- dev_err(pdev-dev, No IO memory resource\n);
- ret = -ENODEV;
- goto exit_free_master;
- }
tspi-phys = r-start;
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
The tspi-phy assignment is broken there now.
diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c
- r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!r) {
- dev_err(pdev-dev, No IO memory resource\n);
- ret = -ENODEV;
- goto exit_free_master;
- }
tspi-phys = r-start;
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Same here.
--
Learn Graph Databases - Download FREE O'Reilly Book
Graph Databases is the definitive new guide to graph databases and
their applications. This 200-page book is written by three acclaimed
leaders in the field. The early access version is available now.
Download your free book today! http://p.sf.net/sfu/neotech_d2d_may
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH 4/4] spi: remove unused Tegra platform data header
On 03/09/2013 02:21 AM, Grant Likely wrote: On Sat, Mar 9, 2013 at 1:10 AM, Rhyland Klein rkl...@nvidia.com wrote: On 3/2/2013 6:02 PM, Grant Likely wrote: On Fri, 15 Feb 2013 15:03:50 -0700, Stephen Warren swar...@wwwdotorg.org wrote: From: Stephen Warren swar...@nvidia.com The platform data header is no longer used. Delete it. Signed-off-by: Stephen Warren swar...@nvidia.com I like the diffstat for this series. Applied! Grant, I was looking to pull these patches. I don't see them in linux-next and I looked at your repo and didn't see them. Can you give me a pointer? That is because I haven't pushed them out yet. Initially it was because the merge window was still open, and then it was because I was in Hong Kong last week for Linaro Connect. I haven't wanted to push out my trees until I have a chance to do some build testing which I will do on Monday. Grant, I still don't see these patches in next-20130403. -- Minimize network downtime and maximize team effectiveness. Reduce network management and security costs.Learn how to hire the most talented Cisco Certified professionals. Visit the Employer Resources Portal http://www.cisco.com/web/learning/employer_resources/index.html ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH] spi/s3c64xx: Convert to bits_per_word_mask
On 04/01/2013 07:18 AM, Mark Brown wrote: The core can do the validation for us. Reviewed-by: Stephen Warren swar...@wwwdotorg.org -- Own the Future-Intel(R) Level Up Game Demo Contest 2013 Rise to greatness in Intel's independent game demo contest. Compete for recognition, cash, and the chance to get your game on Steam. $5K grand prize plus 10 genre and skill prizes. Submit your demo by 6/6/13. http://altfarm.mediaplex.com/ad/ck/12124-176961-30367-2 ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH 1/2] spi: add ability to validate xfer-bits_per_word in SPI core
On 04/01/2013 01:52 PM, Trent Piepho wrote:
On Tue, Mar 26, 2013 at 7:37 PM, Stephen Warren swar...@wwwdotorg.org wrote:
Allow SPI masters to define the set of bits_per_word values they support.
If they do this, then the SPI core will reject transfers that attempt to
use an unsupported bits_per_word value. This eliminates the need for each
SPI driver to implement this checking in most cases.
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
+ if (master-bits_per_word_mask) {
+ /* Only 32 bits fit in the mask */
+ if (xfer-bits_per_word 32)
+ return -EINVAL;
+ if (!(master-bits_per_word_mask
+ BIT(xfer-bits_per_word - 1)))
+ return -EINVAL;
+ }
This could be simplified to:
if (master-bits_per_word_mask
!(master-bits_per_word_mask BIT(xfer-bits_per_word - 1)))
return -EINVAL;
It's not necessary to handle bits_per_word 32 differently. The
resulting mask will either be zero when unsigned long is 32 bits, or
have a bit set if unsigned long is 64 bits. Either way, it won't
match any of the bits set in bits_per_word_mask and the desired result
is produced. The extra test for 32 will just slow down the common
case.
That's certainly true, and I did consider that. However, I preferred to
be explicit. I imagine the compiler optimizes both to the same thing anyway.
@@ -301,6 +306,9 @@ struct spi_master {
/* spi_device.mode flags understood by this controller driver */
u16 mode_bits;
+ /* bitmask of supported bits_per_word for transfers */
+ u32 bits_per_word_mask;
+
/* other constraints relevant to this driver */
u16 flags;
If the u32 field was before the u16 fields, then the structure would
have be more likely to not need padding in the future. There are four
u16 in front of bits_per_word_mask so it doesn't need padding now
(however, there are 2 bytes of padding after flags), but if someone
adds a new 16-bit field in front of bits_per_word_mask then padding
will be added.
I was assuming whoever added any new fields would put thought into the
alignment; the fields can easily be swapped around to avoid any extra
padding when new fields are added.
--
Own the Future-Intel(R) Level Up Game Demo Contest 2013
Rise to greatness in Intel's independent game demo contest. Compete
for recognition, cash, and the chance to get your game on Steam.
$5K grand prize plus 10 genre and skill prizes. Submit your demo
by 6/6/13. http://altfarm.mediaplex.com/ad/ck/12124-176961-30367-2
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH 1/2] spi: add ability to validate xfer-bits_per_word in SPI core
Allow SPI masters to define the set of bits_per_word values they support.
If they do this, then the SPI core will reject transfers that attempt to
use an unsupported bits_per_word value. This eliminates the need for each
SPI driver to implement this checking in most cases.
Signed-off-by: Stephen Warren swar...@wwwdotorg.org
---
drivers/spi/spi.c |8
include/linux/spi/spi.h |8
2 files changed, 16 insertions(+)
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index f996c60..0cabf15 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -1377,6 +1377,14 @@ static int __spi_async(struct spi_device *spi, struct
spi_message *message)
xfer-bits_per_word = spi-bits_per_word;
if (!xfer-speed_hz)
xfer-speed_hz = spi-max_speed_hz;
+ if (master-bits_per_word_mask) {
+ /* Only 32 bits fit in the mask */
+ if (xfer-bits_per_word 32)
+ return -EINVAL;
+ if (!(master-bits_per_word_mask
+ BIT(xfer-bits_per_word - 1)))
+ return -EINVAL;
+ }
}
message-spi = spi;
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 38c2b92..733eb5e 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -228,6 +228,11 @@ static inline void spi_unregister_driver(struct spi_driver
*sdrv)
* every chipselect is connected to a slave.
* @dma_alignment: SPI controller constraint on DMA buffers alignment.
* @mode_bits: flags understood by this controller driver
+ * @bits_per_word_mask: A mask indicating which values of bits_per_word are
+ * supported by the driver. Bit n indicates that a bits_per_word n+1 is
+ * suported. If set, the SPI core will reject any transfer with an
+ * unsupported bits_per_word. If not set, this value is simply ignored,
+ * and it's up to the individual driver to perform any validation.
* @flags: other constraints relevant to this driver
* @bus_lock_spinlock: spinlock for SPI bus locking
* @bus_lock_mutex: mutex for SPI bus locking
@@ -301,6 +306,9 @@ struct spi_master {
/* spi_device.mode flags understood by this controller driver */
u16 mode_bits;
+ /* bitmask of supported bits_per_word for transfers */
+ u32 bits_per_word_mask;
+
/* other constraints relevant to this driver */
u16 flags;
#define SPI_MASTER_HALF_DUPLEX BIT(0) /* can't do full duplex */
--
1.7.10.4
--
Own the Future-Intelreg; Level Up Game Demo Contest 2013
Rise to greatness in Intel's independent game demo contest.
Compete for recognition, cash, and the chance to get your game
on Steam. $5K grand prize plus 10 genre and skill prizes.
Submit your demo by 6/6/13. http://p.sf.net/sfu/intel_levelupd2d
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH 2/2] spi: bcm2835: make use of new bits_per_word_mask core feature
This driver only supports bits_per_word==8, so inform the SPI core of
this. Remove all the open-coded validation that's no longer needed.
Signed-off-by: Stephen Warren swar...@wwwdotorg.org
---
This only converts one driver, but if the concept is acceptable, I'll try
to take a look at other drivers and convert them too.
drivers/spi/spi-bcm2835.c | 36 +---
1 file changed, 1 insertion(+), 35 deletions(-)
diff --git a/drivers/spi/spi-bcm2835.c b/drivers/spi/spi-bcm2835.c
index 346601e..89c0b50 100644
--- a/drivers/spi/spi-bcm2835.c
+++ b/drivers/spi/spi-bcm2835.c
@@ -182,23 +182,6 @@ static irqreturn_t bcm2835_spi_interrupt(int irq, void
*dev_id)
return IRQ_NONE;
}
-static int bcm2835_spi_check_transfer(struct spi_device *spi,
- struct spi_transfer *tfr)
-{
- /* tfr==NULL when called from bcm2835_spi_setup() */
- u32 bpw = tfr ? tfr-bits_per_word : spi-bits_per_word;
-
- switch (bpw) {
- case 8:
- break;
- default:
- dev_err(spi-dev, unsupported bits_per_word=%d\n, bpw);
- return -EINVAL;
- }
-
- return 0;
-}
-
static int bcm2835_spi_start_transfer(struct spi_device *spi,
struct spi_transfer *tfr)
{
@@ -273,19 +256,6 @@ static int bcm2835_spi_finish_transfer(struct spi_device
*spi,
return 0;
}
-static int bcm2835_spi_setup(struct spi_device *spi)
-{
- int ret;
-
- ret = bcm2835_spi_check_transfer(spi, NULL);
- if (ret) {
- dev_err(spi-dev, setup: invalid message\n);
- return ret;
- }
-
- return 0;
-}
-
static int bcm2835_spi_transfer_one(struct spi_master *master,
struct spi_message *mesg)
{
@@ -297,10 +267,6 @@ static int bcm2835_spi_transfer_one(struct spi_master
*master,
bool cs_change;
list_for_each_entry(tfr, mesg-transfers, transfer_list) {
- err = bcm2835_spi_check_transfer(spi, tfr);
- if (err)
- goto out;
-
err = bcm2835_spi_start_transfer(spi, tfr);
if (err)
goto out;
@@ -348,9 +314,9 @@ static int bcm2835_spi_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, master);
master-mode_bits = BCM2835_SPI_MODE_BITS;
+ master-bits_per_word_mask = BIT(8 - 1);
master-bus_num = -1;
master-num_chipselect = 3;
- master-setup = bcm2835_spi_setup;
master-transfer_one_message = bcm2835_spi_transfer_one;
master-dev.of_node = pdev-dev.of_node;
--
1.7.10.4
--
Own the Future-Intelreg; Level Up Game Demo Contest 2013
Rise to greatness in Intel's independent game demo contest.
Compete for recognition, cash, and the chance to get your game
on Steam. $5K grand prize plus 10 genre and skill prizes.
Submit your demo by 6/6/13. http://p.sf.net/sfu/intel_levelupd2d
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH V2] spi: add driver for BCM2835
From: Chris Boot bo...@bootc.net
The BCM2835 contains two forms of SPI master controller (one known
simply as SPI0, and the other known as the Universal SPI Master, in
the auxilliary block) and one form of SPI slave controller. This patch
adds support for the SPI0 controller.
This driver is taken from Chris Boot's repository at
git://github.com/bootc/linux.git rpi-linear
as of commit 6de2905 spi-bcm2708: fix printf with spurious %s.
In the first SPI-related commit there, Chris wrote:
Thanks to csoutreach / A Robinson for his driver which I used as an
inspiration. You can find his version here:
http://piface.openlx.org.uk/raspberry-pi-spi-kernel-driver-available-for
Changes made during upstreaming:
* Renamed bcm2708 to bcm2835 as per upstream naming for this SoC.
* Removed support for brcm,realtime property.
* Increased transfer timeout to 30 seconds.
* Return IRQ_NONE from the IRQ handler if no interrupt was handled.
* Disable TA (Transfer Active) and clear FIFOs on a transfer timeout.
* Wrote device tree binding documentation.
* Request unnamed clock rather than sys_pclk; the DT will provide the
correct clock.
* Assume that tfr-speed_hz and tfr-bits_per_word are always set in
bcm2835_spi_start_transfer(), bcm2835_spi_transfer_one(), so no need
to check spi-speed_hz or tft-bits_per_word.
* Re-ordered probe() to remove the need for temporary variables.
* Call clk_disable_unprepare() rather than just clk_unprepare() on probe()
failure.
* Don't use devm_request_irq(), to ensure that the IRQ doesn't fire after
we've torn down the device, but not unhooked the IRQ.
* Moved probe()'s call to clk_prepare_enable() so we can be sure the clock
is enabled if the IRQ handler fires immediately.
* Remove redundant checks from bcm2835_spi_check_transfer() and
bcm2835_spi_setup().
* Re-ordered IRQ handler to check for RXR before DONE. Added comments to
ISR.
* Removed empty prepare/unprepare implementations.
* Removed use of devinit/devexit.
* Added BCM2835_ prefix to defines.
Signed-off-by: Chris Boot bo...@bootc.net
Signed-off-by: Stephen Warren swar...@wwwdotorg.org
---
v2:
* Removed support for brcm,realtime property.
* Increased transfer timeout to 30 seconds.
* Return IRQ_NONE from the IRQ handler if no interrupt was handled.
* Disable TA (Transfer Active) and clear FIFOs on a transfer timeout.
* Call clk_disable_unprepare() rather than just clk_unprepare() on probe()
failure.
* Moved probe()'s call to clk_prepare_enable() so we can be sure the clock
is enabled if the IRQ handler fires immediately.
* Remove redundant checks from bcm2835_spi_check_transfer() and
bcm2835_spi_setup().
* Re-ordered IRQ handler to check for RXR before DONE. Added comments to
ISR.
---
.../devicetree/bindings/spi/brcm,bcm2835-spi.txt | 22 +
drivers/spi/Kconfig| 11 +
drivers/spi/Makefile |1 +
drivers/spi/spi-bcm2835.c | 456
4 files changed, 490 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/brcm,bcm2835-spi.txt
create mode 100644 drivers/spi/spi-bcm2835.c
diff --git a/Documentation/devicetree/bindings/spi/brcm,bcm2835-spi.txt
b/Documentation/devicetree/bindings/spi/brcm,bcm2835-spi.txt
new file mode 100644
index 000..8bf89c6
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/brcm,bcm2835-spi.txt
@@ -0,0 +1,22 @@
+Broadcom BCM2835 SPI0 controller
+
+The BCM2835 contains two forms of SPI master controller, one known simply as
+SPI0, and the other known as the Universal SPI Master; part of the
+auxilliary block. This binding applies to the SPI0 controller.
+
+Required properties:
+- compatible: Should be brcm,bcm2835-spi.
+- reg: Should contain register location and length.
+- interrupts: Should contain interrupt.
+- clocks: The clock feeding the SPI controller.
+
+Example:
+
+spi@20204000 {
+ compatible = brcm,bcm2835-spi;
+ reg = 0x7e204000 0x1000;
+ interrupts = 2 22;
+ clocks = clk_spi;
+ #address-cells = 1;
+ #size-cells = 0;
+};
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index f80eee7..32b85d4 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -74,6 +74,17 @@ config SPI_ATMEL
This selects a driver for the Atmel SPI Controller, present on
many AT32 (AVR32) and AT91 (ARM) chips.
+config SPI_BCM2835
+ tristate BCM2835 SPI controller
+ depends on ARCH_BCM2835
+ help
+ This selects a driver for the Broadcom BCM2835 SPI master.
+
+ The BCM2835 contains two types of SPI master controller; the
+ universal SPI master, and the regular SPI controller. This driver
+ is for the regular SPI controller. Slave mode operation is not also
+ not supported.
+
config SPI_BFIN5XX
tristate SPI controller driver for ADI Blackfin5xx
depends on BLACKFIN
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index e53c309
Re: [PATCH] spi: slink-tegra20: move runtime pm calls to transfer_one_message
On 03/07/2013 11:21 PM, Laxman Dewangan wrote: The prepare_transfer_hardware() is called in atomic context and calling synchronous runtime pm calls can create scheduling deadlock. Therefore, in place of calling runtime PM calls from prepare/unprepare message transfer, calling this in transfer_one_message(). Tested-by: Stephen Warren swar...@nvidia.com This does fix some slightly intermittent lockups/crashes for me when erasing and re-writing the SPI flash on Cardhu. -- Symantec Endpoint Protection 12 positioned as A LEADER in The Forrester Wave(TM): Endpoint Security, Q1 2013 and remains a good choice in the endpoint security space. For insight on selecting the right partner to tackle endpoint security challenges, access the full report. http://p.sf.net/sfu/symantec-dev2dev ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH] spi: add driver for BCM2835
On 03/05/2013 09:05 PM, Mark Brown wrote:
On Tue, Mar 05, 2013 at 07:49:02PM -0700, Stephen Warren wrote:
+static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id)
+{
if (cs BCM2835_SPI_CS_DONE) { if (bs-len) { /* first interrupt
in a transfer */ /* fill the TX fifo with up to 16 bytes */
bcm2835_wr_fifo(bs, 16); } else { /* transfer complete */ /*
disable SPI interrupts */ cs = ~(BCM2835_SPI_CS_INTR |
BCM2835_SPI_CS_INTD); bcm2835_wr(bs, BCM2835_SPI_CS, cs);
/* wake up our bh */ complete(bs-done); } } else if (cs
BCM2835_SPI_CS_RXR) { /* read 12 bytes of data */
bcm2835_rd_fifo(bs, 12);
/* write up to 12 bytes */ bcm2835_wr_fifo(bs, 12); }
I'd feel happier if these were independent statements in case both
are asserted simultaneously.
I don't think it would be correct to make that change.
As background, CS_DONE is really TX FIFO EMPTY per the description
in the documentation.
When TA (Transfer Active) is set by bcm2835_spi_start_transfer(),
CS_DONE will immediately become set, and cause an interrupt. This will
cause the if/if (first interrupt in a transfer) case above to execute,
and the FIFO to be filled with up to 16 bytes. Once 12 of those bytes
have been transferred, CS_RXR (RX FIFO needs Reading) will be set
causing an interrupt, which will trigger the else case. At the end of
the message, we stop filling the TX FIFO, and so it eventually drains
completely, and CS_DONE fires again, causing the if/else (transfer
complete) path to be taken.
In the end-of-transfer case, it's possible CS_RXR may also be set,
since the last chunk of the transfer might just happen to be 12 bytes.
However, we don't want to execute the else cause to drain the FIFO,
since the CS_DONE case completes the completion, which then allows
bcm2835_spi_finish_transfer() to drain the FIFO based on the RXD (RX
FIFO has Data) field. Doing it in the IRQ handler too would confuse
things. I guess this SoC only has a CPU so it'd work out fine, but
it's probably best not to rely on it.
Also, I do wonder what happens if we process the CS_RXR interrupt too
late though, and CS_DONE gets set before we've transferred the entire
message simply because the FIFO drained unexpectedly.
With the current code, we'd simply write 16 bytes to the TX FIFO and
not read the RX FIFO, thus likely falling out of sync and overflowing
the TX FIFO next time around.
Equally, with your suggestion modification, we'd fill the TX FIFO with
16 bytes in the first if block, then again with 12 more bytes in the
second if block, and likely overflow the FIFO.
Perhaps the test order should be more like:
if (cs RXR) {
drain 12 bytes from RX FIFO
write up to 12 bytes to TX FIFO
} else if (cs DONE) {
if (len)
write up to 16 bytes to TX FIFO
else
finish transfer
}
And again the second block should be an else not an independent if, so
that if RXR was processed late, we don't end up writing first 12 then
16 bytes to the TX FIFO at once.
Does that all make sense?
--
Symantec Endpoint Protection 12 positioned as A LEADER in The Forrester
Wave(TM): Endpoint Security, Q1 2013 and remains a good choice in the
endpoint security space. For insight on selecting the right partner to
tackle endpoint security challenges, access the full report.
http://p.sf.net/sfu/symantec-dev2dev
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH] spi: add driver for BCM2835
On 03/05/2013 09:05 PM, Mark Brown wrote:
On Tue, Mar 05, 2013 at 07:49:02PM -0700, Stephen Warren wrote:
+switch (bpw) { +case 8: + break; +
default: +
dev_err(spi-dev, unsupported bits_per_word=%d\n, bpw); +
return -EINVAL; +}
Is there an assumption in the SPI core that bpw will never be 32? The
value is stored in a u8 in the controller and transfer structs, so
large values are physically possible. So if there is no such
assumption, then representing all of an SPI controller's supported BPW
in a mask/list would be a little unwieldy, so doing central checking
might not work well.
+if (!(spi-mode SPI_NO_CS) +
(spi-chip_select
spi-master-num_chipselect)) { +dev_err(spi-dev, +
invalid chipselect %u\n, + spi-chip_select); +
return
-EINVAL; ` + }
This seems like stuff the core should be able to do for you.
It looks like the core always validates the chip-select value, so I'll
remove that.
--
Symantec Endpoint Protection 12 positioned as A LEADER in The Forrester
Wave(TM): Endpoint Security, Q1 2013 and remains a good choice in the
endpoint security space. For insight on selecting the right partner to
tackle endpoint security challenges, access the full report.
http://p.sf.net/sfu/symantec-dev2dev
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH] spi: add driver for BCM2835
From: Chris Boot bo...@bootc.net
The BCM2835 contains two forms of SPI master controller (one known
simply as SPI0, and the other known as the Universal SPI Master, in
the auxilliary block) and one form of SPI slave controller. This patch
adds support for the SPI0 controller.
This driver is taken from Chris Boot's repository at
git://github.com/bootc/linux.git rpi-linear
as of commit 6de2905 spi-bcm2708: fix printf with spurious %s.
In the first SPI-related commit there, Chris wrote:
Thanks to csoutreach / A Robinson for his driver which I used as an
inspiration. You can find his version here:
http://piface.openlx.org.uk/raspberry-pi-spi-kernel-driver-available-for
Changes made during upstreaming:
* Renamed bcm2708 to bcm2835 as per upstream naming for this SoC.
* Wrote device tree binding documentation.
* Request unnamed clock rather than sys_pclk; the DT will provide the
correct clock.
* Assume that tfr-speed_hz and tfr-bits_per_word are always set in
bcm2835_spi_start_transfer(), bcm2835_spi_transfer_one(), so no need
to check spi-speed_hz or tft-bits_per_word.
* Re-ordered probe() to remove the need for temporary variables.
* Don't use devm_request_irq(), to ensure that the IRQ doesn't fire after
we've torn down the device, but not unhooked the IRQ.
* Removed empty prepare/unprepare implementations.
* Removed use of devinit/devexit.
* Added BCM2835_ prefix to defines.
Signed-off-by: Chris Boot bo...@bootc.net
Signed-off-by: Stephen Warren swar...@wwwdotorg.org
---
.../devicetree/bindings/spi/brcm,bcm2835-spi.txt | 26 ++
drivers/spi/Kconfig| 11 +
drivers/spi/Makefile |1 +
drivers/spi/spi-bcm2835.c | 430
4 files changed, 468 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/brcm,bcm2835-spi.txt
create mode 100644 drivers/spi/spi-bcm2835.c
diff --git a/Documentation/devicetree/bindings/spi/brcm,bcm2835-spi.txt
b/Documentation/devicetree/bindings/spi/brcm,bcm2835-spi.txt
new file mode 100644
index 000..3f54bc8
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/brcm,bcm2835-spi.txt
@@ -0,0 +1,26 @@
+Broadcom BCM2835 SPI0 controller
+
+The BCM2835 contains two forms of SPI master controller, one known simply as
+SPI0, and the other known as the Universal SPI Master; part of the
+auxilliary block. This binding applies to the SPI0 controller.
+
+Required properties:
+- compatible: Should be brcm,bcm2835-spi.
+- reg: Should contain register location and length.
+- interrupts: Should contain interrupt.
+- clocks: The clock feeding the SPI controller.
+
+Optional properties:
+- brcm,realtime: Boolean. Indicates the driver should operate with realtime
+ priority to minimise the transfer latency on the bus.
+
+Example:
+
+spi@20204000 {
+ compatible = brcm,bcm2835-spi;
+ reg = 0x7e204000 0x1000;
+ interrupts = 2 22;
+ clocks = clk_spi;
+ #address-cells = 1;
+ #size-cells = 0;
+};
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index f80eee7..32b85d4 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -74,6 +74,17 @@ config SPI_ATMEL
This selects a driver for the Atmel SPI Controller, present on
many AT32 (AVR32) and AT91 (ARM) chips.
+config SPI_BCM2835
+ tristate BCM2835 SPI controller
+ depends on ARCH_BCM2835
+ help
+ This selects a driver for the Broadcom BCM2835 SPI master.
+
+ The BCM2835 contains two types of SPI master controller; the
+ universal SPI master, and the regular SPI controller. This driver
+ is for the regular SPI controller. Slave mode operation is not also
+ not supported.
+
config SPI_BFIN5XX
tristate SPI controller driver for ADI Blackfin5xx
depends on BLACKFIN
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index e53c309..3ce1d08 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_SPI_ALTERA) += spi-altera.o
obj-$(CONFIG_SPI_ATMEL)+= spi-atmel.o
obj-$(CONFIG_SPI_ATH79)+= spi-ath79.o
obj-$(CONFIG_SPI_AU1550) += spi-au1550.o
+obj-$(CONFIG_SPI_BCM2835) += spi-bcm2835.o
obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o
obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o
obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o
diff --git a/drivers/spi/spi-bcm2835.c b/drivers/spi/spi-bcm2835.c
new file mode 100644
index 000..74fefeb
--- /dev/null
+++ b/drivers/spi/spi-bcm2835.c
@@ -0,0 +1,430 @@
+/*
+ * Driver for Broadcom BCM2835 SPI Controllers
+ *
+ * Copyright (C) 2012 Chris Boot
+ * Copyright (C) 2012 Stephen Warren
+ *
+ * This driver is inspired by:
+ * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos juh...@openwrt.org
+ * spi-atmel.c, Copyright (C) 2006 Atmel Corporation
+ *
+ * This program is free software; you
Re: [PATCH] spi: add driver for BCM2835
On 03/05/2013 09:05 PM, Mark Brown wrote:
On Tue, Mar 05, 2013 at 07:49:02PM -0700, Stephen Warren wrote:
+Optional properties: +- brcm,realtime: Boolean. Indicates the
driver should operate with realtime + priority to minimise the
transfer latency on the bus.
This isn't obviously something that ought to be in DT, it'll depend
on the OS, kernel version and so on. Indeed I don't think this is
used any more as the generic pump code Linus did handles it already
in a runtime tunable way?
I was going to remove this for similar reasons, but then I noticed
that Documentation/devicetree/bindings/spi/spi_pl022.txt contains
basically the same thing:
- pl022,rt : indicates the controller should run the message pump
with realtime priority to minimise the transfer latency on the bus
(boolean)
... so I assumed this must have been conceptually OK'd in the past.
If that somehow accidentally snuck in, I can happily remove this feature.
+list_for_each_entry(tfr, mesg-transfers, transfer_list) { +
err = bcm2835_spi_check_transfer(spi, tfr); +if (err) +
goto
out; + + err = bcm2835_spi_start_transfer(spi, tfr); +
if
(err) + goto out; + + timeout =
wait_for_completion_timeout(bs-done, +
msecs_to_jiffies(BCM2835_SPI_TIMEOUT_MS)); + if (!timeout) { +
err = -ETIMEDOUT; + goto out; + }
But I wanted to transfer 10G in a single message at 1kHz! :P
I'm not sure what the solution is here; calculated timeout value, or
no timeout?
+/* initialise the hardware */ + clk_prepare_enable(bs-clk); +
bcm2835_wr(bs, BCM2835_SPI_CS, +BCM2835_SPI_CS_CLEAR_RX |
BCM2835_SPI_CS_CLEAR_TX);
It'd be nice to only enable the clock during transfers.
In practice, the clock that's provided to the driver is a dummy fixed
clock at the moment, so doing so would make no difference. Controlling
real clocks requires passing messages to the VideoCore co-processor,
and I've avoided upstreaming any of that stuff yet since I'm not sure
if the message structures are static enough to rely on, and I'm hoping
the VC reverse-engineering effort would allow a native driver for some
of those features from the ARM core rather than via message-passing...
I'll fix up the other issues you mentioned that I didn't specifically
respond to.
--
Symantec Endpoint Protection 12 positioned as A LEADER in The Forrester
Wave(TM): Endpoint Security, Q1 2013 and remains a good choice in the
endpoint security space. For insight on selecting the right partner to
tackle endpoint security challenges, access the full report.
http://p.sf.net/sfu/symantec-dev2dev
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH V2] spi: tegra114: add spi driver
On 02/21/2013 12:10 AM, Laxman Dewangan wrote:
Add SPI driver for NVIDIA's Tegra114 SPI controller. This controller
is different than the older SoCs SPI controller in internal design as
well as register interface.
Looks good. Just a couple of nits mentioned below, then,
Reviewed-by: Stephen Warren swar...@nvidia.com
Note: There are a few minor diffs between this file and
spi-tegra20-slink.c. It might be worth eliminating as many as possible,
perhaps in a followon patch.
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
+NVIDIA Tegra114 SPI controller.
+
+Required properties:
+- compatible : should be nvidia,tegra114-spi.
+- reg: Should contain SPI registers location and length.
+- interrupts: Should contain SPI interrupts.
+- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
+ request selector for this SPI controller.
The binding should specify that a clock named spi needs to be
provided, using the standard properties in ../clock/clock-bindings.txt
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
obj-$(CONFIG_SPI_SIRF) += spi-sirf.o
obj-$(CONFIG_SPI_TEGRA20_SFLASH) += spi-tegra20-sflash.o
obj-$(CONFIG_SPI_TEGRA20_SLINK) += spi-tegra20-slink.o
+obj-$(CONFIG_SPI_TEGRA114) += spi-tegra114.o
While Tegra114 is newer, it should really be listed before the Tegra20
entries, since the Makefile is alpha-numerically sorted right now I believe.
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
+static struct platform_driver tegra_spi_driver = {
+ .driver = {
+ .name = spi-tegra114,
+ .owner = THIS_MODULE,
+ .pm = tegra_spi_pm_ops,
+ .of_match_table = of_match_ptr(tegra_spi_of_match),
No need to use of_match_ptr() there; just use the raw value since
CONFIG_OF is guaranteed to be enabled.
--
Everyone hates slow websites. So do we.
Make your web apps faster with AppDynamics
Download AppDynamics Lite for free today:
http://p.sf.net/sfu/appdyn_d2d_feb
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH] spi: tegra114: add spi driver
On 02/20/2013 06:26 AM, Laxman Dewangan wrote: On Wednesday 20 February 2013 06:41 PM, Mark Brown wrote: * PGP Signed by an unknown key On Wed, Feb 20, 2013 at 05:59:03PM +0530, Laxman Dewangan wrote: +tspi-clk = devm_clk_get(pdev-dev, spi); Does this HW block use multiple clocks? If not, I think s/spi/NULL/ there, just like the Tegra20 driver. No, spi controller uses the only one clock. I will change to NULL. I'm never convinced that NULL is a helpful clock name to pick, it's not awesome if you ever acquire a second clock. I had other idea of okeeping clock name here for power optimization. Spi controller can take the power source ffrom different clock source say clk_m (crystal) and pllp. I want to set the parent clock dynamically based on required speed so that if the desire speed can be meet from clk_m, no need to increase pll count and possible we may endup with siwtchng off pllp which can save power. So for this I may require spi_clk = devm_clk_get(pdev-dev, spi); spi_clkm = devm_clk_get(pdev-dev, clmkm); spi_pllp = devm_clk_get(pdev-dev, pllp); and call clk_set_parent(spi_clk, spi_clkm) or clk_set_parent(spi_clk, spi_pllp). OK, so that's certainly an argument for requesting a specific clock name rather than NULL. But, please do think this approach through fully. The DT binding needs to define which clock-names the driver requires to be present, and any optional clock names. DT bindings are supposed to be immutable, or perhaps extendible in a completely backwards-compatible fashion. This implies that you need to have thought through the entire list of clocks that the driver might want in the DT clock-names property when you first write the DT binding documentation... -- Everyone hates slow websites. So do we. Make your web apps faster with AppDynamics Download AppDynamics Lite for free today: http://p.sf.net/sfu/appdyn_d2d_feb ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH] spi: tegra114: add spi driver
On 02/20/2013 10:31 AM, Mark Brown wrote: On Wed, Feb 20, 2013 at 10:25:13AM -0700, Stephen Warren wrote: But, please do think this approach through fully. The DT binding needs to define which clock-names the driver requires to be present, and any optional clock names. DT bindings are supposed to be immutable, or perhaps extendible in a completely backwards-compatible fashion. This implies that you need to have thought through the entire list of clocks that the driver might want in the DT clock-names property when you first write the DT binding documentation... Since we can extend the list of clocks it doesn't seem like there's much issue here, especially if some of them are optional? Yes, there's certainly a way to extend the binding in a backwards-compatible way. However, I have seen in Rob and/or Grant push back on not fully defining bindings in the past - i.e. actively planning to initially create a minimal binding and extend it in the future, rather than completely defining it up-front. I don't know how strong of a rule they intend that to be though. If we get to the point of moving the DT bindings out of the kernel, it'd be good to get a concrete definition of what can and can't be changed in bindings. Though in general it seems like this sort of mux really should be in the clock stuff anyway. How do you see that working: something automatic inside clk_set_rate() seeing that some other parent could provide the rate, so the clock could be reparented, or ...? -- Everyone hates slow websites. So do we. Make your web apps faster with AppDynamics Download AppDynamics Lite for free today: http://p.sf.net/sfu/appdyn_d2d_feb ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH] spi: tegra114: add spi driver
On 02/20/2013 10:57 AM, Mark Brown wrote: On Wed, Feb 20, 2013 at 10:36:41AM -0700, Stephen Warren wrote: On 02/20/2013 10:31 AM, Mark Brown wrote: Since we can extend the list of clocks it doesn't seem like there's much issue here, especially if some of them are optional? Yes, there's certainly a way to extend the binding in a backwards-compatible way. However, I have seen in Rob and/or Grant push back on not fully defining bindings in the past - i.e. actively planning to initially create a minimal binding and extend it in the future, rather than completely defining it up-front. That sounds like the current stuff with a minimal definition is OK? I'm personally OK with defining a minimal binding first and extending it later. But, I'm worried if when we actually try to extend the binding later, we'll get push-back. -- Everyone hates slow websites. So do we. Make your web apps faster with AppDynamics Download AppDynamics Lite for free today: http://p.sf.net/sfu/appdyn_d2d_feb ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH] spi: tegra114: add spi driver
On 02/19/2013 06:38 AM, Laxman Dewangan wrote:
Add spi driver for NVIDIA's Tegra114 spi controller. This controller
is different than the older SoCs spi controller in internal design as
well as register interface.
Nit: SPI should be capitalized. Also in Kconfig below.
diff --git a/Documentation/devicetree/bindings/spi/nvidia,spi-tegra114.txt
b/Documentation/devicetree/bindings/spi/nvidia,spi-tegra114.txt
This file should be named nvidia,tegra114-spi.txt, so that it matches
the compatible value it describes.
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
+config SPI_TEGRA114
+ tristate Nvidia Tegra114 SPI Controller
NVIDIA should be capitalized. Also in the help description below.
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
obj-$(CONFIG_SPI_SIRF) += spi-sirf.o
obj-$(CONFIG_SPI_TEGRA20_SFLASH) += spi-tegra20-sflash.o
+obj-$(CONFIG_SPI_TEGRA114) += spi-tegra114.o
obj-$(CONFIG_SPI_TEGRA20_SLINK) += spi-tegra20-slink.o
obj-$(CONFIG_SPI_TI_SSP) += spi-ti-ssp.o
The Makefile should be sorted; Tegra114 comes before Tegra20*.
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
+static unsigned tegra_spi_calculate_curr_xfer_param(
...
+ bits_per_word = t-bits_per_word ? t-bits_per_word :
+ spi-bits_per_word;
I thought I'd seen patches so this conditional wasn't needed any more;
isn't t-bit_per_word always set correctly by the SPI core now?
Certainly the existing spi-tegra20-slink.c doesn't seem to have any
conditional here.
A similar comment applies in tegra_spi_read_rx_fifo_to_client_rxbuf()
and tegra_spi_copy_spi_rxbuf_to_client_rxbuf().
+ total_fifo_words = (max_len + 3)/4;
Need spaces around /. The same comment applies in some other places;
please search for them. Was checkpatch run? I'm not sure if catches this.
spi-tegra20-slink.c doesn't have that rounding; is just says:
total_fifo_words = max_len / 4;
Is that a bug in the old driver?
+static int tegra_spi_start_dma_based_transfer(
+ struct tegra_spi_data *tspi, struct spi_transfer *t)
...
+ if (tspi-cur_direction DATA_DIR_TX) {
+ tegra_spi_copy_client_txbuf_to_spi_txbuf(tspi, t);
+ ret = tegra_spi_start_tx_dma(tspi, len);
In spi-tegra20-slink.c, there's a wmb() right between those last two
lines. Is it needed here?
+static int tegra_spi_start_transfer_one(struct spi_device *spi,
+ struct spi_transfer *t, bool is_first_of_msg,
+ bool is_single_xfer)
...
+ /* possibly use the hw based chip select */
+ command1 |= SPI_CS_SW_HW;
+ if (spi-mode SPI_CS_HIGH)
+ command1 |= SPI_CS_SS_VAL;
+ else
+ command1 = ~SPI_CS_SS_VAL;
Why possibly; the code seems to always use HW chip select.
+static int tegra_spi_transfer_one_message(struct spi_master *master,
+ struct spi_message *msg)
...
+ ret = pm_runtime_get_sync(tspi-dev);
+ if (ret 0) {
+ dev_err(tspi-dev, runtime PM get failed: %d\n, ret);
+ msg-status = ret;
+ spi_finalize_current_message(master);
+ return ret;
+ }
In the older Tegra SPI drivers, the PM runtime logic was was of
master-{un,}prepare_transfer. I'm curious why it's implemented
differently here.
+static void tegra_spi_parse_dt(struct platform_device *pdev,
+ struct tegra_spi_data *tspi)
...
+ prop = of_get_property(np, spi-max-frequency, NULL);
+ if (prop)
+ tspi-spi_max_frequency = be32_to_cpup(prop);
The following might be better:
if (of_property_read_u32(np, spi-max-frequency,
tspi-spi_max_frequency))
tspi-spi_max_frequency = 2500; /* 25MHz */
(and you can remove the check of !tspi-spi_max_frequency from probe()
then too)
+static int tegra_spi_probe(struct platform_device *pdev)
...
+ if (!pdev-dev.of_node) {
+ dev_err(pdev-dev, Driver support DT registration only\n);
+ return -ENODEV;
+ }
I don't think there's much point checking that; see the Tegra20 SPI
cleanup patches I posted a couple days ago.
+ tspi-base = devm_request_and_ioremap(pdev-dev, r);
+ if (!tspi-base) {
The existing Tegra20 driver checks if (IS_ERR(tspi-base)) here. Which
is wrong?
+ tspi-clk = devm_clk_get(pdev-dev, spi);
Does this HW block use multiple clocks? If not, I think s/spi/NULL/
there, just like the Tegra20 driver.
As an overall comment, this driver is textually perhaps 80-90% the same
as spi-tegra20-slink.c. Instead of creating a completely new driver, how
nasty would a unified driver look; one which contained some runtime
conditionals for the register layout and programming differences? It
might be worth looking at, although perhaps it would turn out
[PATCH 2/4] spi: tegra sflash: assume CONFIG_OF, remove platform data
From: Stephen Warren swar...@nvidia.com
Tegra only supports, and always enables, device tree. Remove all ifdefs
and runtime checks for DT support from the driver. Platform data is
therefore no longer required. Rework the driver to parse the device tree
directly into struct tegra_sflash_data.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
drivers/spi/spi-tegra20-sflash.c | 41 +-
1 file changed, 9 insertions(+), 32 deletions(-)
diff --git a/drivers/spi/spi-tegra20-sflash.c b/drivers/spi/spi-tegra20-sflash.c
index 3d6a12b..d65c000 100644
--- a/drivers/spi/spi-tegra20-sflash.c
+++ b/drivers/spi/spi-tegra20-sflash.c
@@ -33,7 +33,6 @@
#include linux/of.h
#include linux/of_device.h
#include linux/spi/spi.h
-#include linux/spi/spi-tegra.h
#include linux/clk/tegra.h
#define SPI_COMMAND0x000
@@ -439,23 +438,13 @@ static irqreturn_t tegra_sflash_isr(int irq, void
*context_data)
return handle_cpu_based_xfer(tsd);
}
-static struct tegra_spi_platform_data *tegra_sflash_parse_dt(
- struct platform_device *pdev)
+static void tegra_sflash_parse_dt(struct tegra_sflash_data *tsd)
{
- struct tegra_spi_platform_data *pdata;
- struct device_node *np = pdev-dev.of_node;
- u32 max_freq;
-
- pdata = devm_kzalloc(pdev-dev, sizeof(*pdata), GFP_KERNEL);
- if (!pdata) {
- dev_err(pdev-dev, Memory alloc for pdata failed\n);
- return NULL;
- }
-
- if (!of_property_read_u32(np, spi-max-frequency, max_freq))
- pdata-spi_max_frequency = max_freq;
+ struct device_node *np = tsd-dev-of_node;
- return pdata;
+ if (of_property_read_u32(np, spi-max-frequency,
+ tsd-spi_max_frequency))
+ tsd-spi_max_frequency = 2500; /* 25MHz */
}
static struct of_device_id tegra_sflash_of_match[] = {
@@ -469,28 +458,15 @@ static int tegra_sflash_probe(struct platform_device
*pdev)
struct spi_master *master;
struct tegra_sflash_data*tsd;
struct resource *r;
- struct tegra_spi_platform_data *pdata = pdev-dev.platform_data;
int ret;
const struct of_device_id *match;
- match = of_match_device(of_match_ptr(tegra_sflash_of_match),
- pdev-dev);
+ match = of_match_device(tegra_sflash_of_match, pdev-dev);
if (!match) {
dev_err(pdev-dev, Error: No device match found\n);
return -ENODEV;
}
- if (!pdata pdev-dev.of_node)
- pdata = tegra_sflash_parse_dt(pdev);
-
- if (!pdata) {
- dev_err(pdev-dev, No platform data, exiting\n);
- return -ENODEV;
- }
-
- if (!pdata-spi_max_frequency)
- pdata-spi_max_frequency = 2500; /* 25MHz */
-
master = spi_alloc_master(pdev-dev, sizeof(*tsd));
if (!master) {
dev_err(pdev-dev, master allocation failed\n);
@@ -510,6 +486,8 @@ static int tegra_sflash_probe(struct platform_device *pdev)
tsd-dev = pdev-dev;
spin_lock_init(tsd-lock);
+ tegra_sflash_parse_dt(tsd);
+
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!r) {
dev_err(pdev-dev, No IO memory resource\n);
@@ -538,7 +516,6 @@ static int tegra_sflash_probe(struct platform_device *pdev)
goto exit_free_irq;
}
- tsd-spi_max_frequency = pdata-spi_max_frequency;
init_completion(tsd-xfer_completion);
pm_runtime_enable(pdev-dev);
if (!pm_runtime_enabled(pdev-dev)) {
@@ -658,7 +635,7 @@ static struct platform_driver tegra_sflash_driver = {
.name = spi-tegra-sflash,
.owner = THIS_MODULE,
.pm = slink_pm_ops,
- .of_match_table = of_match_ptr(tegra_sflash_of_match),
+ .of_match_table = tegra_sflash_of_match,
},
.probe =tegra_sflash_probe,
.remove = tegra_sflash_remove,
--
1.7.10.4
--
The Go Parallel Website, sponsored by Intel - in partnership with Geeknet,
is your hub for all things parallel software development, from weekly thought
leadership blogs to news, videos, case studies, tutorials, tech docs,
whitepapers, evaluation guides, and opinion stories. Check out the most
recent posts - join the conversation now. http://goparallel.sourceforge.net/
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH 1/4] spi: tegra slink: remove redundant code
From: Stephen Warren swar...@nvidia.com
There is no code to set spi-controller_data, and hence the HW CS logic
can never trigger. Remove the unused code.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
drivers/spi/spi-tegra20-slink.c | 32 +---
1 file changed, 1 insertion(+), 31 deletions(-)
diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c
index b8698b3..00f1b06 100644
--- a/drivers/spi/spi-tegra20-slink.c
+++ b/drivers/spi/spi-tegra20-slink.c
@@ -189,7 +189,6 @@ struct tegra_slink_data {
unsigneddma_buf_size;
unsignedmax_buf_size;
boolis_curr_dma_xfer;
- boolis_hw_based_cs;
struct completion rx_dma_complete;
struct completion tx_dma_complete;
@@ -720,7 +719,6 @@ static int tegra_slink_start_transfer_one(struct spi_device
*spi,
u8 bits_per_word;
unsigned total_fifo_words;
int ret;
- struct tegra_spi_device_controller_data *cdata = spi-controller_data;
unsigned long command;
unsigned long command2;
@@ -743,39 +741,11 @@ static int tegra_slink_start_transfer_one(struct
spi_device *spi,
command = tspi-def_command_reg;
command |= SLINK_BIT_LENGTH(bits_per_word - 1);
+ command |= SLINK_CS_SW | SLINK_CS_VALUE;
command2 = tspi-def_command2_reg;
command2 |= SLINK_SS_EN_CS(spi-chip_select);
- /* possibly use the hw based chip select */
- tspi-is_hw_based_cs = false;
- if (cdata cdata-is_hw_based_cs is_single_xfer
- ((tspi-curr_dma_words * tspi-bytes_per_word) ==
- (t-len - tspi-cur_pos))) {
- int setup_count;
- int sts2;
-
- setup_count = cdata-cs_setup_clk_count 1;
- setup_count = max(setup_count, 3);
- command2 |= SLINK_SS_SETUP(setup_count);
- if (tspi-chip_data-cs_hold_time) {
- int hold_count;
-
- hold_count = cdata-cs_hold_clk_count;
- hold_count = max(hold_count, 0xF);
- sts2 = tegra_slink_readl(tspi, SLINK_STATUS2);
- sts2 = ~SLINK_SS_HOLD_TIME(0xF);
- sts2 |= SLINK_SS_HOLD_TIME(hold_count);
- tegra_slink_writel(tspi, sts2, SLINK_STATUS2);
- }
- tspi-is_hw_based_cs = true;
- }
-
- if (tspi-is_hw_based_cs)
- command = ~SLINK_CS_SW;
- else
- command |= SLINK_CS_SW | SLINK_CS_VALUE;
-
command = ~SLINK_MODES;
if (spi-mode SPI_CPHA)
command |= SLINK_CK_SDA;
--
1.7.10.4
--
The Go Parallel Website, sponsored by Intel - in partnership with Geeknet,
is your hub for all things parallel software development, from weekly thought
leadership blogs to news, videos, case studies, tutorials, tech docs,
whitepapers, evaluation guides, and opinion stories. Check out the most
recent posts - join the conversation now. http://goparallel.sourceforge.net/
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH 3/4] spi: tegra slink: assume CONFIG_OF, remove platform data
From: Stephen Warren swar...@nvidia.com
Tegra only supports, and always enables, device tree. Remove all ifdefs
and runtime checks for DT support from the driver. Platform data is
therefore no longer required. Rework the driver to parse the device tree
directly into struct tegra_slink_data.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
drivers/spi/spi-tegra20-slink.c | 45 ++-
1 file changed, 11 insertions(+), 34 deletions(-)
diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c
index 00f1b06..6a15f63 100644
--- a/drivers/spi/spi-tegra20-slink.c
+++ b/drivers/spi/spi-tegra20-slink.c
@@ -34,7 +34,6 @@
#include linux/of.h
#include linux/of_device.h
#include linux/spi/spi.h
-#include linux/spi/spi-tegra.h
#include linux/clk/tegra.h
#define SLINK_COMMAND 0x000
@@ -1042,29 +1041,18 @@ static irqreturn_t tegra_slink_isr(int irq, void
*context_data)
return IRQ_WAKE_THREAD;
}
-static struct tegra_spi_platform_data *tegra_slink_parse_dt(
- struct platform_device *pdev)
+static void tegra_slink_parse_dt(struct tegra_slink_data *tspi)
{
- struct tegra_spi_platform_data *pdata;
- const unsigned int *prop;
- struct device_node *np = pdev-dev.of_node;
+ struct device_node *np = tspi-dev-of_node;
u32 of_dma[2];
- pdata = devm_kzalloc(pdev-dev, sizeof(*pdata), GFP_KERNEL);
- if (!pdata) {
- dev_err(pdev-dev, Memory alloc for pdata failed\n);
- return NULL;
- }
-
if (of_property_read_u32_array(np, nvidia,dma-request-selector,
of_dma, 2) = 0)
- pdata-dma_req_sel = of_dma[1];
+ tspi-dma_req_sel = of_dma[1];
- prop = of_get_property(np, spi-max-frequency, NULL);
- if (prop)
- pdata-spi_max_frequency = be32_to_cpup(prop);
-
- return pdata;
+ if (of_property_read_u32(np, spi-max-frequency,
+ tspi-spi_max_frequency))
+ tspi-spi_max_frequency = 2500; /* 25MHz */
}
const struct tegra_slink_chip_data tegra30_spi_cdata = {
@@ -1087,27 +1075,16 @@ static int tegra_slink_probe(struct platform_device
*pdev)
struct spi_master *master;
struct tegra_slink_data *tspi;
struct resource *r;
- struct tegra_spi_platform_data *pdata = pdev-dev.platform_data;
int ret, spi_irq;
const struct tegra_slink_chip_data *cdata = NULL;
const struct of_device_id *match;
- match = of_match_device(of_match_ptr(tegra_slink_of_match), pdev-dev);
+ match = of_match_device(tegra_slink_of_match, pdev-dev);
if (!match) {
dev_err(pdev-dev, Error: No device match found\n);
return -ENODEV;
}
cdata = match-data;
- if (!pdata pdev-dev.of_node)
- pdata = tegra_slink_parse_dt(pdev);
-
- if (!pdata) {
- dev_err(pdev-dev, No platform data, exiting\n);
- return -ENODEV;
- }
-
- if (!pdata-spi_max_frequency)
- pdata-spi_max_frequency = 2500; /* 25MHz */
master = spi_alloc_master(pdev-dev, sizeof(*tspi));
if (!master) {
@@ -1127,11 +1104,12 @@ static int tegra_slink_probe(struct platform_device
*pdev)
dev_set_drvdata(pdev-dev, master);
tspi = spi_master_get_devdata(master);
tspi-master = master;
- tspi-dma_req_sel = pdata-dma_req_sel;
tspi-dev = pdev-dev;
tspi-chip_data = cdata;
spin_lock_init(tspi-lock);
+ tegra_slink_parse_dt(tspi);
+
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!r) {
dev_err(pdev-dev, No IO memory resource\n);
@@ -1165,9 +1143,8 @@ static int tegra_slink_probe(struct platform_device *pdev)
tspi-max_buf_size = SLINK_FIFO_DEPTH 2;
tspi-dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
- tspi-spi_max_frequency = pdata-spi_max_frequency;
- if (pdata-dma_req_sel) {
+ if (tspi-dma_req_sel) {
ret = tegra_slink_init_dma_param(tspi, true);
if (ret 0) {
dev_err(pdev-dev, RxDma Init failed, err %d\n, ret);
@@ -1310,7 +1287,7 @@ static struct platform_driver tegra_slink_driver = {
.name = spi-tegra-slink,
.owner = THIS_MODULE,
.pm = slink_pm_ops,
- .of_match_table = of_match_ptr(tegra_slink_of_match),
+ .of_match_table = tegra_slink_of_match,
},
.probe =tegra_slink_probe,
.remove = tegra_slink_remove,
--
1.7.10.4
--
The Go Parallel Website, sponsored by Intel - in partnership with Geeknet,
is your hub for all things parallel software development, from
[PATCH 4/4] spi: remove unused Tegra platform data header
From: Stephen Warren swar...@nvidia.com
The platform data header is no longer used. Delete it.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
include/linux/spi/spi-tegra.h | 40
1 file changed, 40 deletions(-)
delete mode 100644 include/linux/spi/spi-tegra.h
diff --git a/include/linux/spi/spi-tegra.h b/include/linux/spi/spi-tegra.h
deleted file mode 100644
index 786932c..000
--- a/include/linux/spi/spi-tegra.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * spi-tegra.h: SPI interface for Nvidia Tegra20 SLINK controller.
- *
- * Copyright (C) 2011 NVIDIA Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-#ifndef _LINUX_SPI_TEGRA_H
-#define _LINUX_SPI_TEGRA_H
-
-struct tegra_spi_platform_data {
- int dma_req_sel;
- unsigned int spi_max_frequency;
-};
-
-/*
- * Controller data from device to pass some info like
- * hw based chip select can be used or not and if yes
- * then CS hold and setup time.
- */
-struct tegra_spi_device_controller_data {
- bool is_hw_based_cs;
- int cs_setup_clk_count;
- int cs_hold_clk_count;
-};
-
-#endif /* _LINUX_SPI_TEGRA_H */
--
1.7.10.4
--
The Go Parallel Website, sponsored by Intel - in partnership with Geeknet,
is your hub for all things parallel software development, from weekly thought
leadership blogs to news, videos, case studies, tutorials, tech docs,
whitepapers, evaluation guides, and opinion stories. Check out the most
recent posts - join the conversation now. http://goparallel.sourceforge.net/
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH v2 01/10] spi: tegra: Do not use clock name to get clock
On 01/11/2013 01:01 AM, Prashant Gaikwad wrote:
Since Tegra spi devices do not have multiple clocks, no need to use
clock name to get the clock.
Cc'ing in the SPI maintainers as an FYI and for Acks; this patch needs
to go through the Tegra tree due to dependencies.
Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---
This series depends on v4 of Tegra's ccf-rework patch series.
Tested on Ventana (Tegra20) and Cardhu (Tegra30).
Rebased on Tegra's for-3.9/soc and for-3.9/cleanup.
Changes from V1:
- Fixed clock lookup for SPI and nvec drivers.
- Add clock information for nvec in device tree.
---
drivers/spi/spi-tegra20-sflash.c |2 +-
drivers/spi/spi-tegra20-slink.c |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-tegra20-sflash.c
b/drivers/spi/spi-tegra20-sflash.c
index 02feaa5..e5dce91 100644
--- a/drivers/spi/spi-tegra20-sflash.c
+++ b/drivers/spi/spi-tegra20-sflash.c
@@ -525,7 +525,7 @@ static int tegra_sflash_probe(struct platform_device
*pdev)
goto exit_free_master;
}
- tsd-clk = devm_clk_get(pdev-dev, spi);
+ tsd-clk = devm_clk_get(pdev-dev, NULL);
if (IS_ERR(tsd-clk)) {
dev_err(pdev-dev, can not get clock\n);
ret = PTR_ERR(tsd-clk);
diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c
index fa208a5..e255e7a 100644
--- a/drivers/spi/spi-tegra20-slink.c
+++ b/drivers/spi/spi-tegra20-slink.c
@@ -1191,7 +1191,7 @@ static int tegra_slink_probe(struct platform_device
*pdev)
goto exit_free_master;
}
- tspi-clk = devm_clk_get(pdev-dev, slink);
+ tspi-clk = devm_clk_get(pdev-dev, NULL);
if (IS_ERR(tspi-clk)) {
dev_err(pdev-dev, can not get clock\n);
ret = PTR_ERR(tspi-clk);
--
Master HTML5, CSS3, ASP.NET, MVC, AJAX, Knockout.js, Web API and
much more. Get web development skills now with LearnDevNow -
350+ hours of step-by-step video tutorials by Microsoft MVPs and experts.
SALE $99.99 this month only -- learn more at:
http://p.sf.net/sfu/learnmore_122812
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH] spi: tegra: slink: do not prepare dma transfer with DMA_CTRL_ACK flag
On 11/23/2012 02:22 AM, Laxman Dewangan wrote: Spi starts transfer using dma with DMA_CTRL_ACK which is not require becasue spi driver does not use completed dma_desc after transfer done and so it does not ack the dma descriptor. Removing the DMA_CTRL_ACK flag to avoid memory leak in dma driver. I'm not quite sure, but isn't this the opposite of what's wanted. I think that setting this flag in prep() means that the SPI driver need not explicitly ack it later? At least, tegra_dma_desc_get() returns an allocated descriptor if one exists and async_tx_test_ack()==true for it, and it's true when the DMA_CTRL_ACK flag is set, which happens either due to calling async_tx_ack(), or because tegra_dma_prep_slave_sg() was called with DMA_CTRL_ACK in flags. -- Monitor your physical, virtual and cloud infrastructure from a single web console. Get in-depth insight into apps, servers, databases, vmware, SAP, cloud infrastructure, etc. Download 30-day Free Trial. Pricing starts from $795 for 25 servers or applications! http://p.sf.net/sfu/zoho_dev2dev_nov ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH] spi: tegra: add spi driver for sflash controller
On 11/12/2012 10:00 PM, Laxman Dewangan wrote:
Nvidia's Tegra20 have the SPI (SFLASH) controller to
interface with spi flash device which is used for system
boot. Add the spi driver for this controller.
diff --git a/drivers/spi/spi-tegra20-sflash.c
b/drivers/spi/spi-tegra20-sflash.c
+static void tegra_sflash_clear_status(struct tegra_sflash_data *tsd)
+{
+ unsigned long val;
+ unsigned long val_write = 0;
+
+ val = tegra_sflash_readl(tsd, SPI_STATUS);
Why the read of the unused value. Is this to flush earlier bus
transactions, or just left over? If for bus flushing, a comment would be
useful.
+ /* Write 1 to clear status register */
+ val_write = SPI_RDY | SPI_FIFO_ERROR;
+ tegra_sflash_writel(tsd, val_write, SPI_STATUS);
+}
+static irqreturn_t handle_cpu_based_xfer(struct tegra_sflash_data *tsd)
+{
+ struct spi_transfer *t = tsd-curr_xfer;
+ unsigned long flags;
+
+ spin_lock_irqsave(tsd-lock, flags);
+ if (tsd-tx_status || tsd-rx_status ||
Nit: double-space after first || above.
+static struct tegra_spi_platform_data *tegra_sflash_parse_dt(
+ struct platform_device *pdev)
+ prop = of_get_property(np, spi-max-frequency, NULL);
+ if (prop)
+ pdata-spi_max_frequency = be32_to_cpup(prop);
Perhaps use of_property_read_u32()?
+static int __devinit tegra_sflash_probe(struct platform_device *pdev)
+ tsd-clk = devm_clk_get(pdev-dev, spi);
+ if (IS_ERR(tsd-clk)) {
+ dev_err(pdev-dev, can not get clock\n);
+ ret = PTR_ERR(tsd-clk);
+ goto exit_free_irq;
+ }
+
+
+ tsd-spi_max_frequency = pdata-spi_max_frequency;
Nit: Double blank-line there.
+static int tegra_sflash_resume(struct device *dev)
+{
+ struct spi_master *master = dev_get_drvdata(dev);
+ struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
+ int ret;
+
+ ret = pm_runtime_get_sync(dev);
+ if (ret 0) {
+ dev_err(dev, pm runtime failed, e = %d\n, ret);
+ return ret;
+ }
+ tegra_sflash_writel(tsd, tsd-command_reg, SPI_COMMAND);
+ pm_runtime_put(dev);
Can we avoid this whole function simply by programming SPI_COMMAND at
the start of each transaction? That seems simpler. I assume that
shouldn't e.g. leave any chip-selects in some bad state, or at least if
it does, that shouldn't be a problem, because before the driver probes()
at kernel boot, SPI_COMMAND won't have been programmed either.
Aside from that,
Acked-by: Stephen Warren swar...@nvidia.com
Tested-by: Stephen Warren swar...@nvidia.com
Thanks.
--
Monitor your physical, virtual and cloud infrastructure from a single
web console. Get in-depth insight into apps, servers, databases, vmware,
SAP, cloud infrastructure, etc. Download 30-day Free Trial.
Pricing starts from $795 for 25 servers or applications!
http://p.sf.net/sfu/zoho_dev2dev_nov
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH] spi: tegra: sequence compatible strings as per preference
On 11/09/2012 02:07 AM, Laxman Dewangan wrote: Sequence compatible list for tegra20-slink driver to first look for Tegra30 and then Tegra20. Tegra30 have additional feature in HW which need to be utilize if it is provided from DT. I don't object to this patch. However just FYI, it should not be necessary for correctness; The DT matching order is supposed to be driven purely by the order of the compatible values in the DT now, and not affected by the order of values in the table. (This wasn't always the case, but was a bug that was fixed IIRC by Thierry Reding). -- Everyone hates slow websites. So do we. Make your web apps faster with AppDynamics Download AppDynamics Lite for free today: http://p.sf.net/sfu/appdyn_d2d_nov ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH] spi: tegra: sequence compatible strings as per preference
On 11/09/2012 10:10 AM, Mark Brown wrote: On Fri, Nov 09, 2012 at 10:04:56AM -0700, Stephen Warren wrote: However just FYI, it should not be necessary for correctness; The DT matching order is supposed to be driven purely by the order of the compatible values in the DT now, and not affected by the order of values in the table. (This wasn't always the case, but was a bug that was fixed IIRC by Thierry Reding). I guess the driver is being used backported in older kernels which don't have that fix? That sounds likely. Laxman, it'd be a good idea to track down the fix to the DT matching code and backport it, so that hard-to debug issues aren't caused by the lack of that patch! -- Everyone hates slow websites. So do we. Make your web apps faster with AppDynamics Download AppDynamics Lite for free today: http://p.sf.net/sfu/appdyn_d2d_nov ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH V3] spi: tegra: add spi driver for SLINK controller
On 10/30/2012 01:04 AM, Laxman Dewangan wrote: Tegra20/Tegra30 supports the spi interface through its SLINK controller. Add spi driver for SLINK controller. Reviewed-by: Stephen Warren swar...@nvidia.com -- Everyone hates slow websites. So do we. Make your web apps faster with AppDynamics Download AppDynamics Lite for free today: http://p.sf.net/sfu/appdyn_sfd2d_oct ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH] spi: tegra: add spi driver for SLINK controller
On 10/29/2012 10:18 AM, Laxman Dewangan wrote: On Monday 29 October 2012 08:47 PM, Stephen Warren wrote: On 10/26/2012 12:49 PM, Laxman Dewangan wrote: Why not just always set SLINK_FIFO_ERROR; does it have to be set in the write only if the status was previously asserted? If that is true, how do you avoid a race condition where the bit gets set in SLINK_STATUS after you read it but before you write to clear it? Status gets updated together. There is no steps of updating status. Sorry, I don't understand this answer. The status should be updated once by HW and so there is no race condition. HW behavior is that if the tx or Rx error occurs, it updates the status, generates interrupt and still continue transfer and later on, it generates the ready. In first isr, we read status, error status found and so in isr thread, we reset controller to stop the transfer. So in good state, only ready bit will be set and hence writing 1 to clear it. In error state, clearing error first in ISR and in isr thread resetting the controller to stop the controller engine. OK, I see why there's no race. It still seems simply to me if tegra_slink_clear_status() just always writes all the status bits, but I suppose it isn't a correctness issue. Is there a way to support the reset of controller. We will need this functionality. Why do we need to reset the controller at all; can't we simply program all the (few) configuration registers? Are there HW bugs that hang the controller and require a reset or something? HW generates error, then interrupt and still continue transfer and later point of time it generates the transfer done. We want to stop the transfer once error get detected. For this we need to reset controller. I did disabling rx and tx but still controller shows as busy. Oh dear. Well, I guess it'll have to be OK then; we'll just have to find a way of decoupling this API from the mach-tegra directory later:-( -- The Windows 8 Center - In partnership with Sourceforge Your idea - your app - 30 days. Get started! http://windows8center.sourceforge.net/ what-html-developers-need-to-know-about-coding-windows-8-metro-style-apps/ ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH V2] spi: tegra: add spi driver for SLINK controller
On 10/29/2012 11:18 AM, Laxman Dewangan wrote:
Tegra20/Tegra30 supports the spi interface through its SLINK
controller. Add spi driver for SLINK controller.
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
+config SPI_TEGRA20_SLINK
+ tristate Nvidia Tegra20/Tegra30 SLINK Controller
+ depends on ARCH_TEGRA TEGRA20_APB_DMA
I think it depends on DMAENGINE, not the specific driver now, doesn't it?
+static unsigned tegra_slink_fill_tx_fifo_from_client_txbuf(
+ struct tegra_slink_data *tspi, struct spi_transfer *t)
+ if (tspi-is_packed) {
+ fifo_words_left = tx_empty_count * tspi-words_per_32bit;
+ written_words = min(fifo_words_left, tspi-curr_dma_words);
+ nbytes = written_words * tspi-bytes_per_word;
+ max_n_32bit = DIV_ROUND_UP(nbytes, 4);
+ for (count = 0; count max_n_32bit; count++) {
+ x = 0;
+ for (i = 0; (i 4) nbytes; i++, nbytes--)
+ x |= (*tx_buf++) (i*8);
+ tegra_slink_writel(tspi, x, SLINK_TX_FIFO);
+ }
+ } else {
+ max_n_32bit = min(tspi-curr_dma_words, tx_empty_count);
+ written_words = max_n_32bit;
+ nbytes = written_words * tspi-bytes_per_word;
+ for (count = 0; count max_n_32bit; count++) {
+ x = 0;
+ for (i = 0; nbytes (i tspi-bytes_per_word);
+ i++, nbytes--)
+ x |= ((*tx_buf++) i*8);
+ tegra_slink_writel(tspi, x, SLINK_TX_FIFO);
+ }
+ }
The if and the else there are basically identical now. Can't the else
branch simply be replaced by the if branch? At most I think the
difference comes down to max_n_32bit v.s. fifo_words_left calculations
being slight different; everything else is the same.
I suppose this isn't a big deal though; we could clean it up later if
necessary.
+static int tegra_slink_start_cpu_based_transfer(
+ struct tegra_slink_data *tspi, struct spi_transfer *t)
+ tspi-is_curr_dma_xfer = false;
+ if (tspi-is_packed) {
+ val |= SLINK_PACKED;
+ tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
+ udelay(1);
+ wmb();
Why the udelay() and wmb()?
+static int tegra_slink_runtime_suspend(struct device *dev)
+{
+ struct spi_master *master = dev_get_drvdata(dev);
+ struct tegra_slink_data *tspi = spi_master_get_devdata(master);
+
+ tegra_slink_clk_unprepare(tspi);
+ return 0;
+}
+
+static int tegra_slink_runtime_resume(struct device *dev)
+{
+ struct spi_master *master = dev_get_drvdata(dev);
+ struct tegra_slink_data *tspi = spi_master_get_devdata(master);
+
+ return tegra_slink_clk_prepare(tspi);
+}
Why not move the body of tegra_slink_clk_{un,prepare} inside those
functions, since they're only called from those functions?
+MODULE_ALIAS(platform:tegra_slink-slink);
I think that's a typo.
--
The Windows 8 Center - In partnership with Sourceforge
Your idea - your app - 30 days.
Get started!
http://windows8center.sourceforge.net/
what-html-developers-need-to-know-about-coding-windows-8-metro-style-apps/
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH] spi: tegra: add spi driver for SLINK controller
On 10/18/2012 04:47 AM, Laxman Dewangan wrote:
Tegra20/Tegra30 supports the spi interface through its SLINK
controller. Add spi driver for SLINK controller.
diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c
+static inline void tegra_slink_writel(struct tegra_slink_data *tspi,
+ unsigned long val, unsigned long reg)
+{
+ writel(val, tspi-base + reg);
+
+ /* Read back register to make sure that register writes completed */
+ if (reg != SLINK_TX_FIFO)
+ readl(tspi-base + SLINK_MAS_DATA);
Is that really necessary on every single write, or only for certain
specific operations? This seems rather heavy-weight.
+static void tegra_slink_clear_status(struct tegra_slink_data *tspi)
+{
+ unsigned long val;
+ unsigned long val_write = 0;
+
+ val = tegra_slink_readl(tspi, SLINK_STATUS);
+
+ /* Write 1 to clear status register */
+ val_write = SLINK_RDY;
+ val_write |= (val SLINK_FIFO_ERROR);
Why not just always set SLINK_FIFO_ERROR; does it have to be set in the
write only if the status was previously asserted? If that is true, how
do you avoid a race condition where the bit gets set in SLINK_STATUS
after you read it but before you write to clear it?
+ tegra_slink_writel(tspi, val_write, SLINK_STATUS);
+}
+static unsigned tegra_slink_calculate_curr_xfer_param(
+ if (bits_per_word == 8 || bits_per_word == 16) {
+ tspi-is_packed = 1;
+ tspi-words_per_32bit = 32/bits_per_word;
Spaces required around all operators. Does this pass checkpatch? No:
total: 1405 errors, 11 warnings, 1418 lines checked
+static unsigned tegra_slink_fill_tx_fifo_from_client_txbuf(
+ if (tspi-is_packed) {
+ nbytes = tspi-curr_dma_words * tspi-bytes_per_word;
+ max_n_32bit = (min(nbytes, tx_empty_count*4) - 1)/4 + 1;
+ for (count = 0; count max_n_32bit; ++count) {
Very minor almost irrelevant nit: count++ would be much more typical here.
+ x = 0;
+ for (i = 0; (i 4) nbytes; i++, nbytes--)
+ x |= (*tx_buf++) (i*8);
+ tegra_slink_writel(tspi, x, SLINK_TX_FIFO);
+ }
+ written_words = min(max_n_32bit * tspi-words_per_32bit,
+ tspi-curr_dma_words);
The calculations here seem a little over-complex. Why not calculate the
FIFO space in words above, and just set written words based on that.
Something like:
fifo_words_left = tx_empty_count * spi-words_per_32bit;
written_words = min(fifo_words_left, tspi-curr_dma_words);
nbytes = written_words * spi-bytes_per_word;
max_n_32bit = (nbytes + 3) / 4;
Most likely a similar comment applies to all the other similar functions
for filling FIFOs and buffers.
In fact, I suspect you can completely get rid of the if (is_packed)
statement here by appropriately parameterising the code using variables
in *spi...
+static unsigned int tegra_slink_read_rx_fifo_to_client_rxbuf(
+ bits_per_word = t-bits_per_word ? t-bits_per_word :
+ tspi-cur_spi-bits_per_word;
That logic is repeated a few times. Shouldn't there be a macro to avoid
cut/paste. Perhaps even in the SPI core rather than this driver.
+ rx_mask = (1 bits_per_word) - 1;
+ for (count = 0; count rx_full_count; ++count) {
+ x = tegra_slink_readl(tspi, SLINK_RX_FIFO);
+ x = rx_mask;
I don't think you need that mask; the loop below only extracts bytes
that actually exist in the FIFO right?
+ for (i = 0; (i tspi-bytes_per_word); ++i)
+ *rx_buf++ = (x (i*8)) 0xFF;
+static void tegra_slink_copy_client_txbuf_to_spi_txbuf(
+ struct tegra_slink_data *tspi, struct spi_transfer *t)
Are there no cases where we can simply DMA straight into the client
buffer? I suppose it would be limited to cache-line-aligned
cache-line-size-aligned buffers which is probably unlikely in general:-(
+static int tegra_slink_start_dma_based_transfer(
+ struct tegra_slink_data *tspi, struct spi_transfer *t)
+ /* Make sure that Rx and Tx fifo are empty */
+ status = tegra_slink_readl(tspi, SLINK_STATUS);
+ if ((status SLINK_FIFO_EMPTY) != SLINK_FIFO_EMPTY)
+ dev_err(tspi-dev,
+ Rx/Tx fifo are not empty status 0x%08lx\n, status);
Shouldn't this return an error, or drain the FIFO, or something?
+static int tegra_slink_init_dma_param(struct tegra_slink_data *tspi,
+ if (dma_to_memory) {
+ dma_sconfig.src_addr = tspi-phys + SLINK_RX_FIFO;
+ dma_sconfig.dst_addr = tspi-phys + SLINK_RX_FIFO;
+ } else {
+ dma_sconfig.src_addr = tspi-phys + SLINK_TX_FIFO;
+ dma_sconfig.dst_addr = tspi-phys + SLINK_TX_FIFO;
+ }
[PATCH] spi: remove completely broken Tegra driver
From: Stephen Warren swar...@nvidia.com The current SPI driver has many issues. Examples are: * Segfaulting on most transfers due to expecting all transfers to have both RX and TX buffers. * Hanging on TX transfers since the whole driver flow is driven by RX DMA completion, but the HW is only told to enable RX for RX transfers. * Use of clk_disable_unprepare() from atomic context. * Once those and other minor issues are fixed, the driver still doesn't actually work. * The driver also implements a deprecated API to the SPI core. For this reason, simply remove the driver completely. This has two advantages: 1) This will remove the last use of Tegra's mach/dma.h, which will allow that file to be removed, which is required for single zImage work. 2) The downstream driver is significaly different from the current code. I believe a patch to re-add the downstream driver (with appropriate cleanup) will be much simpler to review if it's a new file rather than randomly interspered with essentially unrelated existing code. Signed-off-by: Stephen Warren swar...@nvidia.com --- Mark, If this can be taken through the SPI tree for 3.7 that'd be great. If it needs to be deferred to 3.8, we will need to start talking dependencies, since I'd like to take a patch through the Tegra tree to delete mach/dma.h in 3.8. --- drivers/spi/Kconfig |6 - drivers/spi/Makefile|1 - drivers/spi/spi-tegra.c | 702 --- 3 files changed, 0 insertions(+), 709 deletions(-) delete mode 100644 drivers/spi/spi-tegra.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 63a7943..ecc31a1 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -377,12 +377,6 @@ config SPI_MXS help SPI driver for Freescale MXS devices. -config SPI_TEGRA - tristate Nvidia Tegra SPI controller - depends on ARCH_TEGRA (TEGRA_SYSTEM_DMA || TEGRA20_APB_DMA) - help - SPI driver for NVidia Tegra SoCs - config SPI_TI_SSP tristate TI Sequencer Serial Port - SPI Support depends on MFD_TI_SSP diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 9387056..22fd3a7 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -59,7 +59,6 @@ obj-$(CONFIG_SPI_SH_MSIOF)+= spi-sh-msiof.o obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o obj-$(CONFIG_SPI_SIRF) += spi-sirf.o obj-$(CONFIG_SPI_STMP3XXX) += spi-stmp.o -obj-$(CONFIG_SPI_TEGRA)+= spi-tegra.o obj-$(CONFIG_SPI_TI_SSP) += spi-ti-ssp.o obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x0.o obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o diff --git a/drivers/spi/spi-tegra.c b/drivers/spi/spi-tegra.c deleted file mode 100644 index e28445d..000 --- a/drivers/spi/spi-tegra.c +++ /dev/null @@ -1,702 +0,0 @@ -/* - * Driver for Nvidia TEGRA spi controller. - * - * Copyright (C) 2010 Google, Inc. - * - * Author: - * Erik Gilling konk...@android.com - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include linux/kernel.h -#include linux/module.h -#include linux/init.h -#include linux/err.h -#include linux/platform_device.h -#include linux/io.h -#include linux/dma-mapping.h -#include linux/dmapool.h -#include linux/clk.h -#include linux/interrupt.h -#include linux/delay.h - -#include linux/spi/spi.h -#include linux/dmaengine.h - -#include mach/dma.h - -#define SLINK_COMMAND 0x000 -#define SLINK_BIT_LENGTH(x) (((x) 0x1f) 0) -#define SLINK_WORD_SIZE(x) (((x) 0x1f) 5) -#define SLINK_BOTH_EN(1 10) -#define SLINK_CS_SW (1 11) -#define SLINK_CS_VALUE (1 12) -#define SLINK_CS_POLARITY(1 13) -#define SLINK_IDLE_SDA_DRIVE_LOW (0 16) -#define SLINK_IDLE_SDA_DRIVE_HIGH(1 16) -#define SLINK_IDLE_SDA_PULL_LOW (2 16) -#define SLINK_IDLE_SDA_PULL_HIGH (3 16) -#define SLINK_IDLE_SDA_MASK (3 16) -#define SLINK_CS_POLARITY1 (1 20) -#define SLINK_CK_SDA (1 21) -#define SLINK_CS_POLARITY2 (1 22) -#define SLINK_CS_POLARITY3 (1 23) -#define SLINK_IDLE_SCLK_DRIVE_LOW(0 24) -#define SLINK_IDLE_SCLK_DRIVE_HIGH (1 24) -#define SLINK_IDLE_SCLK_PULL_LOW (2 24) -#define SLINK_IDLE_SCLK_PULL_HIGH(3 24) -#define SLINK_IDLE_SCLK_MASK (3 24) -#define SLINK_M_S(1 28) -#define SLINK_WAIT
Re: [PATCH 5/5] ASoC: tegra: remove support of legacy DMA driver based access
On 09/06/2012 05:50 PM, Stephen Warren wrote: On 08/16/2012 08:13 AM, Laxman Dewangan wrote: Remove the support code which uses the legacy APB DMA driver for accessing the I2S FIFO. The driver will use the dmaengine based APB DMA driver for accessing reqding/writing to I2S FIFO. Signed-off-by: Laxman Dewangan ldewan...@nvidia.com Mark, Liam, I'd like to take this patch through the Tegra tree, since it relies on the previous Tegra patches to convert to dmaengine. Could I please get an ack if that's OK? Thanks. I'm still looking for an ack. -- Got visibility? Most devs has no idea what their production app looks like. Find out how fast your code is with AppDynamics Lite. http://ad.doubleclick.net/clk;262219671;13503038;y? http://info.appdynamics.com/FreeJavaPerformanceDownload.html ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH 4/5] spi: tegra: remove support of legacy DMA driver based access
On 09/06/2012 05:50 PM, Stephen Warren wrote: On 08/16/2012 08:13 AM, Laxman Dewangan wrote: Remove the support code which uses the legacy APB DMA driver for accessing the SPI FIFO. The driver will use the dmaengine based APB DMA driver for accessing reqding/writing to SPI FIFO. Signed-off-by: Laxman Dewangan ldewan...@nvidia.com Grant, Mark, I'd like to take this patch through the Tegra tree, since it relies on the previous Tegra patches to convert to dmaengine. Could I please get an ack if that's OK? Thanks. I'm still looking for an ack. -- Got visibility? Most devs has no idea what their production app looks like. Find out how fast your code is with AppDynamics Lite. http://ad.doubleclick.net/clk;262219671;13503038;y? http://info.appdynamics.com/FreeJavaPerformanceDownload.html ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH 5/5] ASoC: tegra: remove support of legacy DMA driver based access
On 09/14/2012 09:53 AM, Mark Brown wrote: On Thu, Sep 13, 2012 at 05:36:30PM -0600, Stephen Warren wrote: Please note that I've applied this to Tegra's for-3.7/dmaengine branch, even though it hasn't been ack'd by an ASoC maintainer. Please don't apply this without review, we've got quite enough problems with the dmaengine stuff as it is unfortunately so I want to keep a handle on what's going on. I didn't look at it since when it was originally posted people found problems in testing so I was expecting a respin of the series. OK, I'll remove the series from next then. But do note that I pinged 8 days ago for an ack, and received no objections, and you were well aware that the bug was fixed since you applied the fix to the Tegra ASoC PCM driver yourself, and we had discussed this being a dependency for the dmaengine patches, and you'd told me to just base the Tegra branch on top of your tree until a signed tag was available for me to base upon. -- Got visibility? Most devs has no idea what their production app looks like. Find out how fast your code is with AppDynamics Lite. http://ad.doubleclick.net/clk;262219671;13503038;y? http://info.appdynamics.com/FreeJavaPerformanceDownload.html ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH RESEND 1/5] ARM: tegra: config: enable dmaengine based APB DMA driver
From: Laxman Dewangan ldewan...@nvidia.com Enable config for dmaengine based Tegra APB DMA driver and disable the legacy APB DMA driver (SYSTEM_DMA). Signed-off-by: Laxman Dewangan ldewan...@nvidia.com Signed-off-by: Stephen Warren swar...@nvidia.com --- I'm looking for Ack's on patches 4 and 5 from the SPI and ASoC maintainers respectively, so that I can take this series through the Tegra tree for 3.7. When this series was first posted, there was a bug in the Tegra ASoC PCM driver which prevented it from working. A fix for this has since been applied to ASoC's for-3.6 branch and hence should show up in 3.6. arch/arm/configs/tegra_defconfig |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index adcf3c2..2990396 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -29,6 +29,7 @@ CONFIG_ARCH_TEGRA_2x_SOC=y CONFIG_ARCH_TEGRA_3x_SOC=y CONFIG_TEGRA_PCI=y CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA=y +# CONFIG_TEGRA_SYSTEM_DMA is not set CONFIG_TEGRA_EMC_SCALING_ENABLE=y CONFIG_SMP=y CONFIG_PREEMPT=y @@ -175,6 +176,8 @@ CONFIG_RTC_DRV_MAX8907=y CONFIG_RTC_DRV_TPS65910=y CONFIG_RTC_DRV_EM3027=y CONFIG_RTC_DRV_TEGRA=y +CONFIG_DMADEVICES=y +CONFIG_TEGRA20_APB_DMA=y CONFIG_STAGING=y CONFIG_SENSORS_ISL29018=y CONFIG_SENSORS_ISL29028=y -- 1.7.0.4 -- Got visibility? Most devs has no idea what their production app looks like. Find out how fast your code is with AppDynamics Lite. http://ad.doubleclick.net/clk;262219671;13503038;y? http://info.appdynamics.com/FreeJavaPerformanceDownload.html ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH RESEND 3/5] ARM: tegra: apbio: remove support of legacy DMA driver based access
From: Laxman Dewangan ldewan...@nvidia.com
Remove the support code which uses the legacy APB DMA driver
for accessing the apbio register.
The driver will use the dmaengine based APB DMA driver for
accessing apbio register.
Signed-off-by: Laxman Dewangan ldewan...@nvidia.com
Signed-off-by: Stephen Warren swar...@nvidia.com
---
arch/arm/mach-tegra/apbio.c | 118 +--
1 files changed, 1 insertions(+), 117 deletions(-)
diff --git a/arch/arm/mach-tegra/apbio.c b/arch/arm/mach-tegra/apbio.c
index 643a378..b5015d0 100644
--- a/arch/arm/mach-tegra/apbio.c
+++ b/arch/arm/mach-tegra/apbio.c
@@ -28,7 +28,7 @@
#include apbio.h
-#if defined(CONFIG_TEGRA_SYSTEM_DMA) || defined(CONFIG_TEGRA20_APB_DMA)
+#if defined(CONFIG_TEGRA20_APB_DMA)
static DEFINE_MUTEX(tegra_apb_dma_lock);
static u32 *tegra_apb_bb;
static dma_addr_t tegra_apb_bb_phys;
@@ -37,121 +37,6 @@ static DECLARE_COMPLETION(tegra_apb_wait);
static u32 tegra_apb_readl_direct(unsigned long offset);
static void tegra_apb_writel_direct(u32 value, unsigned long offset);
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
-static struct tegra_dma_channel *tegra_apb_dma;
-
-bool tegra_apb_init(void)
-{
- struct tegra_dma_channel *ch;
-
- mutex_lock(tegra_apb_dma_lock);
-
- /* Check to see if we raced to setup */
- if (tegra_apb_dma)
- goto out;
-
- ch = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT |
- TEGRA_DMA_SHARED);
-
- if (!ch)
- goto out_fail;
-
- tegra_apb_bb = dma_alloc_coherent(NULL, sizeof(u32),
- tegra_apb_bb_phys, GFP_KERNEL);
- if (!tegra_apb_bb) {
- pr_err(%s: can not allocate bounce buffer\n, __func__);
- tegra_dma_free_channel(ch);
- goto out_fail;
- }
-
- tegra_apb_dma = ch;
-out:
- mutex_unlock(tegra_apb_dma_lock);
- return true;
-
-out_fail:
- mutex_unlock(tegra_apb_dma_lock);
- return false;
-}
-
-static void apb_dma_complete(struct tegra_dma_req *req)
-{
- complete(tegra_apb_wait);
-}
-
-static u32 tegra_apb_readl_using_dma(unsigned long offset)
-{
- struct tegra_dma_req req;
- int ret;
-
- if (!tegra_apb_dma !tegra_apb_init())
- return tegra_apb_readl_direct(offset);
-
- mutex_lock(tegra_apb_dma_lock);
- req.complete = apb_dma_complete;
- req.to_memory = 1;
- req.dest_addr = tegra_apb_bb_phys;
- req.dest_bus_width = 32;
- req.dest_wrap = 1;
- req.source_addr = offset;
- req.source_bus_width = 32;
- req.source_wrap = 4;
- req.req_sel = TEGRA_DMA_REQ_SEL_CNTR;
- req.size = 4;
-
- INIT_COMPLETION(tegra_apb_wait);
-
- tegra_dma_enqueue_req(tegra_apb_dma, req);
-
- ret = wait_for_completion_timeout(tegra_apb_wait,
- msecs_to_jiffies(50));
-
- if (WARN(ret == 0, apb read dma timed out)) {
- tegra_dma_dequeue_req(tegra_apb_dma, req);
- *(u32 *)tegra_apb_bb = 0;
- }
-
- mutex_unlock(tegra_apb_dma_lock);
- return *((u32 *)tegra_apb_bb);
-}
-
-static void tegra_apb_writel_using_dma(u32 value, unsigned long offset)
-{
- struct tegra_dma_req req;
- int ret;
-
- if (!tegra_apb_dma !tegra_apb_init()) {
- tegra_apb_writel_direct(value, offset);
- return;
- }
-
- mutex_lock(tegra_apb_dma_lock);
- *((u32 *)tegra_apb_bb) = value;
- req.complete = apb_dma_complete;
- req.to_memory = 0;
- req.dest_addr = offset;
- req.dest_wrap = 4;
- req.dest_bus_width = 32;
- req.source_addr = tegra_apb_bb_phys;
- req.source_bus_width = 32;
- req.source_wrap = 1;
- req.req_sel = TEGRA_DMA_REQ_SEL_CNTR;
- req.size = 4;
-
- INIT_COMPLETION(tegra_apb_wait);
-
- tegra_dma_enqueue_req(tegra_apb_dma, req);
-
- ret = wait_for_completion_timeout(tegra_apb_wait,
- msecs_to_jiffies(50));
-
- if (WARN(ret == 0, apb write dma timed out))
- tegra_dma_dequeue_req(tegra_apb_dma, req);
-
- mutex_unlock(tegra_apb_dma_lock);
-}
-
-#else
static struct dma_chan *tegra_apb_dma_chan;
static struct dma_slave_config dma_sconfig;
@@ -279,7 +164,6 @@ static void tegra_apb_writel_using_dma(u32 value, unsigned
long offset)
pr_err(error in writing offset 0x%08lx using dma\n, offset);
mutex_unlock(tegra_apb_dma_lock);
}
-#endif
#else
#define tegra_apb_readl_using_dma tegra_apb_readl_direct
#define tegra_apb_writel_using_dma tegra_apb_writel_direct
--
1.7.0.4
--
Got visibility?
Most devs has no idea what their production app looks like.
Find out how fast your code is with AppDynamics Lite.
http://ad.doubleclick.net/clk;262219671;13503038;y?
http://info.appdynamics.com/FreeJavaPerformanceDownload.html
[PATCH RESEND 4/5] spi: tegra: remove support of legacy DMA driver based access
From: Laxman Dewangan ldewan...@nvidia.com
Remove the support code which uses the legacy APB DMA driver
for accessing the SPI FIFO.
The driver will use the dmaengine based APB DMA driver for
accessing reqding/writing to SPI FIFO.
Signed-off-by: Laxman Dewangan ldewan...@nvidia.com
Signed-off-by: Stephen Warren swar...@nvidia.com
---
drivers/spi/Kconfig |2 +-
drivers/spi/spi-tegra.c | 55 +--
2 files changed, 2 insertions(+), 55 deletions(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 76631d0..323ea8f 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -387,7 +387,7 @@ config SPI_MXS
config SPI_TEGRA
tristate Nvidia Tegra SPI controller
- depends on ARCH_TEGRA (TEGRA_SYSTEM_DMA || TEGRA20_APB_DMA)
+ depends on ARCH_TEGRA TEGRA20_APB_DMA
help
SPI driver for NVidia Tegra SoCs
diff --git a/drivers/spi/spi-tegra.c b/drivers/spi/spi-tegra.c
index e28445d..f900506 100644
--- a/drivers/spi/spi-tegra.c
+++ b/drivers/spi/spi-tegra.c
@@ -164,23 +164,15 @@ struct spi_tegra_data {
* for the generic case.
*/
int dma_req_len;
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
- struct tegra_dma_reqrx_dma_req;
- struct tegra_dma_channel *rx_dma;
-#else
struct dma_chan *rx_dma;
struct dma_slave_config sconfig;
struct dma_async_tx_descriptor *rx_dma_desc;
dma_cookie_trx_cookie;
-#endif
u32 *rx_bb;
dma_addr_t rx_bb_phys;
};
-#if !defined(CONFIG_TEGRA_SYSTEM_DMA)
static void tegra_spi_rx_dma_complete(void *args);
-#endif
-
static inline unsigned long spi_tegra_readl(struct spi_tegra_data *tspi,
unsigned long reg)
{
@@ -204,10 +196,6 @@ static void spi_tegra_go(struct spi_tegra_data *tspi)
val = ~SLINK_DMA_BLOCK_SIZE(~0) ~SLINK_DMA_EN;
val |= SLINK_DMA_BLOCK_SIZE(tspi-dma_req_len / 4 - 1);
spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
- tspi-rx_dma_req.size = tspi-dma_req_len;
- tegra_dma_enqueue_req(tspi-rx_dma, tspi-rx_dma_req);
-#else
tspi-rx_dma_desc = dmaengine_prep_slave_single(tspi-rx_dma,
tspi-rx_bb_phys, tspi-dma_req_len,
DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
@@ -219,7 +207,6 @@ static void spi_tegra_go(struct spi_tegra_data *tspi)
tspi-rx_dma_desc-callback_param = tspi;
tspi-rx_cookie = dmaengine_submit(tspi-rx_dma_desc);
dma_async_issue_pending(tspi-rx_dma);
-#endif
val |= SLINK_DMA_EN;
spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
@@ -405,19 +392,12 @@ static void handle_spi_rx_dma_complete(struct
spi_tegra_data *tspi)
spin_unlock_irqrestore(tspi-lock, flags);
}
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
-static void tegra_spi_rx_dma_complete(struct tegra_dma_req *req)
-{
- struct spi_tegra_data *tspi = req-dev;
- handle_spi_rx_dma_complete(tspi);
-}
-#else
+
static void tegra_spi_rx_dma_complete(void *args)
{
struct spi_tegra_data *tspi = args;
handle_spi_rx_dma_complete(tspi);
}
-#endif
static int spi_tegra_setup(struct spi_device *spi)
{
@@ -509,9 +489,7 @@ static int __devinit spi_tegra_probe(struct platform_device
*pdev)
struct spi_tegra_data *tspi;
struct resource *r;
int ret;
-#if !defined(CONFIG_TEGRA_SYSTEM_DMA)
dma_cap_mask_t mask;
-#endif
master = spi_alloc_master(pdev-dev, sizeof *tspi);
if (master == NULL) {
@@ -563,14 +541,6 @@ static int __devinit spi_tegra_probe(struct
platform_device *pdev)
INIT_LIST_HEAD(tspi-queue);
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
- tspi-rx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT);
- if (!tspi-rx_dma) {
- dev_err(pdev-dev, can not allocate rx dma channel\n);
- ret = -ENODEV;
- goto err3;
- }
-#else
dma_cap_zero(mask);
dma_cap_set(DMA_SLAVE, mask);
tspi-rx_dma = dma_request_channel(mask, NULL, NULL);
@@ -580,8 +550,6 @@ static int __devinit spi_tegra_probe(struct platform_device
*pdev)
goto err3;
}
-#endif
-
tspi-rx_bb = dma_alloc_coherent(pdev-dev, sizeof(u32) * BB_LEN,
tspi-rx_bb_phys, GFP_KERNEL);
if (!tspi-rx_bb) {
@@ -590,17 +558,6 @@ static int __devinit spi_tegra_probe(struct
platform_device *pdev)
goto err4;
}
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
- tspi-rx_dma_req.complete = tegra_spi_rx_dma_complete;
- tspi-rx_dma_req.to_memory = 1;
- tspi-rx_dma_req.dest_addr = tspi-rx_bb_phys;
- tspi-rx_dma_req.dest_bus_width = 32;
- tspi-rx_dma_req.source_addr = tspi-phys + SLINK_RX_FIFO;
- tspi
[PATCH RESEND 2/5] ARM: tegra: dma: remove legacy APB DMA driver
From: Laxman Dewangan ldewan...@nvidia.com Remove the legacy APB dma driver. The APB DMA support is moved to dmaengine based Tegra APB DMA driver. All clients are also moved to dmaengine based APB DMA driver. Signed-off-by: Laxman Dewangan ldewan...@nvidia.com Signed-off-by: Stephen Warren swar...@nvidia.com --- arch/arm/mach-tegra/Kconfig|7 - arch/arm/mach-tegra/Makefile |1 - arch/arm/mach-tegra/dma.c | 822 arch/arm/mach-tegra/include/mach/dma.h | 97 4 files changed, 0 insertions(+), 927 deletions(-) delete mode 100644 arch/arm/mach-tegra/dma.c diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index b3226f8..5f3c03b 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -110,13 +110,6 @@ config TEGRA_DEBUG_UART_AUTO_SCRATCH endchoice -config TEGRA_SYSTEM_DMA - bool Enable system DMA driver for NVIDIA Tegra SoCs - default y - help - Adds system DMA functionality for NVIDIA Tegra SoCs, used by - several Tegra device drivers - config TEGRA_EMC_SCALING_ENABLE bool Enable scaling the memory frequency diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index a5cd6c1..9aa653b 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -20,7 +20,6 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-t30.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_SMP) += reset.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o -obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o obj-$(CONFIG_TEGRA_PCI)+= pcie.o diff --git a/arch/arm/mach-tegra/dma.c b/arch/arm/mach-tegra/dma.c deleted file mode 100644 index 7f27320..000 --- a/arch/arm/mach-tegra/dma.c +++ /dev/null @@ -1,822 +0,0 @@ -/* - * arch/arm/mach-tegra/dma.c - * - * System DMA driver for NVIDIA Tegra SoCs - * - * Copyright (c) 2008-2009, NVIDIA Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#include linux/io.h -#include linux/interrupt.h -#include linux/module.h -#include linux/spinlock.h -#include linux/err.h -#include linux/irq.h -#include linux/delay.h -#include linux/clk.h -#include mach/dma.h -#include mach/irqs.h -#include mach/iomap.h - -#include apbio.h - -#define APB_DMA_GEN0x000 -#define GEN_ENABLE (131) - -#define APB_DMA_CNTRL 0x010 - -#define APB_DMA_IRQ_MASK 0x01c - -#define APB_DMA_IRQ_MASK_SET 0x020 - -#define APB_DMA_CHAN_CSR 0x000 -#define CSR_ENB(131) -#define CSR_IE_EOC (130) -#define CSR_HOLD (129) -#define CSR_DIR(128) -#define CSR_ONCE (127) -#define CSR_FLOW (121) -#define CSR_REQ_SEL_SHIFT 16 -#define CSR_WCOUNT_SHIFT 2 -#define CSR_WCOUNT_MASK0xFFFC - -#define APB_DMA_CHAN_STA 0x004 -#define STA_BUSY (131) -#define STA_ISE_EOC(130) -#define STA_HALT (129) -#define STA_PING_PONG (128) -#define STA_COUNT_SHIFT2 -#define STA_COUNT_MASK 0xFFFC - -#define APB_DMA_CHAN_AHB_PTR 0x010 - -#define APB_DMA_CHAN_AHB_SEQ 0x014 -#define AHB_SEQ_INTR_ENB (131) -#define AHB_SEQ_BUS_WIDTH_SHIFT28 -#define AHB_SEQ_BUS_WIDTH_MASK (0x7AHB_SEQ_BUS_WIDTH_SHIFT) -#define AHB_SEQ_BUS_WIDTH_8(0AHB_SEQ_BUS_WIDTH_SHIFT) -#define AHB_SEQ_BUS_WIDTH_16 (1AHB_SEQ_BUS_WIDTH_SHIFT) -#define AHB_SEQ_BUS_WIDTH_32 (2AHB_SEQ_BUS_WIDTH_SHIFT) -#define AHB_SEQ_BUS_WIDTH_64 (3AHB_SEQ_BUS_WIDTH_SHIFT) -#define AHB_SEQ_BUS_WIDTH_128
[PATCH RESEND 5/5] ASoC: tegra: remove support of legacy DMA driver based access
From: Laxman Dewangan ldewan...@nvidia.com
Remove the support code which uses the legacy APB DMA driver
for accessing the I2S FIFO.
The driver will use the dmaengine based APB DMA driver for
accessing reqding/writing to I2S FIFO.
Signed-off-by: Laxman Dewangan ldewan...@nvidia.com
Signed-off-by: Stephen Warren swar...@nvidia.com
---
sound/soc/tegra/Kconfig |2 +-
sound/soc/tegra/tegra_pcm.c | 232 ---
sound/soc/tegra/tegra_pcm.h | 14 ---
3 files changed, 1 insertions(+), 247 deletions(-)
diff --git a/sound/soc/tegra/Kconfig b/sound/soc/tegra/Kconfig
index 02bcd30..19e5fe7 100644
--- a/sound/soc/tegra/Kconfig
+++ b/sound/soc/tegra/Kconfig
@@ -1,6 +1,6 @@
config SND_SOC_TEGRA
tristate SoC Audio for the Tegra System-on-Chip
- depends on ARCH_TEGRA (TEGRA_SYSTEM_DMA || TEGRA20_APB_DMA)
+ depends on ARCH_TEGRA TEGRA20_APB_DMA
select REGMAP_MMIO
select SND_SOC_DMAENGINE_PCM if TEGRA20_APB_DMA
help
diff --git a/sound/soc/tegra/tegra_pcm.c b/sound/soc/tegra/tegra_pcm.c
index 8d6900c..e187339 100644
--- a/sound/soc/tegra/tegra_pcm.c
+++ b/sound/soc/tegra/tegra_pcm.c
@@ -57,237 +57,6 @@ static const struct snd_pcm_hardware tegra_pcm_hardware = {
.fifo_size = 4,
};
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
-static void tegra_pcm_queue_dma(struct tegra_runtime_data *prtd)
-{
- struct snd_pcm_substream *substream = prtd-substream;
- struct snd_dma_buffer *buf = substream-dma_buffer;
- struct tegra_dma_req *dma_req;
- unsigned long addr;
-
- dma_req = prtd-dma_req[prtd-dma_req_idx];
- prtd-dma_req_idx = 1 - prtd-dma_req_idx;
-
- addr = buf-addr + prtd-dma_pos;
- prtd-dma_pos += dma_req-size;
- if (prtd-dma_pos = prtd-dma_pos_end)
- prtd-dma_pos = 0;
-
- if (substream-stream == SNDRV_PCM_STREAM_PLAYBACK)
- dma_req-source_addr = addr;
- else
- dma_req-dest_addr = addr;
-
- tegra_dma_enqueue_req(prtd-dma_chan, dma_req);
-}
-
-static void dma_complete_callback(struct tegra_dma_req *req)
-{
- struct tegra_runtime_data *prtd = (struct tegra_runtime_data *)req-dev;
- struct snd_pcm_substream *substream = prtd-substream;
- struct snd_pcm_runtime *runtime = substream-runtime;
-
- spin_lock(prtd-lock);
-
- if (!prtd-running) {
- spin_unlock(prtd-lock);
- return;
- }
-
- if (++prtd-period_index = runtime-periods)
- prtd-period_index = 0;
-
- tegra_pcm_queue_dma(prtd);
-
- spin_unlock(prtd-lock);
-
- snd_pcm_period_elapsed(substream);
-}
-
-static void setup_dma_tx_request(struct tegra_dma_req *req,
- struct tegra_pcm_dma_params * dmap)
-{
- req-complete = dma_complete_callback;
- req-to_memory = false;
- req-dest_addr = dmap-addr;
- req-dest_wrap = dmap-wrap;
- req-source_bus_width = 32;
- req-source_wrap = 0;
- req-dest_bus_width = dmap-width;
- req-req_sel = dmap-req_sel;
-}
-
-static void setup_dma_rx_request(struct tegra_dma_req *req,
- struct tegra_pcm_dma_params * dmap)
-{
- req-complete = dma_complete_callback;
- req-to_memory = true;
- req-source_addr = dmap-addr;
- req-dest_wrap = 0;
- req-source_bus_width = dmap-width;
- req-source_wrap = dmap-wrap;
- req-dest_bus_width = 32;
- req-req_sel = dmap-req_sel;
-}
-
-static int tegra_pcm_open(struct snd_pcm_substream *substream)
-{
- struct snd_pcm_runtime *runtime = substream-runtime;
- struct tegra_runtime_data *prtd;
- struct snd_soc_pcm_runtime *rtd = substream-private_data;
- struct tegra_pcm_dma_params * dmap;
- int ret = 0;
-
- prtd = kzalloc(sizeof(struct tegra_runtime_data), GFP_KERNEL);
- if (prtd == NULL)
- return -ENOMEM;
-
- runtime-private_data = prtd;
- prtd-substream = substream;
-
- spin_lock_init(prtd-lock);
-
- if (substream-stream == SNDRV_PCM_STREAM_PLAYBACK) {
- dmap = snd_soc_dai_get_dma_data(rtd-cpu_dai, substream);
- setup_dma_tx_request(prtd-dma_req[0], dmap);
- setup_dma_tx_request(prtd-dma_req[1], dmap);
- } else {
- dmap = snd_soc_dai_get_dma_data(rtd-cpu_dai, substream);
- setup_dma_rx_request(prtd-dma_req[0], dmap);
- setup_dma_rx_request(prtd-dma_req[1], dmap);
- }
-
- prtd-dma_req[0].dev = prtd;
- prtd-dma_req[1].dev = prtd;
-
- prtd-dma_chan = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT);
- if (prtd-dma_chan == NULL) {
- ret = -ENOMEM;
- goto err;
- }
-
- /* Set HW params now that initialization is complete */
- snd_soc_set_runtime_hwparams(substream, tegra_pcm_hardware);
-
- /* Ensure
Re: [PATCH 0/5] ARM: tegra: move all APB DMA client to dmaengine based driver
On 08/16/2012 08:13 AM, Laxman Dewangan wrote: This patch series enable the dmaengine based Tegra APB DMA driver and remove the support code for the legacy dma driver from different APB DMA clients. Patch 1 enable the dmaengine based dma drie and disable the legacy dma driver in config file. Patch 2 remove the legacy dma driver. Patch 3,4, 5 remove the support code from different APB DMA clients to support legacy dma driver. Please note that this series will depends on patch dma: tegra: enable/disable dma clock which is not in 3.6-rc1 but will be available in next RC (rc2) of 3.6 as part of fixes. I have applied this series to Tegra's for-3.7/dmaengine branch. Right now, that branch is based directly on Mark Brown's ASoC for-3.6 branch in order to pick up the fix it depends on. However, I'll rebase on the 3.6 pull request tag he sends for that branch as soon as it's available. -- Everyone hates slow websites. So do we. Make your web apps faster with AppDynamics Download AppDynamics Lite for free today: http://ad.doubleclick.net/clk;258768047;13503038;j? http://info.appdynamics.com/FreeJavaPerformanceDownload.html ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH 4/5] spi: tegra: remove support of legacy DMA driver based access
On 08/16/2012 08:13 AM, Laxman Dewangan wrote: Remove the support code which uses the legacy APB DMA driver for accessing the SPI FIFO. The driver will use the dmaengine based APB DMA driver for accessing reqding/writing to SPI FIFO. Signed-off-by: Laxman Dewangan ldewan...@nvidia.com Please note that I've applied this to Tegra's for-3.7/dmaengine branch, even though it hasn't been ack'd by an SPI maintainer. -- Everyone hates slow websites. So do we. Make your web apps faster with AppDynamics Download AppDynamics Lite for free today: http://ad.doubleclick.net/clk;258768047;13503038;j? http://info.appdynamics.com/FreeJavaPerformanceDownload.html ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH 5/5] ASoC: tegra: remove support of legacy DMA driver based access
On 08/16/2012 08:13 AM, Laxman Dewangan wrote: Remove the support code which uses the legacy APB DMA driver for accessing the I2S FIFO. The driver will use the dmaengine based APB DMA driver for accessing reqding/writing to I2S FIFO. Signed-off-by: Laxman Dewangan ldewan...@nvidia.com Please note that I've applied this to Tegra's for-3.7/dmaengine branch, even though it hasn't been ack'd by an ASoC maintainer. -- Everyone hates slow websites. So do we. Make your web apps faster with AppDynamics Download AppDynamics Lite for free today: http://ad.doubleclick.net/clk;258768047;13503038;j? http://info.appdynamics.com/FreeJavaPerformanceDownload.html ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH 4/5] spi: tegra: remove support of legacy DMA driver based access
On 08/16/2012 08:13 AM, Laxman Dewangan wrote: Remove the support code which uses the legacy APB DMA driver for accessing the SPI FIFO. The driver will use the dmaengine based APB DMA driver for accessing reqding/writing to SPI FIFO. Signed-off-by: Laxman Dewangan ldewan...@nvidia.com Grant, Mark, I'd like to take this patch through the Tegra tree, since it relies on the previous Tegra patches to convert to dmaengine. Could I please get an ack if that's OK? Thanks. -- Live Security Virtual Conference Exclusive live event will cover all the ways today's security and threat landscape has changed and how IT managers can respond. Discussions will include endpoint security, mobile security and the latest in malware threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/ ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH 5/5] ASoC: tegra: remove support of legacy DMA driver based access
On 08/16/2012 08:13 AM, Laxman Dewangan wrote: Remove the support code which uses the legacy APB DMA driver for accessing the I2S FIFO. The driver will use the dmaengine based APB DMA driver for accessing reqding/writing to I2S FIFO. Signed-off-by: Laxman Dewangan ldewan...@nvidia.com Mark, Liam, I'd like to take this patch through the Tegra tree, since it relies on the previous Tegra patches to convert to dmaengine. Could I please get an ack if that's OK? Thanks. -- Live Security Virtual Conference Exclusive live event will cover all the ways today's security and threat landscape has changed and how IT managers can respond. Discussions will include endpoint security, mobile security and the latest in malware threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/ ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH 1/5] ARM: tegra: config: enable dmaengine based APB DMA driver
On 08/17/2012 12:38 AM, Laxman Dewangan wrote: On Thursday 16 August 2012 11:23 PM, Stephen Warren wrote: On 08/16/2012 08:13 AM, Laxman Dewangan wrote: Enable config for dmaengine based Tegra APB DMA driver and disable the legacy APB DMA driver (SYSTEM_DMA). Laxman, if I apply this series to next-20120816 (plus a few patches in my local work branch plus the CPU hotplug patches from Joseph, although I suspect none of that matters), then audio playback on Tegra20 is broken; the pitch is far too high. Audio playback on Tegra30 works as expected. I run the test again on ventana and did not see any issue. I play one song and saw similar behavior with/without this series. OK, I'll test some other boards. I tested Whistler, although all the clocking logic is identical between all Tegra20 boards. With this series: ubuntu@tegra-ubuntu:/home$ aplay 1-04 Hungry Like The Wolf.wav Playing WAVE '1-04 Hungry Like The Wolf.wav' : Signed 16 bit Little Endian, Rate 44100 Hz, Stereo underrun!!! (at least 5039.388 ms long) Why are you getting all these underruns? I almost never see this, except when something else is hammering the SD card containing the .wav file. If I saw those, I'd count it as a test failure. -- Live Security Virtual Conference Exclusive live event will cover all the ways today's security and threat landscape has changed and how IT managers can respond. Discussions will include endpoint security, mobile security and the latest in malware threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/ ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH 1/5] ARM: tegra: config: enable dmaengine based APB DMA driver
On 08/17/2012 09:17 AM, Stephen Warren wrote: On 08/17/2012 12:38 AM, Laxman Dewangan wrote: On Thursday 16 August 2012 11:23 PM, Stephen Warren wrote: On 08/16/2012 08:13 AM, Laxman Dewangan wrote: Enable config for dmaengine based Tegra APB DMA driver and disable the legacy APB DMA driver (SYSTEM_DMA). Laxman, if I apply this series to next-20120816 (plus a few patches in my local work branch plus the CPU hotplug patches from Joseph, although I suspect none of that matters), then audio playback on Tegra20 is broken; the pitch is far too high. Audio playback on Tegra30 works as expected. I run the test again on ventana and did not see any issue. I play one song and saw similar behavior with/without this series. OK, I'll test some other boards. I tested Whistler, although all the clocking logic is identical between all Tegra20 boards. I tested both 3.6-rc2 and next-20120816, and they both work fine on Ventana. I then applied this patch series to both (plus your dma: tegra: enable/disable dma clock for 3.6-rc2) and it causes (or at least exposes) the problem. All testing was with a full git clean, using tegra_defconfig, and with no other patches applied. If you're not seeing this problem, are you sure you're executing the kernel you think you are, and that it got correctly switched to the new dmaengine driver, and rebuilt after applying your patches? -- Live Security Virtual Conference Exclusive live event will cover all the ways today's security and threat landscape has changed and how IT managers can respond. Discussions will include endpoint security, mobile security and the latest in malware threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/ ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH 1/5] ARM: tegra: config: enable dmaengine based APB DMA driver
On 08/16/2012 08:13 AM, Laxman Dewangan wrote: Enable config for dmaengine based Tegra APB DMA driver and disable the legacy APB DMA driver (SYSTEM_DMA). Laxman, if I apply this series to next-20120816 (plus a few patches in my local work branch plus the CPU hotplug patches from Joseph, although I suspect none of that matters), then audio playback on Tegra20 is broken; the pitch is far too high. Audio playback on Tegra30 works as expected. -- Live Security Virtual Conference Exclusive live event will cover all the ways today's security and threat landscape has changed and how IT managers can respond. Discussions will include endpoint security, mobile security and the latest in malware threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/ ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH] spi: tegra: use dmaengine based dma driver
On 06/29/2012 05:31 AM, Laxman Dewangan wrote: Use the dmaengine based Tegra APB DMA driver for data transfer between SPI FIFO and memory in place of legacy Tegra APB DMA. The new driver is selected if legacy driver is not selected and new DMA driver is enabled through config file. Signed-off-by: Laxman Dewangan ldewan...@nvidia.com Acked-by: Stephen Warren swar...@wwwdotorg.org -- Live Security Virtual Conference Exclusive live event will cover all the ways today's security and threat landscape has changed and how IT managers can respond. Discussions will include endpoint security, mobile security and the latest in malware threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/ ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
RE: [PATCH V3 1/5] i2c: Add irq_gpio field to struct i2c_client, i2c_board_info.
Greg KH wrote at Tuesday, September 06, 2011 4:57 PM: On Fri, Sep 02, 2011 at 11:24:04AM -0700, Stephen Warren wrote: Jean Delvare wrote at Friday, September 02, 2011 3:25 AM: ... Why not make it platform data for now and 'if' it becomes way more common (probably won't) we can always propose adding as a general field at a later date. Yes, this sounds like a much more reasonable approach. BTW, if that's the direction that's decided, just take the first version of the patchset I posted, plus Jonathan Cameron's subsequent patch to modify ak8975 to accept GPIO ID through platform data. I don't know which patchset that would be, can you please just resend what you want applied so that I know I get the correct one? Sorry for the slow response; I was on vacation for the last couple weeks. I've now posted an updated version of this patchset, without any of the changes for I2C/SPI core/types/... -- nvpublic -- All the data continuously generated in your IT infrastructure contains a definitive record of customers, application performance, security threats, fraudulent activity and more. Splunk takes this data and makes sense of it. Business sense. IT sense. Common sense. http://p.sf.net/sfu/splunk-d2dcopy1 ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
RE: [PATCH V3 1/5] i2c: Add irq_gpio field to struct i2c_client, i2c_board_info.
Jean Delvare wrote at Friday, September 02, 2011 3:25 AM: Hi Jonathan, On Fri, 02 Sep 2011 10:19:24 +0100, Jonathan Cameron wrote: On 09/02/11 07:56, Jean Delvare wrote: Stephen, Can you please fix your e-mail client / system / whatever so that your patch series are no longer sent duplicated? On Thu, 1 Sep 2011 16:04:27 -0600, Stephen Warren wrote: Some devices use a single pin as both an IRQ and a GPIO. In that case, irq_gpio is the GPIO ID for that pin. Not all drivers use this feature. Where they do, and the use of this feature is optional, and the system wishes to disable this feature, this field must be explicitly set to a defined invalid GPIO ID, such as -1. Signed-off-by: Stephen Warren swar...@nvidia.com --- v3: Also add the field to i2c_board_info, and copy the field from i2c_board_info to i2c_client upon instantiation I don't get the idea. The i2c core doesn't make any use of the field, and that field will only be used by a few drivers amongst the 420+ i2c drivers in the tree. This looks like a waste of memory. What's wrong with including the new field in the private platform or arch data structure for drivers which need it? Why not make it platform data for now and 'if' it becomes way more common (probably won't) we can always propose adding as a general field at a later date. Yes, this sounds like a much more reasonable approach. BTW, if that's the direction that's decided, just take the first version of the patchset I posted, plus Jonathan Cameron's subsequent patch to modify ak8975 to accept GPIO ID through platform data. -- nvpublic -- Special Offer -- Download ArcSight Logger for FREE! Finally, a world-class log management solution at an even better price-free! And you'll get a free Love Thy Logs t-shirt when you download Logger. Secure your free ArcSight Logger TODAY! http://p.sf.net/sfu/arcsisghtdev2dev ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH V3 3/5] staging:iio:magnetometer:ak8975 Don't use irq_to_gpio()
Tegra doesn't have irq_to_gpio() any more, and ak8975 is included in tegra_defconfig. This causes a build failure. Instead, obtain the GPIO ID corresponding to the chip's IRQ from the new i2c_client field irq_gpio. Signed-off-by: Stephen Warren swar...@nvidia.com --- drivers/staging/iio/magnetometer/ak8975.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/staging/iio/magnetometer/ak8975.c b/drivers/staging/iio/magnetometer/ak8975.c index a17fa9f..14076da 100644 --- a/drivers/staging/iio/magnetometer/ak8975.c +++ b/drivers/staging/iio/magnetometer/ak8975.c @@ -477,7 +477,7 @@ static int ak8975_probe(struct i2c_client *client, int err; /* Grab and set up the supplied GPIO. */ - eoc_gpio = irq_to_gpio(client-irq); + eoc_gpio = client-irq_gpio; /* We may not have a GPIO based IRQ to scan, that is fine, we will poll if so */ -- 1.7.0.4 -- Special Offer -- Download ArcSight Logger for FREE! Finally, a world-class log management solution at an even better price-free! And you'll get a free Love Thy Logs t-shirt when you download Logger. Secure your free ArcSight Logger TODAY! http://p.sf.net/sfu/arcsisghtdev2dev ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH V3 4/5] staging:iio:magnetometer:ak8975: Don't assume 0 is an invalid GPIO
gpio_is_valid() is the defined mechanism to determine whether a GPIO is
valid. Use this instead of assuming that 0 is an invalid GPIO.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
drivers/staging/iio/magnetometer/ak8975.c | 11 +--
1 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/staging/iio/magnetometer/ak8975.c
b/drivers/staging/iio/magnetometer/ak8975.c
index 14076da..0dfdf50 100644
--- a/drivers/staging/iio/magnetometer/ak8975.c
+++ b/drivers/staging/iio/magnetometer/ak8975.c
@@ -373,7 +373,7 @@ static int ak8975_read_axis(struct iio_dev *indio_dev, int
index, int *val)
}
/* Wait for the conversion to complete. */
- if (data-eoc_gpio)
+ if (gpio_is_valid(data-eoc_gpio))
ret = wait_conversion_complete_gpio(data);
else
ret = wait_conversion_complete_polled(data);
@@ -481,7 +481,7 @@ static int ak8975_probe(struct i2c_client *client,
/* We may not have a GPIO based IRQ to scan, that is fine, we will
poll if so */
- if (eoc_gpio 0) {
+ if (gpio_is_valid(eoc_gpio)) {
err = gpio_request(eoc_gpio, ak_8975);
if (err 0) {
dev_err(client-dev,
@@ -497,8 +497,7 @@ static int ak8975_probe(struct i2c_client *client,
eoc_gpio, err);
goto exit_gpio;
}
- } else
- eoc_gpio = 0; /* No GPIO available */
+ }
/* Register with IIO */
indio_dev = iio_allocate_device(sizeof(*data));
@@ -534,7 +533,7 @@ static int ak8975_probe(struct i2c_client *client,
exit_free_iio:
iio_free_device(indio_dev);
exit_gpio:
- if (eoc_gpio)
+ if (gpio_is_valid(eoc_gpio))
gpio_free(eoc_gpio);
exit:
return err;
@@ -549,7 +548,7 @@ static int ak8975_remove(struct i2c_client *client)
iio_device_unregister(indio_dev);
iio_free_device(indio_dev);
- if (eoc_gpio)
+ if (gpio_is_valid(eoc_gpio))
gpio_free(eoc_gpio);
return 0;
--
1.7.0.4
--
Special Offer -- Download ArcSight Logger for FREE!
Finally, a world-class log management solution at an even better
price-free! And you'll get a free Love Thy Logs t-shirt when you
download Logger. Secure your free ArcSight Logger TODAY!
http://p.sf.net/sfu/arcsisghtdev2dev
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH V3 1/5] i2c: Add irq_gpio field to struct i2c_client, i2c_board_info.
Some devices use a single pin as both an IRQ and a GPIO. In that case,
irq_gpio is the GPIO ID for that pin. Not all drivers use this feature.
Where they do, and the use of this feature is optional, and the system
wishes to disable this feature, this field must be explicitly set to a
defined invalid GPIO ID, such as -1.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
v3: Also add the field to i2c_board_info, and copy the field from
i2c_board_info to i2c_client upon instantiation
drivers/i2c/i2c-core.c |1 +
include/linux/i2c.h|9 +
2 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/drivers/i2c/i2c-core.c b/drivers/i2c/i2c-core.c
index 131079a..da12540 100644
--- a/drivers/i2c/i2c-core.c
+++ b/drivers/i2c/i2c-core.c
@@ -518,6 +518,7 @@ i2c_new_device(struct i2c_adapter *adap, struct
i2c_board_info const *info)
client-flags = info-flags;
client-addr = info-addr;
client-irq = info-irq;
+ client-irq_gpio = info-irq_gpio;
strlcpy(client-name, info-type, sizeof(client-name));
diff --git a/include/linux/i2c.h b/include/linux/i2c.h
index 3fad485..49e2e36 100644
--- a/include/linux/i2c.h
+++ b/include/linux/i2c.h
@@ -192,6 +192,12 @@ struct i2c_driver {
* @driver: device's driver, hence pointer to access routines
* @dev: Driver model device node for the slave.
* @irq: indicates the IRQ generated by this device (if any)
+ * @irq_gpio: some devices use a single pin as both an IRQ and a GPIO. In
+ * that case, irq_gpio is the GPIO ID for that pin. Not all drivers
+ * use this feature. Where they do, and the use of this feature is
+ * optional, and the system wishes to disable this feature, this
+ * field must be explicitly set to a defined invalid GPIO ID, such
+ * as -1.
* @detected: member of an i2c_driver.clients list or i2c-core's
* userspace_devices list
*
@@ -209,6 +215,7 @@ struct i2c_client {
struct i2c_driver *driver; /* and our access routines */
struct device dev; /* the device structure */
int irq;/* irq issued by device */
+ int irq_gpio; /* gpio corresponding to irq*/
struct list_head detected;
};
#define to_i2c_client(d) container_of(d, struct i2c_client, dev)
@@ -240,6 +247,7 @@ static inline void i2c_set_clientdata(struct i2c_client
*dev, void *data)
* @archdata: copied into i2c_client.dev.archdata
* @of_node: pointer to OpenFirmware device node
* @irq: stored in i2c_client.irq
+ * @irq_gpio: stored in i2c_client.irq_gpio
*
* I2C doesn't actually support hardware probing, although controllers and
* devices may be able to use I2C_SMBUS_QUICK to tell whether or not there's
@@ -260,6 +268,7 @@ struct i2c_board_info {
struct dev_archdata *archdata;
struct device_node *of_node;
int irq;
+ int irq_gpio;
};
/**
--
1.7.0.4
--
Special Offer -- Download ArcSight Logger for FREE!
Finally, a world-class log management solution at an even better
price-free! And you'll get a free Love Thy Logs t-shirt when you
download Logger. Secure your free ArcSight Logger TODAY!
http://p.sf.net/sfu/arcsisghtdev2dev
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH V3 5/5] staging:iio:magnetometer:ak8975: Fix probe() error-handling
Fix ak8975_probe() to jump to the appropriate exit labels when an error
occurs. With the previous code, some cleanup actions were being skipped
for some error conditions.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
drivers/staging/iio/magnetometer/ak8975.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/staging/iio/magnetometer/ak8975.c
b/drivers/staging/iio/magnetometer/ak8975.c
index 0dfdf50..cc20e8d 100644
--- a/drivers/staging/iio/magnetometer/ak8975.c
+++ b/drivers/staging/iio/magnetometer/ak8975.c
@@ -510,7 +510,7 @@ static int ak8975_probe(struct i2c_client *client,
err = ak8975_setup(client);
if (err 0) {
dev_err(client-dev, AK8975 initialization fails\n);
- goto exit_gpio;
+ goto exit_free_iio;
}
i2c_set_clientdata(client, indio_dev);
--
1.7.0.4
--
Special Offer -- Download ArcSight Logger for FREE!
Finally, a world-class log management solution at an even better
price-free! And you'll get a free Love Thy Logs t-shirt when you
download Logger. Secure your free ArcSight Logger TODAY!
http://p.sf.net/sfu/arcsisghtdev2dev
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH V3 2/5] spi: Add irq_gpio field to struct spi_device, spi_board_info.
Some devices use a single pin as both an IRQ and a GPIO. In that case,
irq_gpio is the GPIO ID for that pin. Not all drivers use this feature.
Where they do, and the use of this feature is optional, and the system
wishes to disable this feature, this field must be explicitly set to a
defined invalid GPIO ID, such as -1.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
v3: New patch for v3; apply the same change to spi as for i2c per Mark
Brown.
drivers/spi/spi.c |1 +
include/linux/spi/spi.h | 10 ++
2 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 77eae99..9932572 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -433,6 +433,7 @@ struct spi_device *spi_new_device(struct spi_master *master,
proxy-max_speed_hz = chip-max_speed_hz;
proxy-mode = chip-mode;
proxy-irq = chip-irq;
+ proxy-irq_gpio = chip-irq_gpio;
strlcpy(proxy-modalias, chip-modalias, sizeof(proxy-modalias));
proxy-dev.platform_data = (void *) chip-platform_data;
proxy-controller_data = chip-controller_data;
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index bb4f5fb..086b591 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -50,6 +50,12 @@ extern struct bus_type spi_bus_type;
* The spi_transfer.bits_per_word can override this for each transfer.
* @irq: Negative, or the number passed to request_irq() to receive
* interrupts from this device.
+ * @irq_gpio: some devices use a single pin as both an IRQ and a GPIO. In
+ * that case, irq_gpio is the GPIO ID for that pin. Not all drivers
+ * use this feature. Where they do, and the use of this feature is
+ * optional, and the system wishes to disable this feature, this
+ * field must be explicitly set to a defined invalid GPIO ID, such
+ * as -1.
* @controller_state: Controller's runtime state
* @controller_data: Board-specific definitions for controller, such as
* FIFO initialization parameters; from board_info.controller_data
@@ -86,6 +92,7 @@ struct spi_device {
#defineSPI_READY 0x80/* slave pulls low to
pause */
u8 bits_per_word;
int irq;
+ int irq_gpio;
void*controller_state;
void*controller_data;
charmodalias[SPI_NAME_SIZE];
@@ -692,6 +699,8 @@ static inline ssize_t spi_w8r16(struct spi_device *spi, u8
cmd)
* @controller_data: Initializes spi_device.controller_data; some
* controllers need hints about hardware setup, e.g. for DMA.
* @irq: Initializes spi_device.irq; depends on how the board is wired.
+ * @irq_gpio: Initializes spi_device.irq_gpio; depends on how the board
+ * is wired.
* @max_speed_hz: Initializes spi_device.max_speed_hz; based on limits
* from the chip datasheet and board-specific signal quality issues.
* @bus_num: Identifies which spi_master parents the spi_device; unused
@@ -727,6 +736,7 @@ struct spi_board_info {
const void *platform_data;
void*controller_data;
int irq;
+ int irq_gpio;
/* slower signaling on noisy or low voltage boards */
u32 max_speed_hz;
--
1.7.0.4
--
Special Offer -- Download ArcSight Logger for FREE!
Finally, a world-class log management solution at an even better
price-free! And you'll get a free Love Thy Logs t-shirt when you
download Logger. Secure your free ArcSight Logger TODAY!
http://p.sf.net/sfu/arcsisghtdev2dev
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH V3 2/5] spi: Add irq_gpio field to struct spi_device, spi_board_info.
Some devices use a single pin as both an IRQ and a GPIO. In that case,
irq_gpio is the GPIO ID for that pin. Not all drivers use this feature.
Where they do, and the use of this feature is optional, and the system
wishes to disable this feature, this field must be explicitly set to a
defined invalid GPIO ID, such as -1.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
v3: New patch for v3; apply the same change to spi as for i2c per Mark
Brown.
drivers/spi/spi.c |1 +
include/linux/spi/spi.h | 10 ++
2 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 77eae99..9932572 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -433,6 +433,7 @@ struct spi_device *spi_new_device(struct spi_master *master,
proxy-max_speed_hz = chip-max_speed_hz;
proxy-mode = chip-mode;
proxy-irq = chip-irq;
+ proxy-irq_gpio = chip-irq_gpio;
strlcpy(proxy-modalias, chip-modalias, sizeof(proxy-modalias));
proxy-dev.platform_data = (void *) chip-platform_data;
proxy-controller_data = chip-controller_data;
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index bb4f5fb..086b591 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -50,6 +50,12 @@ extern struct bus_type spi_bus_type;
* The spi_transfer.bits_per_word can override this for each transfer.
* @irq: Negative, or the number passed to request_irq() to receive
* interrupts from this device.
+ * @irq_gpio: some devices use a single pin as both an IRQ and a GPIO. In
+ * that case, irq_gpio is the GPIO ID for that pin. Not all drivers
+ * use this feature. Where they do, and the use of this feature is
+ * optional, and the system wishes to disable this feature, this
+ * field must be explicitly set to a defined invalid GPIO ID, such
+ * as -1.
* @controller_state: Controller's runtime state
* @controller_data: Board-specific definitions for controller, such as
* FIFO initialization parameters; from board_info.controller_data
@@ -86,6 +92,7 @@ struct spi_device {
#defineSPI_READY 0x80/* slave pulls low to
pause */
u8 bits_per_word;
int irq;
+ int irq_gpio;
void*controller_state;
void*controller_data;
charmodalias[SPI_NAME_SIZE];
@@ -692,6 +699,8 @@ static inline ssize_t spi_w8r16(struct spi_device *spi, u8
cmd)
* @controller_data: Initializes spi_device.controller_data; some
* controllers need hints about hardware setup, e.g. for DMA.
* @irq: Initializes spi_device.irq; depends on how the board is wired.
+ * @irq_gpio: Initializes spi_device.irq_gpio; depends on how the board
+ * is wired.
* @max_speed_hz: Initializes spi_device.max_speed_hz; based on limits
* from the chip datasheet and board-specific signal quality issues.
* @bus_num: Identifies which spi_master parents the spi_device; unused
@@ -727,6 +736,7 @@ struct spi_board_info {
const void *platform_data;
void*controller_data;
int irq;
+ int irq_gpio;
/* slower signaling on noisy or low voltage boards */
u32 max_speed_hz;
--
1.7.0.4
--
Special Offer -- Download ArcSight Logger for FREE!
Finally, a world-class log management solution at an even better
price-free! And you'll get a free Love Thy Logs t-shirt when you
download Logger. Secure your free ArcSight Logger TODAY!
http://p.sf.net/sfu/arcsisghtdev2dev
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH V3 3/5] staging:iio:magnetometer:ak8975 Don't use irq_to_gpio()
Tegra doesn't have irq_to_gpio() any more, and ak8975 is included in tegra_defconfig. This causes a build failure. Instead, obtain the GPIO ID corresponding to the chip's IRQ from the new i2c_client field irq_gpio. Signed-off-by: Stephen Warren swar...@nvidia.com --- drivers/staging/iio/magnetometer/ak8975.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/staging/iio/magnetometer/ak8975.c b/drivers/staging/iio/magnetometer/ak8975.c index a17fa9f..14076da 100644 --- a/drivers/staging/iio/magnetometer/ak8975.c +++ b/drivers/staging/iio/magnetometer/ak8975.c @@ -477,7 +477,7 @@ static int ak8975_probe(struct i2c_client *client, int err; /* Grab and set up the supplied GPIO. */ - eoc_gpio = irq_to_gpio(client-irq); + eoc_gpio = client-irq_gpio; /* We may not have a GPIO based IRQ to scan, that is fine, we will poll if so */ -- 1.7.0.4 -- Special Offer -- Download ArcSight Logger for FREE! Finally, a world-class log management solution at an even better price-free! And you'll get a free Love Thy Logs t-shirt when you download Logger. Secure your free ArcSight Logger TODAY! http://p.sf.net/sfu/arcsisghtdev2dev ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH V3 1/5] i2c: Add irq_gpio field to struct i2c_client, i2c_board_info.
Some devices use a single pin as both an IRQ and a GPIO. In that case,
irq_gpio is the GPIO ID for that pin. Not all drivers use this feature.
Where they do, and the use of this feature is optional, and the system
wishes to disable this feature, this field must be explicitly set to a
defined invalid GPIO ID, such as -1.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
v3: Also add the field to i2c_board_info, and copy the field from
i2c_board_info to i2c_client upon instantiation
drivers/i2c/i2c-core.c |1 +
include/linux/i2c.h|9 +
2 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/drivers/i2c/i2c-core.c b/drivers/i2c/i2c-core.c
index 131079a..da12540 100644
--- a/drivers/i2c/i2c-core.c
+++ b/drivers/i2c/i2c-core.c
@@ -518,6 +518,7 @@ i2c_new_device(struct i2c_adapter *adap, struct
i2c_board_info const *info)
client-flags = info-flags;
client-addr = info-addr;
client-irq = info-irq;
+ client-irq_gpio = info-irq_gpio;
strlcpy(client-name, info-type, sizeof(client-name));
diff --git a/include/linux/i2c.h b/include/linux/i2c.h
index 3fad485..49e2e36 100644
--- a/include/linux/i2c.h
+++ b/include/linux/i2c.h
@@ -192,6 +192,12 @@ struct i2c_driver {
* @driver: device's driver, hence pointer to access routines
* @dev: Driver model device node for the slave.
* @irq: indicates the IRQ generated by this device (if any)
+ * @irq_gpio: some devices use a single pin as both an IRQ and a GPIO. In
+ * that case, irq_gpio is the GPIO ID for that pin. Not all drivers
+ * use this feature. Where they do, and the use of this feature is
+ * optional, and the system wishes to disable this feature, this
+ * field must be explicitly set to a defined invalid GPIO ID, such
+ * as -1.
* @detected: member of an i2c_driver.clients list or i2c-core's
* userspace_devices list
*
@@ -209,6 +215,7 @@ struct i2c_client {
struct i2c_driver *driver; /* and our access routines */
struct device dev; /* the device structure */
int irq;/* irq issued by device */
+ int irq_gpio; /* gpio corresponding to irq*/
struct list_head detected;
};
#define to_i2c_client(d) container_of(d, struct i2c_client, dev)
@@ -240,6 +247,7 @@ static inline void i2c_set_clientdata(struct i2c_client
*dev, void *data)
* @archdata: copied into i2c_client.dev.archdata
* @of_node: pointer to OpenFirmware device node
* @irq: stored in i2c_client.irq
+ * @irq_gpio: stored in i2c_client.irq_gpio
*
* I2C doesn't actually support hardware probing, although controllers and
* devices may be able to use I2C_SMBUS_QUICK to tell whether or not there's
@@ -260,6 +268,7 @@ struct i2c_board_info {
struct dev_archdata *archdata;
struct device_node *of_node;
int irq;
+ int irq_gpio;
};
/**
--
1.7.0.4
--
Special Offer -- Download ArcSight Logger for FREE!
Finally, a world-class log management solution at an even better
price-free! And you'll get a free Love Thy Logs t-shirt when you
download Logger. Secure your free ArcSight Logger TODAY!
http://p.sf.net/sfu/arcsisghtdev2dev
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH V3 5/5] staging:iio:magnetometer:ak8975: Fix probe() error-handling
Fix ak8975_probe() to jump to the appropriate exit labels when an error
occurs. With the previous code, some cleanup actions were being skipped
for some error conditions.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
drivers/staging/iio/magnetometer/ak8975.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/staging/iio/magnetometer/ak8975.c
b/drivers/staging/iio/magnetometer/ak8975.c
index 0dfdf50..cc20e8d 100644
--- a/drivers/staging/iio/magnetometer/ak8975.c
+++ b/drivers/staging/iio/magnetometer/ak8975.c
@@ -510,7 +510,7 @@ static int ak8975_probe(struct i2c_client *client,
err = ak8975_setup(client);
if (err 0) {
dev_err(client-dev, AK8975 initialization fails\n);
- goto exit_gpio;
+ goto exit_free_iio;
}
i2c_set_clientdata(client, indio_dev);
--
1.7.0.4
--
Special Offer -- Download ArcSight Logger for FREE!
Finally, a world-class log management solution at an even better
price-free! And you'll get a free Love Thy Logs t-shirt when you
download Logger. Secure your free ArcSight Logger TODAY!
http://p.sf.net/sfu/arcsisghtdev2dev
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH V3 4/5] staging:iio:magnetometer:ak8975: Don't assume 0 is an invalid GPIO
gpio_is_valid() is the defined mechanism to determine whether a GPIO is
valid. Use this instead of assuming that 0 is an invalid GPIO.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
drivers/staging/iio/magnetometer/ak8975.c | 11 +--
1 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/staging/iio/magnetometer/ak8975.c
b/drivers/staging/iio/magnetometer/ak8975.c
index 14076da..0dfdf50 100644
--- a/drivers/staging/iio/magnetometer/ak8975.c
+++ b/drivers/staging/iio/magnetometer/ak8975.c
@@ -373,7 +373,7 @@ static int ak8975_read_axis(struct iio_dev *indio_dev, int
index, int *val)
}
/* Wait for the conversion to complete. */
- if (data-eoc_gpio)
+ if (gpio_is_valid(data-eoc_gpio))
ret = wait_conversion_complete_gpio(data);
else
ret = wait_conversion_complete_polled(data);
@@ -481,7 +481,7 @@ static int ak8975_probe(struct i2c_client *client,
/* We may not have a GPIO based IRQ to scan, that is fine, we will
poll if so */
- if (eoc_gpio 0) {
+ if (gpio_is_valid(eoc_gpio)) {
err = gpio_request(eoc_gpio, ak_8975);
if (err 0) {
dev_err(client-dev,
@@ -497,8 +497,7 @@ static int ak8975_probe(struct i2c_client *client,
eoc_gpio, err);
goto exit_gpio;
}
- } else
- eoc_gpio = 0; /* No GPIO available */
+ }
/* Register with IIO */
indio_dev = iio_allocate_device(sizeof(*data));
@@ -534,7 +533,7 @@ static int ak8975_probe(struct i2c_client *client,
exit_free_iio:
iio_free_device(indio_dev);
exit_gpio:
- if (eoc_gpio)
+ if (gpio_is_valid(eoc_gpio))
gpio_free(eoc_gpio);
exit:
return err;
@@ -549,7 +548,7 @@ static int ak8975_remove(struct i2c_client *client)
iio_device_unregister(indio_dev);
iio_free_device(indio_dev);
- if (eoc_gpio)
+ if (gpio_is_valid(eoc_gpio))
gpio_free(eoc_gpio);
return 0;
--
1.7.0.4
--
Special Offer -- Download ArcSight Logger for FREE!
Finally, a world-class log management solution at an even better
price-free! And you'll get a free Love Thy Logs t-shirt when you
download Logger. Secure your free ArcSight Logger TODAY!
http://p.sf.net/sfu/arcsisghtdev2dev
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH] spi/tegra: Use engineering names in DT compatible property
Engineering names are more stable than marketing names. Hence, use them
for Device Tree compatible properties instead.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
Grant, this is against devicetree/arm, and also makes sense for
devicetree/test.
.../devicetree/bindings/spi/spi_nvidia.txt |2 +-
drivers/spi/spi_tegra.c|2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/spi_nvidia.txt
b/Documentation/devicetree/bindings/spi/spi_nvidia.txt
index bde450b..6b9e518 100644
--- a/Documentation/devicetree/bindings/spi/spi_nvidia.txt
+++ b/Documentation/devicetree/bindings/spi/spi_nvidia.txt
@@ -1,5 +1,5 @@
NVIDIA Tegra 2 SPI device
Required properties:
-- compatible : should be nvidia,tegra250-spi.
+- compatible : should be nvidia,tegra20-spi.
- gpios : should specify GPIOs used for chipselect.
diff --git a/drivers/spi/spi_tegra.c b/drivers/spi/spi_tegra.c
index 1e7de98..b0e3586 100644
--- a/drivers/spi/spi_tegra.c
+++ b/drivers/spi/spi_tegra.c
@@ -598,7 +598,7 @@ MODULE_ALIAS(platform:spi_tegra);
#ifdef CONFIG_OF
static struct of_device_id spi_tegra_of_match_table[] __devinitdata = {
- { .compatible = nvidia,tegra250-spi, },
+ { .compatible = nvidia,tegra20-spi, },
{}
};
MODULE_DEVICE_TABLE(of, spi_tegra_of_match_table);
--
1.7.0.4
--
All of the data generated in your IT infrastructure is seriously valuable.
Why? It contains a definitive record of application performance, security
threats, fraudulent activity, and more. Splunk takes this data and makes
sense of it. IT sense. And common sense.
http://p.sf.net/sfu/splunk-d2d-c2
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
RE: [PATCH] spi/tegra: add devicetree support
Grant Likely wrote at Wednesday, June 15, 2011 1:08 PM:
Allow the tegra spi driver to obtain populate the spi bus with devices
Remote obtain?
from the device tree.
Signed-off-by: Grant Likely grant.lik...@secretlab.ca
---
.../devicetree/bindings/spi/spi_nvidia.txt |5 +
drivers/spi/spi-tegra.c| 12
2 files changed, 17 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/spi_nvidia.txt
diff --git a/Documentation/devicetree/bindings/spi/spi_nvidia.txt
b/Documentation/devicetree/bindings/spi/spi_nvidia.txt
new file mode 100644
index 000..bde450b
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi_nvidia.txt
@@ -0,0 +1,5 @@
+NVIDIA Tegra 2 SPI device
+
+Required properties:
+- compatible : should be nvidia,tegra250-spi.
+- gpios : should specify GPIOs used for chipselect.
Are things like reg, interrupts, and other general stuff implicit?
I notice that fsl-spi.txt does specify those, but spi_altera.txt
and spi_oc_tiny.txt don't.
Otherwise, LGTM.
diff --git a/drivers/spi/spi-tegra.c b/drivers/spi/spi-tegra.c
index 8e30727..a43ceeb 100644
--- a/drivers/spi/spi-tegra.c
+++ b/drivers/spi/spi-tegra.c
@@ -546,6 +546,7 @@ static int __init spi_tegra_probe(struct
platform_device *pdev)
tspi-rx_dma_req.req_sel = spi_tegra_req_sels[pdev-id];
tspi-rx_dma_req.dev = tspi;
+ master-dev.of_node = pdev-dev.of_node;
ret = spi_register_master(master);
if (ret 0)
@@ -595,10 +596,21 @@ static int __devexit spi_tegra_remove(struct
platform_device *pdev)
MODULE_ALIAS(platform:spi_tegra);
+#ifdef CONFIG_OF
+static struct of_device_id spi_tegra_of_match_table[] __devinitdata = {
+ { .compatible = nvidia,tegra250-spi, },
+ {}
+};
+MODULE_DEVICE_TABLE(of, spi_tegra_of_match_table);
+#else /* CONFIG_OF */
+#define spi_tegra_of_match_table NULL
+#endif /* CONFIG_OF */
+
static struct platform_driver spi_tegra_driver = {
.driver = {
.name = spi_tegra,
.owner =THIS_MODULE,
+ .of_match_table = spi_tegra_of_match_table,
},
.remove = __devexit_p(spi_tegra_remove),
};
--
nvpublic
--
EditLive Enterprise is the world's most technically advanced content
authoring tool. Experience the power of Track Changes, Inline Image
Editing and ensure content is compliant with Accessibility Checking.
http://p.sf.net/sfu/ephox-dev2dev
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
