On Tue, Feb 05, 2013 at 08:24:33AM -0300, Ezequiel Garcia wrote:
This patch adds an SPI master device node for Armada XP-GP board.
This master node is an SPI flash controller 'n25q128a13'.
Since there is no 'partitions' node declared, one full sized
partition named as the device will be
And don't forget to compile the SPI flash driver, CONFIG_MTD_M25P80=y
Hi Ezequiel
Maybe it makes sense to provide a patch to mvebu_defconfig to add
CONFIG_MTD_M25P80=y ?
Andrew
--
Free Next-Gen Firewall
On Wed, 26 Dec 2012 10:48:33 +0800, Barry Song barry.s...@csr.com wrote:
From: Barry Song baohua.s...@csr.com
Convert clk_enable/clk_disable to clk_prepare_enable/clk_disable_unprepare
calls as required by common clock framework.
Signed-off-by: Barry Song baohua.s...@csr.com
Applied,
On Mon, Feb 04, 2013 at 09:47:38PM +, Arnd Bergmann wrote:
On Monday 04 February 2013, Linus Walleij wrote:
So I think the above concerns are moot. The callback we can
set on cookies is entirely optional, and it's even implemented by
each DMA engine, and some may not even support it but
On Wed, 26 Dec 2012 14:48:51 +0900, Juha Lumme juha.lu...@gmail.com wrote:
On MX23 the XFER_COUNT part in ctrl0 field in DMA descriptor was improperly
OR'd during the construction of DMA descriptor chain, instead of being
freshly set.
Because of that too many bytes were being expected from SPI
On Mon, Feb 04, 2013 at 04:54:45PM -0500, Cyril Chemparathy wrote:
You're assuming that cookies complete in order. That is not necessarily
true.
Under what circumstances is that not true?
--
Free Next-Gen Firewall
Morning-ish Andrew,
On Tue, Feb 05, 2013 at 01:38:27PM +0100, Andrew Lunn wrote:
And don't forget to compile the SPI flash driver, CONFIG_MTD_M25P80=y
Maybe it makes sense to provide a patch to mvebu_defconfig to add
CONFIG_MTD_M25P80=y ?
I thought this as well, then reconsidered when he
On Thu, 27 Dec 2012 10:42:24 +0100, Gabor Juhos juh...@openwrt.org wrote:
The driver uses the as fast as it can approach
to drive the SCK signal. However this does not
work with certain low speed SPI chips (e.g. the
PCF2123 RTC chip).
The patch adds per-bit slowdowns in order to be
able to
On Thu, 27 Dec 2012 10:42:25 +0100, Gabor Juhos juh...@openwrt.org wrote:
The 'ath79_spi_txrx_mode0' function does not
set the SCK signal to LOW at the end of a word
transfer. This causes communications errors with
certain devices (e.g. the PCF2123 RTC chip).
The patch ensures that the SCK
On Thu, 27 Dec 2012 10:42:26 +0100, Gabor Juhos juh...@openwrt.org wrote:
The spi_bitbang driver calls the chipselect function
of the driver from spi_bitbang_setup in order to
deselect the given SPI chip, so we don't have to
initialize the CS line here.
Signed-off-by: Gabor Juhos
On Thu, 27 Dec 2012 10:42:27 +0100, Gabor Juhos juh...@openwrt.org wrote:
Use gpio_request_one() instead of multiple gpiolib calls.
Signed-off-by: Gabor Juhos juh...@openwrt.org
Applied, thanks.
g.
---
drivers/spi/spi-ath79.c | 22 +++---
1 file changed, 11
On Thu, 27 Dec 2012 10:42:29 +0100, Gabor Juhos juh...@openwrt.org wrote:
The SPI controller of the AR7xxx/AR9xxx SoCs
have a special mode which allows the SoC to
directly read data from SPI flash chips. In
this mode, the content of the SPI flash chip
can be accessed via a memory mapped
On Tue, 22 Jan 2013 16:50:30 +0100, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On 09/01/2013 09:37, Maxime Ripard wrote:
On 27/12/2012 22:54, Maxime Ripard wrote:
The bindings assumed that the gpios properties were always there, which
made the NO_TX and NO_RX mode not usable
On Sat, 5 Jan 2013 00:17:14 +0530, Laxman Dewangan ldewan...@nvidia.com wrote:
When spi client does the spi transfer and if it does not set
the speed for each transfer then set it as default
of spi device in spi core before calling low level transfer.
This will remove the extra check in low
On Sat, 5 Jan 2013 00:17:15 +0530, Laxman Dewangan ldewan...@nvidia.com wrote:
SPI core make sure that all transfer has proper speed set
before calling low level spi transfer. Hence, it is not
require to have check in spi driver.
Remove the check for speed validity from transfer and use it
On Mon, 7 Jan 2013 20:42:55 -0200, Fabio Estevam feste...@gmail.com wrote:
From: Fabio Estevam fabio.este...@freescale.com
Add an entry for MODULE_ALIAS().
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
Applied, thanks.
g.
---
drivers/spi/spi-imx.c |1 +
1 file
On Thu, 10 Jan 2013 11:04:21 +0900, Jingoo Han jg1@samsung.com wrote:
Use devm_clk_get() and devm_request_irq() rather than clk_get() and
request_irq() to make cleanup paths more simple.
Signed-off-by: Jingoo Han jg1@samsung.com
Applied, thanks.
g.
On Thu, 31 Jan 2013 15:25:01 +0900, Jingoo Han jg1@samsung.com wrote:
Fix checkpatch warnings and error as below:
ERROR: foo * bar should be foo *bar
WARNING: please, no space before tabs
WARNING: quoted string split across lines
WARNING: msleep 20ms can sleep for up to 20ms; see
On Fri, 25 Jan 2013 14:14:31 +, Arnd Bergmann a...@arndb.de wrote:
Since we no longer allow building without hotplug, the
atmel_spi_remove function is always present and we should
not use __exit_p() to refer to it.
Without this patch, building at91_dt_defconfig results in:
On Fri, 1 Feb 2013 20:40:17 +0100 (CET), MichaÅ MirosÅaw
mirq-li...@rere.qmqm.pl wrote:
All in-kernel users of class_find_device() don't really need mutable
data for match callback.
In two places (kernel/power/suspend_test.c, drivers/scsi/osd/osd_uld.c)
this patch changes match callbacks
Hi Ezequiel,
On 02/04/2013 05:38 PM, Ezequiel Garcia wrote:
The Armada 370 and Armada XP SoC has an SPI controller.
This patch adds support for this controller in Armada 370
and Armada XP SoC common device tree files.
Cc: Gregory Clement gregory.clem...@free-electrons.com
Cc: Thomas
Some of the spi driver module remove hooks were annotated with __exit
and referenced with __exit_p(). Presumably these were supposed to be
__devexit and __devexit_p() since __exit for a remove hook has never
been correct. They also got missed during the big __devexit purge since
they didn't match
On Sun, 27 Jan 2013 03:33:59 +, Mark Brown
broo...@opensource.wolfsonmicro.com wrote:
On Wed, Jan 09, 2013 at 06:31:09PM +0100, Lars-Peter Clausen wrote:
The second function spi_sync_transfer() takes a SPI device and an array of
spi_transfers. It will allocate a new spi_message (on the
On Fri, 11 Jan 2013 01:05:48 +0100, Anatolij Gustschin ag...@denx.de wrote:
Remove deprecated cell-index property and use spi alias to
obtain the SPI PSC number used for SPI bus id.
Signed-off-by: Anatolij Gustschin ag...@denx.de
---
v2:
- use of_alias_get_id() to get spi bus number
On Mon, 14 Jan 2013 21:27:00 +0100, Anatolij Gustschin ag...@denx.de wrote:
The driver should setup mode bits it supports, otherwise
adding an SPI device might fail even if the driver supports
the requested SPI mode.
Signed-off-by: Anatolij Gustschin ag...@denx.de
Applied, thanks.
g.
---
On Mon, 14 Jan 2013 21:27:01 +0100, Anatolij Gustschin ag...@denx.de wrote:
Currently the driver only uses one internal chip select. Add support
for gpio chip selects configured by gpio specifiers in the device tree.
Signed-off-by: Anatolij Gustschin ag...@denx.de
GPIO chip selects are now
On Mon, 21 Jan 2013 11:09:18 +0100, Thierry Reding
thierry.red...@avionic-design.de wrote:
Convert all uses of devm_request_and_ioremap() to the newly introduced
devm_ioremap_resource() which provides more consistent error handling.
devm_ioremap_resource() provides its own error messages so
On Sun, 27 Jan 2013 14:35:04 +0800, Mark Brown
broo...@opensource.wolfsonmicro.com wrote:
Use GFP_DMA in order to ensure that the memory we allocate for transfers
in spi_write_then_read() can be DMAed. On most platforms this will have
no effect.
Signed-off-by: Mark Brown
On Mon, 28 Jan 2013 17:57:34 +, Arnd Bergmann a...@arndb.de wrote:
With the new OF DMA binding, it is possible to completely avoid the
need for platform_data for configuring a DMA channel. In cases where the
platform has already been converted, calling dma_request_slave_channel
should get
On Mon, 28 Jan 2013 17:57:35 +, Arnd Bergmann a...@arndb.de wrote:
With the new OF DMA binding, it is possible to completely avoid the
need for platform_data for configuring a DMA channel. In cases where the
platform has already been converted, calling dma_request_slave_channel
should get
On Tue, Feb 05, 2013 at 07:48:33AM -0500, Jason Cooper wrote:
Morning-ish Andrew,
On Tue, Feb 05, 2013 at 01:38:27PM +0100, Andrew Lunn wrote:
And don't forget to compile the SPI flash driver, CONFIG_MTD_M25P80=y
Maybe it makes sense to provide a patch to mvebu_defconfig to add
On Sun, 3 Feb 2013 15:15:11 +0100, Jonas Gorski j...@openwrt.org wrote:
The bcm63xx SPI controller does not support keeping CS up after doing a
transfer. Since this is problematic for most typical use cases, this
patchset introduces a workaround by combining small enough messages
to one
On Sun, 3 Feb 2013 15:15:12 +0100, Jonas Gorski j...@openwrt.org wrote:
The hardware does not support keeping CS asserted after sending one
FIFO buffer worth of data, so reject transfers requiring CS being kept
asserted, either between transers or for a certain time after it,
or exceeding the
On Sun, 3 Feb 2013 15:15:13 +0100, Jonas Gorski j...@openwrt.org wrote:
This SPI controller does not support keeping CS asserted after sending
a transfer.
Since messages expected on this SPI controller are rather short, we can
work around it for normal use cases by sending all transfers at
On Mon, 4 Feb 2013 09:26:26 -0300, Ezequiel Garcia
ezequiel.gar...@free-electrons.com wrote:
This patch reduces and simplifies initalization code by
using module_platform_driver().
With this change it's necessary to remove the __init annotation
to avoid section mismatch warnings.
Some of the spi driver module remove hooks were annotated with __exit
and referenced with __exit_p(). Presumably these were supposed to be
__devinit, __devexit and __devexit_p() since __init/__exit for a
probe/remove hook has never been correct. They also got missed during
the big
On Tue, 05 Feb 2013 14:35:30 +
Grant Likely grant.lik...@secretlab.ca wrote:
On Sun, 3 Feb 2013 15:15:13 +0100, Jonas Gorski j...@openwrt.org wrote:
This SPI controller does not support keeping CS asserted after sending
a transfer.
Since messages expected on this SPI controller are
On Mon, Feb 4, 2013 at 10:54 PM, Cyril Chemparathy cy...@ti.com wrote:
On 02/04/2013 04:11 PM, Linus Walleij wrote:
Cyril, just stack up the cookies and take a sweep over them to see
which ones are baked when the NAPI poll comes in - problem
solved.
You're assuming that cookies complete in
On Tue, Feb 05, 2013 at 11:27:21AM -0300, Ezequiel Garcia wrote:
On Tue, Feb 05, 2013 at 07:48:33AM -0500, Jason Cooper wrote:
Morning-ish Andrew,
On Tue, Feb 05, 2013 at 01:38:27PM +0100, Andrew Lunn wrote:
And don't forget to compile the SPI flash driver, CONFIG_MTD_M25P80=y
On 02/05/2013 07:38 AM, Russell King - ARM Linux wrote:
On Mon, Feb 04, 2013 at 09:47:38PM +, Arnd Bergmann wrote:
On Monday 04 February 2013, Linus Walleij wrote:
So I think the above concerns are moot. The callback we can
set on cookies is entirely optional, and it's even implemented by
On 02/05/2013 07:41 AM, Russell King - ARM Linux wrote:
On Mon, Feb 04, 2013 at 04:54:45PM -0500, Cyril Chemparathy wrote:
You're assuming that cookies complete in order. That is not necessarily
true.
Under what circumstances is that not true?
Notably when hardware can prioritize certain
Dear Jason Cooper,
On Tue, 5 Feb 2013 10:31:35 -0500, Jason Cooper wrote:
One thing we've been doing a lot of with mvebu is using it for
build-testing. For that use case, since the bootloader is there, I'd
recommend setting it. This will reduce the likelyhood of nasty build
breakages
On 02/05/2013 05:17 PM, Thomas Petazzoni wrote:
Dear Jason Cooper,
On Tue, 5 Feb 2013 10:31:35 -0500, Jason Cooper wrote:
One thing we've been doing a lot of with mvebu is using it for
build-testing. For that use case, since the bootloader is there, I'd
recommend setting it. This will
On Mon, Feb 4, 2013 at 11:30 PM, Cyril Chemparathy cy...@ti.com wrote:
NAPI needs to switch between polled and interrupt driven modes of operation.
Further, in a given poll, it needs to be able to limit the amount of traffic
processed to a specified budget.
I don't think any of this is a
On Tue, Feb 05, 2013 at 05:17:01PM +0100, Thomas Petazzoni wrote:
Dear Jason Cooper,
On Tue, 5 Feb 2013 10:31:35 -0500, Jason Cooper wrote:
One thing we've been doing a lot of with mvebu is using it for
build-testing. For that use case, since the bootloader is there, I'd
recommend
Hi Ezequiel,
On 02/05/2013 12:24 PM, Ezequiel Garcia wrote:
This patch adds an SPI master device node for Armada XP-GP board.
This master node is an SPI flash controller 'n25q128a13'.
Since there is no 'partitions' node declared, one full sized
partition named as the device will be created.
On Tue, Feb 05, 2013 at 04:47:05PM +, Mark Brown wrote:
On Tue, Feb 05, 2013 at 05:21:48PM +0100, Linus Walleij wrote:
For IRQ mode, use the completion callback to push each cookie
to NAPI, and thus let the IRQ drive the traffic.
The whole purpose of NAPI is to avoid taking
On Tue, Feb 05, 2013 at 04:30:45PM +0100, Linus Walleij wrote:
On Mon, Feb 4, 2013 at 10:54 PM, Cyril Chemparathy cy...@ti.com wrote:
On 02/04/2013 04:11 PM, Linus Walleij wrote:
Cyril, just stack up the cookies and take a sweep over them to see
which ones are baked when the NAPI poll
On Tue, Feb 05, 2013 at 06:07:05PM +0100, Thomas Petazzoni wrote:
Of course, it doesn't make sense to have drivers for pluggable devices
like PCIe devices that are not soldered, USB devices and things like
that. But for all the rest, I would say it should be in the defconfig.
hmmm, so for the
On Wed, 30 Jan 2013 21:33:31 +0100, John Crispin blo...@openwrt.org wrote:
Due to hardware limitations of the spi/flash frontend of the EBU we need to
set
the SPI_MASTER_HALF_DUPLEX flag.
Signed-off-by: Thomas Langer thomas.lan...@lantiq.com
Signed-off-by: John Crispin blo...@openwrt.org
On Fri, 18 Jan 2013 10:03:28 +0100, Thomas De Schampheleire
patrickdepinguin+spide...@gmail.com wrote:
Hi,
The Freescale eSPI controller driver is broken in several ways. I already
attempted to fix this with a patch many months back. The patch works for
me, but never got feedback from the
On Wed, 2 Jan 2013 10:19:08 -0500, Murali Karicheri m-kariche...@ti.com wrote:
On 12/22/2012 05:08 AM, Grant Likely wrote:
On Fri, 21 Dec 2012 15:13:26 -0500, Murali Karicherim-kariche...@ti.com
wrote:
With RT pre-empt patch applied to Linux kernel, the irq handler will be
force
On Tue, 5 Feb 2013 15:04:41 +, Mark Brown
broo...@opensource.wolfsonmicro.com wrote:
On Tue, Feb 05, 2013 at 02:30:40PM +, Grant Likely wrote:
Another option is to allow longer transfers if a GPIO is used for the CS
line. A lot of SPI controllers need to do that.
That isn't a
On Wed, 30 Jan 2013 13:15:24 +0100, Andreas Larsson andr...@gaisler.com wrote:
This makes the cpu mode of the driver available outside of an FSL SOC
and even powerpc environment. This is accomplished by putting things
regarding fsl specific code and to cpm specific code within ifdefs.
On Wed, 30 Jan 2013 21:33:30 +0100, John Crispin blo...@openwrt.org wrote:
Rather than calling m-complete() directly we choose the sane way and call
spi_finalize_current_message instead.
Signed-off-by: Thomas Langer thomas.lan...@lantiq.com
Signed-off-by: John Crispin blo...@openwrt.org
On Thu, 10 Jan 2013 13:04:37 +0100 (CET), Guennadi Liakhovetski
g.liakhovet...@gmx.de wrote:
On Thu, 10 Jan 2013, Linus Walleij wrote:
On Wed, Jan 9, 2013 at 3:44 PM, Guennadi Liakhovetski
g.liakhovet...@gmx.de wrote:
[ 79.968000] mmc0: new SD card on SPI
[ 79.976000] mmcblk0:
On Sun, 30 Dec 2012 18:14:55 +0900, Juha Lumme juha.lu...@gmail.com wrote:
Hi,
I am having issues communicating with a micro controller connected to
SPI bus, using spidev.
I would like to send messages to my MSP430 from user land, but so far no
luck.
At least I know that my SPI bus
On Tue, 5 Feb 2013 16:00:04 +0100, Jonas Gorski j...@openwrt.org wrote:
On Tue, 05 Feb 2013 14:35:30 +
Grant Likely grant.lik...@secretlab.ca wrote:
On Sun, 3 Feb 2013 15:15:13 +0100, Jonas Gorski j...@openwrt.org wrote:
This SPI controller does not support keeping CS asserted after
* Felipe Balbi ba...@ti.com [130204 07:46]:
Current DMA abstraction is quite poor, for example there's no way to
compile support for multiple DMA engines. Code also makes certain, IMO
unnecessary, assumptions about the underlying DMA engine (abstraction is
poor, as said above but it we could
On Tue, Feb 5, 2013 at 5:47 PM, Mark Brown
broo...@opensource.wolfsonmicro.com wrote:
On Tue, Feb 05, 2013 at 05:21:48PM +0100, Linus Walleij wrote:
For IRQ mode, use the completion callback to push each cookie
to NAPI, and thus let the IRQ drive the traffic.
The whole purpose of NAPI is to
On Tue, Feb 5, 2013 at 6:14 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Tue, Feb 05, 2013 at 04:30:45PM +0100, Linus Walleij wrote:
So put them on a wait list? Surely you will have a list of pending
cookies and pick from the front of the queue if there isn't a hole on
queue
On 02/05/2013 01:29 PM, Linus Walleij wrote:
On Tue, Feb 5, 2013 at 5:47 PM, Mark Brown
broo...@opensource.wolfsonmicro.com wrote:
On Tue, Feb 05, 2013 at 05:21:48PM +0100, Linus Walleij wrote:
For IRQ mode, use the completion callback to push each cookie
to NAPI, and thus let the IRQ drive
On Tue, Feb 05, 2013 at 06:07:05PM +0100, Thomas Petazzoni wrote:
Dear Gregory CLEMENT,
On Tue, 05 Feb 2013 17:20:02 +0100, Gregory CLEMENT wrote:
So that means we should enable the drivers for all the devices present
on all the boards?
Yes. For example my mvsdio patch set enables
Hi Grant,
On Thu, 27 Dec 2012 10:42:24 +0100, Gabor Juhos juh...@openwrt.org wrote:
The driver uses the as fast as it can approach
to drive the SCK signal. However this does not
work with certain low speed SPI chips (e.g. the
PCF2123 RTC chip).
The patch adds per-bit slowdowns in order to
2013.02.05. 14:02 keltezéssel, Grant Likely írta:
-static int ath79_spi_remove(struct platform_device *pdev)
+static void __ath79_spi_remove(struct platform_device *pdev)
{
struct ath79_spi *sp = platform_get_drvdata(pdev);
@@ -304,13 +304,23 @@ static int ath79_spi_remove(struct
The SPI controller of the AR7xxx/AR9xxx SoCs
have a special mode which allows the SoC to
directly read data from SPI flash chips. In
this mode, the content of the SPI flash chip
can be accessed via a memory mapped region.
During early init time, the kernel expects
that the flash chip is
On 02/05/2013 05:28 PM, Gregory CLEMENT wrote:
Hi Ezequiel,
On 02/05/2013 12:24 PM, Ezequiel Garcia wrote:
This patch adds an SPI master device node for Armada XP-GP board.
This master node is an SPI flash controller 'n25q128a13'.
Since there is no 'partitions' node declared, one full
Hi,
Following the Ezequiel's patches this patch set add support for SPI
data Flash for two other development board from Marvell.
This pacthes depend on the SPI serie of Ezequiel [1], and also on the
selection of CONFIG_MTD_M25P80=y in the config file.
[1]
This patch add support for the SPI flash MX25l25635E which is present
on the Armada 370 DB board. This flash stores the bootloader and its
environment.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/boot/dts/armada-370-db.dts | 11 +++
1 file changed, 11
On Tuesday 05 February 2013, Tony Lindgren wrote:
* Felipe Balbi ba...@ti.com [130204 07:46]:
Current DMA abstraction is quite poor, for example there's no way to
compile support for multiple DMA engines. Code also makes certain, IMO
unnecessary, assumptions about the underlying DMA
This patch adds support for spi controllers with
dedicated clk/miso/mosi/cs pins. It skips the gpio
parsing and initialization for controllers that
have dedicated pins.
Signed-off-by: Girish K S ks.g...@samsung.com
---
drivers/spi/spi-s3c64xx.c | 39 +++
1
[PATCH 1/4]: fixes the error handling in the interrupt handler
[PATCH 2/4]: The existing driver support partial polling mode.
This patch modifies the current driver to support
only polling mode.
[PATCH 3/4]: Adds quirk to support SoC's with dedicated i/o pins
[PATCH 4/4]:
The 64xx spi driver supports partial polling mode.
Only the last chunk of the transfer length is transferred
or recieved in polling mode.
Some SoC's that adopt this controller might not have have dma
interface. This patch adds support for complete polling mode
and gives flexibity for the user to
The status of the interrupt is available in the status register,
so reading the clear pending register and writing back the same
value will not actually clear the pending interrupts. This patch
modifies the interrupt handler to read the status register and
clear the corresponding pending bit in
This patch adds support for the exynos5440 spi controller.
The integration of the spi IP in exynos5440 is different from
other SoC's. The I/O pins are no more configured via gpio, they
have dedicated pins.
Signed-off-by: Girish K S ks.g...@samsung.com
---
drivers/spi/spi-s3c64xx.c | 12
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