Re: svn commit: r314389 - in head/sys: arm/altera/socfpga arm/conf boot/fdt/dts/arm

[Andrew Turner]

On Tue, 28 Feb 2017 14:02:16 + (UTC)
Ruslan Bukin  wrote:

> Author: br
> Date: Tue Feb 28 14:02:16 2017
> New Revision: 314389
> URL: https://svnweb.freebsd.org/changeset/base/314389
> 
> Log:
>   Add support for Intel Arria 10 SoC Development Kit.
>   Use standard DTS files for SOCKIT and SOCDK.
>   
>   Sponsored by:   DARPA, AFRL
> 
> Added:
>   head/sys/arm/conf/SOCDK   (contents, props changed)
>   head/sys/arm/conf/SOCFPGA   (contents, props changed)
>   head/sys/boot/fdt/dts/arm/socfpga_arria10_socdk_sdmmc.dts
> (contents, props changed)
> head/sys/boot/fdt/dts/arm/socfpga_cyclone5_sockit_beri_sdmmc.dts
> (contents, props changed)
> head/sys/boot/fdt/dts/arm/socfpga_cyclone5_sockit_sdmmc.dts
> (contents, props changed) Deleted: head/sys/arm/conf/SOCKIT.common
> head/sys/boot/fdt/dts/arm/socfpga-sockit-beri.dts
> head/sys/boot/fdt/dts/arm/socfpga-sockit.dts
> head/sys/boot/fdt/dts/arm/socfpga.dtsi Modified:
>   head/sys/arm/altera/socfpga/socfpga_machdep.c
>   head/sys/arm/altera/socfpga/socfpga_manager.c
>   head/sys/arm/altera/socfpga/socfpga_mp.c
>   head/sys/arm/altera/socfpga/socfpga_mp.h
>   head/sys/arm/altera/socfpga/socfpga_rstmgr.c
>   head/sys/arm/altera/socfpga/socfpga_rstmgr.h
>   head/sys/arm/conf/SOCKIT
>   head/sys/arm/conf/SOCKIT-BERI
> 
> Modified: head/sys/arm/altera/socfpga/socfpga_machdep.c
> ==
> --- head/sys/arm/altera/socfpga/socfpga_machdep.c Tue Feb 28
> 12:05:58 2017 (r314388) +++
> head/sys/arm/altera/socfpga/socfpga_machdep.c Tue Feb 28
> 14:02:16 2017 (r314389) @@ -1,5 +1,5 @@ /*-
> - * Copyright (c) 2014 Ruslan Bukin 
> + * Copyright (c) 2014-2017 Ruslan Bukin 
>   * All rights reserved.
>   *
>   * This software was developed by SRI International and the
> University of @@ -83,24 +83,43 @@ socfpga_devmap_init(platform_t plat)
>   return (0);
>  }
>  
> +static int
> +socfpga_a10_devmap_init(platform_t plat)

You should create a SOC_ALTERA_ARRIA10 (or similar) option and use it
to conditionally compile this code.

> +{
> +
> + /* UART */
> + devmap_add_entry(0xffc0, 0x10);
> +
> + /* USB OTG */
> + devmap_add_entry(0xffb0, 0x10);
> +
> + /* dwmmc */
> + devmap_add_entry(0xff80, 0x10);
> +
> + /* scu */
> + devmap_add_entry(0xfff0, 0x10);
> +
> + return (0);
> +}
> +
>  static void
> -socfpga_cpu_reset(platform_t plat)
> +_socfpga_cpu_reset(platform_t plat, uint32_t reg)

Why are you passing the platform_t into this? And reg should be a
bus_size_t.

>  {
>   uint32_t paddr;
>   bus_addr_t vaddr;
>   phandle_t node;
>  
> - if (rstmgr_warmreset() == 0)
> + if (rstmgr_warmreset(reg) == 0)
>   goto end;
>  
> - node = OF_finddevice("rstmgr");
> + node = OF_finddevice("/soc/rstmgr");
>   if (node == -1)
>   goto end;
>  
>   if ((OF_getencprop(node, "reg", , sizeof(paddr))) > 0)
> { if (bus_space_map(fdtbus_bs_tag, paddr, 0x8, 0, ) == 0) {
>   bus_space_write_4(fdtbus_bs_tag, vaddr,
> - RSTMGR_CTRL, CTRL_SWWARMRSTREQ);
> + reg, CTRL_SWWARMRSTREQ);
>   }
>   }
>  
> @@ -108,16 +127,38 @@ end:
>   while (1);
>  }
>  
> +static void
> +socfpga_cpu_reset(platform_t plat)
> +{
> +
> + _socfpga_cpu_reset(plat, RSTMGR_CTRL);
> +}
> +
> +static void
> +socfpga_a10_cpu_reset(platform_t plat)
> +{
> +
> + _socfpga_cpu_reset(plat, RSTMGR_A10_CTRL);
> +}

these two and the methods below should be under SOC_ checks.

> +
>  static platform_method_t socfpga_methods[] = {
>   PLATFORMMETHOD(platform_devmap_init,
> socfpga_devmap_init), PLATFORMMETHOD(platform_cpu_reset,
> socfpga_cpu_reset), -
>  #ifdef SMP
>   PLATFORMMETHOD(platform_mp_setmaxid,
> socfpga_mp_setmaxid), PLATFORMMETHOD(platform_mp_start_ap,
> socfpga_mp_start_ap), #endif
> -
>   PLATFORMMETHOD_END,
>  };
> +FDT_PLATFORM_DEF(socfpga, "socfpga", 0, "altr,socfpga-cyclone5",
> 200); 
> -FDT_PLATFORM_DEF(socfpga, "socfpga", 0, "altr,socfpga", 0);
> +static platform_method_t socfpga_a10_methods[] = {
> + PLATFORMMETHOD(platform_devmap_init,
> socfpga_a10_devmap_init),
> + PLATFORMMETHOD(platform_cpu_reset,
> socfpga_a10_cpu_reset), +#ifdef SMP
> + PLATFORMMETHOD(platform_mp_setmaxid,
> socfpga_mp_setmaxid),
> + PLATFORMMETHOD(platform_mp_start_ap,
> socfpga_a10_mp_start_ap), +#endif
> + PLATFORMMETHOD_END,
> +};
> +FDT_PLATFORM_DEF(socfpga_a10, "socfpga", 0, "altr,socfpga-arria10",
> 200);
> 
> Modified: head/sys/arm/altera/socfpga/socfpga_manager.c
> ==
> --- head/sys/arm/altera/socfpga/socfpga_manager.c Tue Feb 28
> 12:05:58 2017 (r314388) +++
> head/sys/arm/altera/socfpga/socfpga_manager.c Tue Feb 28
> 14:02:16 2017 (r314389) @@ -377,7 +377,7 @@
> 

svn commit: r314389 - in head/sys: arm/altera/socfpga arm/conf boot/fdt/dts/arm

[Ruslan Bukin]

Author: br
Date: Tue Feb 28 14:02:16 2017
New Revision: 314389
URL: https://svnweb.freebsd.org/changeset/base/314389

Log:
  Add support for Intel Arria 10 SoC Development Kit.
  Use standard DTS files for SOCKIT and SOCDK.
  
  Sponsored by: DARPA, AFRL

Added:
  head/sys/arm/conf/SOCDK   (contents, props changed)
  head/sys/arm/conf/SOCFPGA   (contents, props changed)
  head/sys/boot/fdt/dts/arm/socfpga_arria10_socdk_sdmmc.dts   (contents, props 
changed)
  head/sys/boot/fdt/dts/arm/socfpga_cyclone5_sockit_beri_sdmmc.dts   (contents, 
props changed)
  head/sys/boot/fdt/dts/arm/socfpga_cyclone5_sockit_sdmmc.dts   (contents, 
props changed)
Deleted:
  head/sys/arm/conf/SOCKIT.common
  head/sys/boot/fdt/dts/arm/socfpga-sockit-beri.dts
  head/sys/boot/fdt/dts/arm/socfpga-sockit.dts
  head/sys/boot/fdt/dts/arm/socfpga.dtsi
Modified:
  head/sys/arm/altera/socfpga/socfpga_machdep.c
  head/sys/arm/altera/socfpga/socfpga_manager.c
  head/sys/arm/altera/socfpga/socfpga_mp.c
  head/sys/arm/altera/socfpga/socfpga_mp.h
  head/sys/arm/altera/socfpga/socfpga_rstmgr.c
  head/sys/arm/altera/socfpga/socfpga_rstmgr.h
  head/sys/arm/conf/SOCKIT
  head/sys/arm/conf/SOCKIT-BERI

Modified: head/sys/arm/altera/socfpga/socfpga_machdep.c
==
--- head/sys/arm/altera/socfpga/socfpga_machdep.c   Tue Feb 28 12:05:58 
2017(r314388)
+++ head/sys/arm/altera/socfpga/socfpga_machdep.c   Tue Feb 28 14:02:16 
2017(r314389)
@@ -1,5 +1,5 @@
 /*-
- * Copyright (c) 2014 Ruslan Bukin 
+ * Copyright (c) 2014-2017 Ruslan Bukin 
  * All rights reserved.
  *
  * This software was developed by SRI International and the University of
@@ -83,24 +83,43 @@ socfpga_devmap_init(platform_t plat)
return (0);
 }
 
+static int
+socfpga_a10_devmap_init(platform_t plat)
+{
+
+   /* UART */
+   devmap_add_entry(0xffc0, 0x10);
+
+   /* USB OTG */
+   devmap_add_entry(0xffb0, 0x10);
+
+   /* dwmmc */
+   devmap_add_entry(0xff80, 0x10);
+
+   /* scu */
+   devmap_add_entry(0xfff0, 0x10);
+
+   return (0);
+}
+
 static void
-socfpga_cpu_reset(platform_t plat)
+_socfpga_cpu_reset(platform_t plat, uint32_t reg)
 {
uint32_t paddr;
bus_addr_t vaddr;
phandle_t node;
 
-   if (rstmgr_warmreset() == 0)
+   if (rstmgr_warmreset(reg) == 0)
goto end;
 
-   node = OF_finddevice("rstmgr");
+   node = OF_finddevice("/soc/rstmgr");
if (node == -1)
goto end;
 
if ((OF_getencprop(node, "reg", , sizeof(paddr))) > 0) {
if (bus_space_map(fdtbus_bs_tag, paddr, 0x8, 0, ) == 0) {
bus_space_write_4(fdtbus_bs_tag, vaddr,
-   RSTMGR_CTRL, CTRL_SWWARMRSTREQ);
+   reg, CTRL_SWWARMRSTREQ);
}
}
 
@@ -108,16 +127,38 @@ end:
while (1);
 }
 
+static void
+socfpga_cpu_reset(platform_t plat)
+{
+
+   _socfpga_cpu_reset(plat, RSTMGR_CTRL);
+}
+
+static void
+socfpga_a10_cpu_reset(platform_t plat)
+{
+
+   _socfpga_cpu_reset(plat, RSTMGR_A10_CTRL);
+}
+
 static platform_method_t socfpga_methods[] = {
PLATFORMMETHOD(platform_devmap_init,socfpga_devmap_init),
PLATFORMMETHOD(platform_cpu_reset,  socfpga_cpu_reset),
-
 #ifdef SMP
PLATFORMMETHOD(platform_mp_setmaxid,socfpga_mp_setmaxid),
PLATFORMMETHOD(platform_mp_start_ap,socfpga_mp_start_ap),
 #endif
-
PLATFORMMETHOD_END,
 };
+FDT_PLATFORM_DEF(socfpga, "socfpga", 0, "altr,socfpga-cyclone5", 200);
 
-FDT_PLATFORM_DEF(socfpga, "socfpga", 0, "altr,socfpga", 0);
+static platform_method_t socfpga_a10_methods[] = {
+   PLATFORMMETHOD(platform_devmap_init,socfpga_a10_devmap_init),
+   PLATFORMMETHOD(platform_cpu_reset,  socfpga_a10_cpu_reset),
+#ifdef SMP
+   PLATFORMMETHOD(platform_mp_setmaxid,socfpga_mp_setmaxid),
+   PLATFORMMETHOD(platform_mp_start_ap,socfpga_a10_mp_start_ap),
+#endif
+   PLATFORMMETHOD_END,
+};
+FDT_PLATFORM_DEF(socfpga_a10, "socfpga", 0, "altr,socfpga-arria10", 200);

Modified: head/sys/arm/altera/socfpga/socfpga_manager.c
==
--- head/sys/arm/altera/socfpga/socfpga_manager.c   Tue Feb 28 12:05:58 
2017(r314388)
+++ head/sys/arm/altera/socfpga/socfpga_manager.c   Tue Feb 28 14:02:16 
2017(r314389)
@@ -377,7 +377,7 @@ fpgamgr_probe(device_t dev)
if (!ofw_bus_status_okay(dev))
return (ENXIO);
 
-   if (!ofw_bus_is_compatible(dev, "altr,fpga-mgr"))
+   if (!ofw_bus_is_compatible(dev, "altr,socfpga-fpga-mgr"))
return (ENXIO);
 
device_set_desc(dev, "FPGA Manager");

Modified: head/sys/arm/altera/socfpga/socfpga_mp.c