On Wed, Jan 16, 2013 at 01:38:01PM +1100, Darren Tucker wrote:
On Mon, Jan 14, 2013 at 10:10:55PM +1100, Darren Tucker wrote:
On my ALIX, it increase the IP routing throughput from 80Mbit/s to
85Mbit/s while reducing the interrupt CPU usage from 99% to 80%.
It turns out that due to an
On Thu, Jan 17, 2013 at 09:34:32PM +1100, Darren Tucker wrote:
OK, here's another diff which does seem to help. It seems that there's
two different bits in the TX descriptor that control interrupts. Quoting
from the VT6105M spec:
Thanks to Mark Patruck for noticing that the previous patch
On Fri, Jan 18, 2013 at 09:00:25AM +1100, Darren Tucker wrote:
Thanks to Mark Patruck for noticing that the previous patch didn't
actually help, due to a bug I introduced in a last minute obviously
correct clean up.
The turd polishing continues unabated. This adds the interrupt disable
bit to
Darren Tucker [dtuc...@zip.com.au] wrote:
On Fri, Jan 18, 2013 at 09:00:25AM +1100, Darren Tucker wrote:
Thanks to Mark Patruck for noticing that the previous patch didn't
actually help, due to a bug I introduced in a last minute obviously
correct clean up.
The turd polishing continues
On Fri, Jan 18, 2013 at 01:09:50PM +1100, Darren Tucker wrote:
The turd polishing continues unabated.
and continues to continue. This adds a quirk to frob the
interrupt-disable bit for VT6105M only.
After checking all of the spec sheets that I can find, I found the TX
interrupt disable bit
On Mon, Jan 14, 2013 at 10:10:55PM +1100, Darren Tucker wrote:
On my ALIX, it increase the IP routing throughput from 80Mbit/s to
85Mbit/s while reducing the interrupt CPU usage from 99% to 80%.
It turns out that due to an error on my part, most of this improvment
was due to one of the test
Hi all.
This patch below reduces the number of interrupts on the transmit side
of vr(4). Currently we set the TX competion interrupt bit on each
outbound packet. This patch changes it to only set the interrupt bit on
the last packet enqueued. (One thing of note is that the interrupt bit
is set
2013/1/14 Darren Tucker dtuc...@zip.com.au:
Testing on any VIA Rhine chips would be appreciated (especially ones
that are not 6105M like my ALIX).
Hi, nothing conclusive on VIA VT6107 (dmesg: vr0 at pci0 dev 10
function 0 VIA RhineII-2 rev 0x8d: irq 15, address
00:16:35:06:af:eb).
current
Micha?? Markowski [markows...@gmail.com] wrote:
2013/1/14 Darren Tucker dtuc...@zip.com.au:
Testing on any VIA Rhine chips would be appreciated (especially ones
that are not 6105M like my ALIX).
Hi, nothing conclusive on VIA VT6107 (dmesg: vr0 at pci0 dev 10
function 0 VIA RhineII-2 rev
On 2013/01/14 14:03, Chris Cappuccio wrote:
Micha?? Markowski [markows...@gmail.com] wrote:
2013/1/14 Darren Tucker dtuc...@zip.com.au:
Testing on any VIA Rhine chips would be appreciated (especially ones
that are not 6105M like my ALIX).
Hi, nothing conclusive on VIA VT6107 (dmesg:
2013/1/14 Chris Cappuccio ch...@nmedia.net:
This will only affect TX direction interrupts. Can you try and generate a
stream
of UDP traffic at full rate with a program like iperf to test just TX?
Those numbers are from `iperf -c a -t 100 -i 10` on vr machine.
Iperf man page says: user must
Micha?? Markowski [markows...@gmail.com] wrote:
2013/1/14 Chris Cappuccio ch...@nmedia.net:
This will only affect TX direction interrupts. Can you try and generate a
stream
of UDP traffic at full rate with a program like iperf to test just TX?
Those numbers are from `iperf -c a -t 100
On Mon, Jan 14, 2013 at 10:10:55PM +1100, Darren Tucker wrote:
This patch below reduces the number of interrupts on the transmit side
of vr(4). Currently we set the TX competion interrupt bit on each
outbound packet. This patch changes it to only set the interrupt bit on
the last packet
2013/1/15 Chris Cappuccio ch...@nmedia.net:
Well your numbers clearly show almost no difference. But TCP might not
be the best way to test due to the regular ack reply.
Ok, -current kernel:
$ int1=`vmstat -i | awk '$1 ~ /vr0/ {print $2}'`; tcpbench -u -t 100
-r 1 r; int2=`vmstat -i | awk
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