On 14 October 2016 at 12:40, Mike Belopuhov wrote:
> On Fri, Oct 14, 2016 at 07:58 +0200, Claudio Jeker wrote:
>> It is time to put the nasty comment from rl(4) into em(4) and ix(4).
>> Everybody knew how bad realtek was but thinks Intel nics are good. The
>> truth is that
On Fri, Oct 14, 2016 at 15:48 +1000, David Gwynne wrote:
> this adds a pool backend for MCLGETI thats 2k+2 bytes in size, which
> can be used on some very common nics that have annoying constraints
> on their rx descriptors.
>
> this in turn simplifies the code in those drivers and lets them
>
On Fri, Oct 14, 2016 at 07:58 +0200, Claudio Jeker wrote:
> It is time to put the nasty comment from rl(4) into em(4) and ix(4).
> Everybody knew how bad realtek was but thinks Intel nics are good. The
> truth is that modern Intel nic are as bad as the cheepest and crapiest
> 10/100 Mbps Ethernet
> On 14 Oct 2016, at 16:17, Ted Unangst wrote:
>
> David Gwynne wrote:
>> this adds a pool backend for MCLGETI thats 2k+2 bytes in size, which
>> can be used on some very common nics that have annoying constraints
>> on their rx descriptors.
>>
>> this in turn simplifies
David Gwynne wrote:
> this adds a pool backend for MCLGETI thats 2k+2 bytes in size, which
> can be used on some very common nics that have annoying constraints
> on their rx descriptors.
>
> this in turn simplifies the code in those drivers and lets them
> always operate on ETHER_ALIGN
It is time to put the nasty comment from rl(4) into em(4) and ix(4).
Everybody knew how bad realtek was but thinks Intel nics are good. The
truth is that modern Intel nic are as bad as the cheepest and crapiest
10/100 Mbps Ethernet chips from the last millenium.
--
:wq Claudio
On Fri, Oct 14,
this adds a pool backend for MCLGETI thats 2k+2 bytes in size, which
can be used on some very common nics that have annoying constraints
on their rx descriptors.
this in turn simplifies the code in those drivers and lets them
always operate on ETHER_ALIGN boundaries.
the pool is cheap, pages