the
differences between 14 bits and 16 bits ADC are.
Regards
Li Ang / BI7LNQ
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Hi Guys
I have just bought 2 kinds of PRS10 connectors on taobao.com. (PCB type and
cable type, refer to the attached photo). It is about 8$ each(the D-SUB +
center RF part). If you are looking for it, I can send you the link off the
list.
Yours
Li Ang / BI7LNQ
Hi
I think the purpose is to get high input impedance for high frequency signal.
The input impedance of comparator is high at low frequency range only.
Li Ang / BI7LNQ
---Original---
From: "Attila Kinali"<att...@kinali.ch>
Date: 2017/6/20 15:20:44
To: "Discussion of preci
observation satellite XPNAV-1.
5. detector intro: wolter-i focused x-ray detector. energy range: 0.5-10keV.
view : 2ω=15'. geometric area: 30cm2@1.5keV. Time resolution:<=1.5us. Energy
resolution: <=180eV@5.9keV.
-- Original --
From: "Li Ang"
and related information.
Regards
Li Ang / BI7LNQ
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Hi
I am wondering if anyone tried to put a Rb unit into a vacuum container. And
how much the performance is improved? Someone told me that's why the Rb clocks
are more stable than Cs clocks on the GPS satellites.
LiAng
---Original---
From: "Bob Camp"
Date: 2017/1/17 21:20:23
To:
Hi
Thanks for the info. The fpga baesed TDC is something I am interested in.
However, I am a beginner of fpga programming. Maybe next year I will spend
sometime study this project. VHDL is quite difficult for a C programmer :(.
Regards
Li Ang
BI7LNQ
---Original---
From: "Attila Kinali
a/20161209/freqcnt_v6_20161209_3corneredhat.png
TODO list:
1) web based interface, calculate and show *DEVs with javascript on Chrome
browser
2) front end experiments
Regards
Li Ang / BI7LNQ
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Great job.
I am doing a similar project too.
I've just sent gerber/pos/bom files to the PCB company. 3 tdc7200s are
used on my board to support the 3-corner-hat measurement.
Regards
Li Ang
---Original---
From: "John Ackermann N8UR"<j...@febo.com>
Date: 2016/11/25 22:57:33
oscillators.
I also told him to keep the leaky one running for days and see what's going
on. If it goes to normal, price will x2 or more.
regards
Li Ang
---Original---
From: "Tom Van Baak"<t...@leapsecond.com>
Date: 2016/11/13 19:34:59
To: "Discussion of preci
HI
I just came back from another 5071a seller.
#1-#3 fatal error: max emult.
#4 fatal error: overcureent (about 80uA)
I put the tube from #1 to #4. #4 became a "max emult" one.
I think the tube #1 is really dead and the circuit of #4 is functional.
Since the ion pump current was dropping
ges of a DDS-based GPSDO instead of the traditional DAC/EFC
method.
/tvb
- Original Message -
From: Li Ang
To: Tom Van Baak ; Discussion of precise time and frequency measurement
Sent: Tuesday, November 08, 2016 10:48 PM
Subject: Re: [time-nuts] 5071A with ATTENTION flashing
Hi Tom
I have
According to the Log, "CBT Oven Err: -9.55 C" might be something wrong.
However, I can't find the correct range in the manual. Does anyone have the
information about this parameter?
Regards
Li Ang
-- Original --
From: "Li Ang";<379
Hi Tom
I have collected the log from it. Log level is service. The 9.2G pll pass the
test today. The log during the power-up process is also included.
Regards
Li Ang / BI7LNQ
-
scpi >
MJD0 02:02:18
CBT ID: 3128A00642(H)
Status summary: Fa
Hi Tom
Thanks for the info. I think I should pay a visit to this 5071a again. There
are 5 more 5071a 200km away, I need to visit them next week. :)
regards
Li Ang / BI7LNQ
---Original---
From: "Tom Van Baak"<t...@leapsecond.com>
Date: 2016/11/4 00:42:46
To: "Discu
Hi
Welcome to Shenzhen. As far as I know there is no market that you can see
pile of OCXO. They were taken off from equipments, and the process is done in
the Qingyuan or Shanwei city Guangdong province. The seller might be in
Shenzhen, but the source is in Qingyuan/Shanwei. These city have
Hi
Today I met one HP 5071A with option 001 at one secondhand equipment company.
This one can not enter CONTINUOUS OPERATION status, the ATTENTION led flashes.
There is a "Low cs signal with max Emult" error in the log. I have run the
self-test, and it stopped at "9.2GHz PLL test 10.3v". I
Hi
I got 5 samples of TDC7200 from TI a few months ago. I have made a board to
test it with TDC-GP22 from ACAM. Actually it's a new board of my frequency
counter. The CPU system is changed from MCU to a OrangePi board. The digital
part is still a Cyclone 4 FPGA.
Verilog:
Hi
Thanks to all the information here. I can put more items to my experiment
list.
Regads
Li Ang, BI7LNQ
2016-01-11 11:28 GMT+08:00 Magnus Danielson <mag...@rubidium.dyndns.org>:
> Moin,
>
> On 01/10/2016 07:56 PM, Attila Kinali wrote:
>
>> On Sun, 10 Jan 2016
Hi Bob,
In some article, I see people use a D-flipflop to sample the input
signal with reference clock. When you want implement a mixer what's the
difference between D-flipflop and XOR gate? Acorrding to my understanding,
to multiply 1bit with another, I should use an AND gate, right?
When
, it might vary few ms.
2) Does any one have the test data of 12 digit/s counter when DUT=REF?
I want to know the gap between mine and a commercial counter.
Thanks
Li Ang
2015-02-27 4:30 GMT+08:00 Charles Steinmetz csteinm...@yandex.com:
Magnus wrote:
A bit of hysteresis can help to avoid
will evaluate with
it.
2015-02-25 0:02 GMT+08:00 Attila Kinali att...@kinali.ch:
On Tue, 24 Feb 2015 14:43:10 +0800
Li Ang lll...@gmail.com wrote:
I saw people talking about using 74AC to square the signal, what's
the
difference between 74LVC and 74AC? 74AC is not easy to get
talking about using 74AC to square the signal, what's the
difference between 74LVC and 74AC? 74AC is not easy to get.
Thanks
Li Ang
2015-02-24 5:36 GMT+08:00 Magnus Danielson mag...@rubidium.dyndns.org:
Dear Li Ang,
Nice to have you back reporting on your progress!
Now, you have some pretty
Hi,
I'm back. I have been testing my new borad for days.
Compared to previous version, this board makes the PCB track of signals far
from each other and replaces LDO for TDC with LP5907.
CH_A: simple resistor bias and ac couple front end, CH_B:
CH_A+MC100LVELT22 LVPECL , CH_C:
Li Ang
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Hi
I have a question about the GPS antenna. Since the GPS signal strength on
the ground is about 20db lower than the thermal noise, does the gain of
antenna matter?
2015-01-16 7:01 GMT+08:00 Björn Gabrielsson b...@lysator.liu.se:
Magnus,
If civilian receivers where to implement L2C and L5
Magnus Danielson magnus@... writes:
Which display is it?
Hi Mangus,
I do not know the model name, but I found the same one on ebay (key word
2.2 TFT SPI). It's a SPI screen, so it shows things quite slow. However,
320x240 resolution is good to display a lot of slow changing stuffs. I use
Tom Van Baak tvb@... writes:
Just use:
ref_delta = ref_curr - ref_prev;
sig_delta = sig_curr - sig_prev;
Not only is it much simpler but it also works in every case (your code
would fail whenever curr equals prev).
Here's a test program in case you don't believe me:
Hi
Just now, I changed the way to calculate frequency and get a better
ADEV chart.
http://www.qsl.net/b/bi7lnq/freqcntv4/test/20150114/0114.gif
http://www.qsl.net/b/bi7lnq/freqcntv4/test/20150114/newway.tim
http://www.qsl.net/b/bi7lnq/freqcntv4/test/20150114/oldway.tim
Thanks to John
is there now. There is something
need to figure out.
Thanks
Li Ang
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= 0x,
Register_4 = 0x2000,
Register_5 = 0 27,
Register_6 = 1 12;
2015-01-06 7:33 GMT+08:00 Li Ang lll...@gmail.com:
Hi Bob,
There are 2 oscillator on board, one 8MHz for MCU one 125MHz for FPGA.
I've took it down from the board, and changed MCU to use internal RC
oscillator
Hi Neil
Just now, I disconnected TPS79333 from board and used LR6 battery for
the analog part of TDC. The result does not show improvement. So I think
LDO might not be the primary noise contributor.
Thanks for the suggestion.
2015-01-03 22:01 GMT+08:00 Neil Schroeder gign...@gmail.com:
I
need new board to
verify. I have got some BFT92 and looking for pin-pin compatible low
noise LDO to play with.
Thanks
Li Ang
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Hi Magnus
You are right, I could compensate it in the software. I've tried that.
The software sets sig=ref=10MHz and measures start-to-stop time t1. Then,
it sets sig=ref=5MHz and measures time t2. With t1 t2, I could get the
time difference between the start path and the stop path. Repeat it
Hi Bob,
Actually, I dont want to ask my colledge for help. Everytime ,for each
guy I ask for help, I need expain the entire system and principle of a
frequency counter to him. They just keep asking questions instead of
answering mine. :(
The 2 MV89As are powered by the same power supply
4:35 GMT+08:00 Bob Camp kb...@n1k.org:
Hi
On Dec 28, 2014, at 9:19 AM, Li Ang lll...@gmail.com wrote:
Hi Bob,
I did some test according to your suggestions. DUT is a symmetricom x72
rb oscillator. Also, I've tried signal generator as the DUT. RS SMY01 is
not as good as HP8662A
kb...@n1k.org:
Hi
On Dec 28, 2014, at 9:19 AM, Li Ang lll...@gmail.com wrote:
Hi Bob,
I did some test according to your suggestions. DUT is a symmetricom x72
rb oscillator. Also, I've tried signal generator as the DUT. RS SMY01 is
not as good as HP8662A but that the best I've got
compensation network. Its a fabulous part for a sensitive
application like yours.
I'm hoping I am right in assuming that the noise performance of the LDOs
is
a concern, and don't mean to even dare suggest that you've done anything
but a great job! :-)
NS
On Sat, Dec 27, 2014 at 5:34 AM, Li Ang lll
. But to assist you further,
please find a spread-sheet of it attached.
Notice that I scaled the values by 100 ns before further processing.
Cheers,
Magnus
On 12/31/2014 01:03 PM, Li Ang wrote:
Hi Magnus,
I'm not familar with error analysis and statistics, can you tell me
how
to calculate
,
Magnus
On 12/29/2014 01:55 PM, Li Ang wrote:
Hi Magnus,
The unit of these data is not ns but reference clock cycles (100ns).
TDC_GP22 measures the time between the edge of tdc_start and
tdc_stop1, then it measures the reference clock automaticly. The result
you
get from it is the ratio
. They have a nice looking unit, but are still trying to
figure out the bugs and finish up the software …
Bob
On Dec 28, 2014, at 6:19 PM, Li Ang lll...@gmail.com wrote:
Hi
This unit is done by BG7TBL. In his store on taobao.com, there is a
adev
chart. Please refrer to this link
http
2,243 ps
RMS jitter, which isn't all that bad. Yes, it will spread out to that 11 ps
peak-to-peak jitter, but it is to be expected.
It's pretty respectable for a home-built.
Cheers,
Magnus
On 12/28/2014 03:19 PM, Li Ang wrote:
Hi Bob,
I did some test according to your suggestions
Hi
This unit is done by BG7TBL. In his store on taobao.com, there is a adev
chart. Please refrer to this link
http://item.taobao.com/item.htm?spm=a1z10.3.w4002-1278071728.49.XHJlQLid=42336500072
2014-12-29 1:56 GMT+08:00 Dan Rae dan...@verizon.net:
On 12/28/2014 7:25 AM, David Smith
. Once that is
done, build the input channel(s) on their own board(s). They will need
their own regulators to keep noise down (regulators are cheap). You can
optimize the input channel circuits as part of a separate project.
Bob
On Dec 26, 2014, at 8:21 AM, Li Ang lll...@gmail.com wrote
Hi Charles,
In my circuit, the VCC is 5v. I've noticed my bias and emitter resistor
is something need to be changed. I will play with the resistors and see if
it improves. Thanks.
2014-12-27 6:42 GMT+08:00 Charles Steinmetz csteinm...@yandex.com:
Li Ang wrote:
RF pnp transistor is harder
). They will need
their own regulators to keep noise down (regulators are cheap). You can
optimize the input channel circuits as part of a separate project.
Bob
On Dec 26, 2014, at 8:21 AM, Li Ang lll...@gmail.com wrote:
Hi
Thanks for the suggestion. I will do some experiments with the front
* of different ways to do the same sort of thing. I
would not go overboard doing this with complicated circuits. You simply
want a way to figure out what the input circuits are doing.
Have Fun!
Bob
On Dec 24, 2014, at 11:19 AM, Li Ang lll...@gmail.com wrote:
http://www.qsl.net/bi7lnq
GMT+08:00 Charles Steinmetz csteinm...@yandex.com:
In reply to Li Ang, Bruce wrote:
The CLK1 input circuit produces an output incompatible with the 3.3V CMOS
device it drives.A pair of pnp transistors in an otherwise similar circuit
is capable of producing a 3.3V CMOS compatible output
http://www.qsl.net/bi7lnq/freqcnt_bi7lnq_v4.pdf this is my current board.
I'm not a hardware guy, feel free to correct my mistakes. :)
http://assets.fluke.com/manuals/6690smeng.pdf schematic of cnt90
aka pm6690
Happy holidays
Li Ang
to ground
test instruments
1) HP6622A as power supply
2) FE5650 rb as reference
3) PRS10 rb as DUT
Li Ang
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Thanks Tom,
The front end is still 75ALS176, but I put another simple transistor
circuit from wenzel to to compare the performance.
http://www.wenzel.com/wp-content/uploads/diffsqr.gif
2014-12-12 17:04 GMT+08:00, Tom Van Baak t...@leapsecond.com:
This large posting is from Li Ang.
/tvb
= 0;
}
}
2014-12-12 21:18 GMT+08:00 Bob Camp kb...@n1k.org:
HI
On Dec 12, 2014, at 4:04 AM, Tom Van Baak t...@leapsecond.com wrote:
This large posting is from Li Ang.
/tvb
- Original Message -
From: Li Ang
To: Discussion of precise time and frequency measurement
independent sources (one
reference and the other as input)?
I’m guessing that the answer is yes in both cases.
Bob
On Dec 12, 2014, at 10:40 AM, Li Ang lll...@gmail.com wrote:
Hi Bob,
The job done by linear regression is to reduce the uncertainty. This
counter is designed to use
-stop1= -6
stop1-start= 2013, stop2-stop1= -6
stop1-start= 2016, stop2-stop1= -2
stop1-start= 1987, stop2-stop1= -2
stop1-start= 2062, stop2-stop1= -6
stop1-start= 2021, stop2-stop1= -5
2014-11-29 1:41 GMT+08:00 Bob Camp kb...@n1k.org:
Hi
On Nov 28, 2014, at 10:14 AM, Li Ang lll
Hi
Thanks for the great article.
I did a little test just now. To measure the refclk of itself. And this
is the result(I kept 10 digits of the fraction part):
### Frequency Counter startup ###
gate=1s #=8985 freq=10.02
gate=1s #=9038 freq=10.01
gate=1s #=9039
I did a little calculation and it's a 10 digits counter.
log(10,000,000,005) = 10.
There is still a big gap between this one and 53132A :(
For 53132A, the time resolution is 150ps, which I think is 10digits/s with
interpolator. According to the schematics the only difference between
53132A
1) What frequency is the crystal at? (can you drive the chip from an OCXO?)
I'm clking this chip with the refclk/2=5Mhz, which is done by cpld.
something like always @(posedge refclk) tdc_clk = ~tdc_clk; Not sure if
it's noisy.
2) Is there more bypassing on the circuit than shown? (If not, add
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