OK, I'll try to rewrite and test that section.
On Fri, Mar 1, 2013 at 2:28 PM, Javier Serrano <
javier.serrano.par...@gmail.com> wrote:
> On Fri, Mar 1, 2013 at 10:40 AM, Azelio Boriani
> wrote:
> > The metastability from the PPS latching the counter is indeed a problem:
> > rarely do I see out
On Fri, Mar 1, 2013 at 10:40 AM, Azelio Boriani
wrote:
> The metastability from the PPS latching the counter is indeed a problem:
> rarely do I see out of range numbers and have to filter them out.
You cannot filter them out. One time you will have bit 10 wrong and
you will be able to detect that
t...@leapsecond.com said:
> Consider also using two identical 24-bit counters. ...
That doesn't help solve the metastability issue.
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Sent: Friday, March 01, 2013 1:40 AM
Subject: Re: [time-nuts] GPSDO with a RaspberryPi
> Javier:
> CSelect after PPS -> yes, the CSelect must occur after the PPS has loaded
> new data. This is managed using the GPS serial NMEA output. The NMEA
> strings are output after the P
Javier:
CSelect after PPS -> yes, the CSelect must occur after the PPS has loaded
new data. This is managed using the GPS serial NMEA output. The NMEA
strings are output after the PPS, timing the sequence of events.
Two registers and data transfer-> well, I have two registers: the data gets
transfe
On Fri, Mar 1, 2013 at 12:47 AM, Azelio Boriani
wrote:
> Javier:
> the 24bit counter is clocked only by the 10MHz and is running continuously,
> the PPS is the most important signal. The LSClock is the clock for the
> latch: this latch has to be clocked to shift out its content serially and
> has
Javier:
the 24bit counter is clocked only by the 10MHz and is running continuously,
the PPS is the most important signal. The LSClock is the clock for the
latch: this latch has to be clocked to shift out its content serially and
has to be loaded with the PPS from the GPS (PPSReference). I see no ot
On Thu, Feb 28, 2013 at 1:26 AM, Azelio Boriani
wrote:
> First try at a simple GPSDO for the RaspberryPi. See here:
> http://www.c-c-i.com/exchange/for the file PiAutoTIC1.zip
Nice project Azelio! Here are a few comments after a cursory look at the VHDL:
- Gated clocks (i.e. LSClock) are in
The 24bit counter counts up to 999 then is reset to 0 to get a PPS out
of a 10MHz clock. The most significant bit is high from 0x80 to
0x98967F, so that you have a 161.1392ms wide high pulse when driving the
PPS output with the MSB.
On Thu, Feb 28, 2013 at 1:28 PM, Herbert Poetzl wrote:
>
On Thu, Feb 28, 2013 at 01:26:17AM +0100, Azelio Boriani wrote:
> First try at a simple GPSDO for the RaspberryPi. See here:
> http://www.c-c-i.com/exchange/ for the file PiAutoTIC1.zip
> Thanks to Bob Smither for his file exchange site.
Pardon my ignorance, but where does the 161ms PPS length
com
First try at a simple GPSDO for the RaspberryPi. See here:
http://www.c-c-i.com/exchange/for the file PiAutoTIC1.zip
Thanks to Bob Smither for his file exchange site.
This project is completely open-source, VHDL and C sources are available.
Can be implemented also with any uP but the C source m
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