Javier: the 24bit counter is clocked only by the 10MHz and is running continuously, the PPS is the most important signal. The LSClock is the clock for the latch: this latch has to be clocked to shift out its content serially and has to be loaded with the PPS from the GPS (PPSReference). I see no other way to deal with this other than selecting the two clock sources for this latch/shifter. When the chip select (CSelect) line is high, the PPS is selected as a clock, when the CSelect is low (SPI trying to read) the SClockIN is selected as a clock. I know it is not a good practice to use gated clocks but at times it seems there is no way out and the CPLD is only 64 cells wide...
On Thu, Feb 28, 2013 at 5:34 PM, Javier Serrano < [email protected]> wrote: > On Thu, Feb 28, 2013 at 1:26 AM, Azelio Boriani > <[email protected]> wrote: > > First try at a simple GPSDO for the RaspberryPi. See here: > > http://www.c-c-i.com/exchange/ for the file PiAutoTIC1.zip > > Nice project Azelio! Here are a few comments after a cursory look at the > VHDL: > > - Gated clocks (i.e. LSClock) are in general not a good idea. You can > split things in two: the serial link clocked by SClockIN and the > getting hold of the value of the counter in a separate process clocked > by PPSReference (or for a better option, see below). > > - In any case you will have to deal with metastability properly [1]. > Now you're clocking the 24-bit output of the counter (which is in the > Clk10MHz clock domain) with the PPSReference signal (after gates). It > would be better to synchronize the PPSReference input to Clk10MHz with > three FFs and a synchronous edge detector (i.e. PPSRising <= PPSRefd2 > and not PPSRefd3 inside a CLK10MHz clocked process). Then you can look > at the value of the counter when that 1-tick-wide Clk10MHz-synchronous > signal (PPSRising) goes to '1'. > > - The CMDReg process is another place where metastability can occur in > the current design. > > - Once you have reduced the number of clocks in your design you will > need to watch carefully every place where clock domains are crossed > and put synchronizers [1] in there. > > Cheers, > > Javier > > [1] I uploaded some useful references to http://www.ohwr.org/documents/22 > _______________________________________________ > time-nuts mailing list -- [email protected] > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
