From: time-nuts [mailto:time-nuts-boun...@febo.com] On Behalf Of Attila
>>>> Kinali
>>>> Sent: Thursday, August 27, 2015 4:51 PM
>>>> To: Discussion of precise time and frequency measurement
>>>> Subject: Re: [time-nuts] Chinese GPSDO 10 MHz error
>>>&
Hi
At the most basic level:
FLL is frequency locked. Consider a lock system driven by an FM discriminator.
(That’s
how the idea originally was done.) The output of the detector is a voltage
proportional to the
frequency error. With a simple loop (gain only / no integrator) you have a
static
[mailto:time-nuts-boun...@febo.com] On Behalf Of Attila
>>> Kinali
>>> Sent: Thursday, August 27, 2015 4:51 PM
>>> To: Discussion of precise time and frequency measurement
>>> Subject: Re: [time-nuts] Chinese GPSDO 10 MHz error
>>>
>>> On T
Since I have not found a strong definition for the FLL, I assumed: if
PLL= zero phase error (and so zero frequency error) the FLL= same
frequency, random phase. The XOR with RC is a perfect fit for this:
same frequency all the time but phase determined by the EFC needed to
have that frequency. The
it is a bit more complicated FLL need circuit which is sensitive to
frequency difference, it looks always, PLL need a phase detector and
has a capture range, which is depend mainly on the bandwidth of the loop
filter
there are combined phase /frequency detectors, which are sequential
circuits
done.
Bob
>
> Bob
>
>>>> -Original Message-
>>>> From: time-nuts [mailto:time-nuts-boun...@febo.com] On Behalf Of Tim
>>>> Shoppa
>>>> Sent: Wednesday, August 26, 2015 5:18 PM
>>>> To: Discussion of precise time and fr
On Thu, 27 Aug 2015 17:19:34 +0200
Azelio Boriani wrote:
> The simplest form of a frequency locked loop is the XOR gate, when the
> driving signals are 50% square waves. To achieve lock, the phase
> difference will be proportional to the voltage needed to the VCO to
> generate the desired frequen
GHz?
>
> Bob
>
>>>> -Original Message-
>>>> From: time-nuts [mailto:time-nuts-boun...@febo.com] On Behalf Of Tim
>>>> Shoppa
>>>> Sent: Wednesday, August 26, 2015 5:18 PM
>>>> To: Discussion of precise time and frequency measurem
11:55 PM
To: 'Discussion of precise time and frequency measurement'
Subject: Re: [time-nuts] Chinese GPSDO 10 MHz error
So how does a frequency lock work? How is it implemented? Can someone sketch a
schematic?
And what equipment or technique is used to measure a 2hz error at 10
;> -Original Message-
> >>> From: time-nuts [mailto:time-nuts-boun...@febo.com] On Behalf Of Tim
> >>> Shoppa
> >>> Sent: Wednesday, August 26, 2015 5:18 PM
> >>> To: Discussion of precise time and frequency measurement
> >>> Sub
gt;>> Shoppa
>>> Sent: Wednesday, August 26, 2015 5:18 PM
>>> To: Discussion of precise time and frequency measurement
>>> Subject: Re: [time-nuts] Chinese GPSDO 10 MHz error
>>>
>>> Full KE5FX evaluation of BG7TBL GPSDO here:
>>> http:/
Hi
Further investigation by list members in China came back with the information
that this particular
design is indeed a FLL. The error is considered “acceptable” by the designer.
This is not the case
on the various CDMA oriented GPSDO’s we typically play with in the US and
Europe. All of thos
Full KE5FX evaluation of BG7TBL GPSDO here: http://www.ke5fx.com/gpscomp.htm
I'm wondering out loud if it might, like many hobbyist GPSDO's, be
frequency-locked rather than phase-locked and thus susceptible to
last-digit-counter bobble in some long-averaging counter.
Tim N3QE
On Wed, Aug 26, 201
Hi,
On the EEVBLOG (http://www.eevblog.com/forum/index.php)
They mention that the "2014-11-06"version GPSDO that was “most extensively
tested, so far (by ke5x and others).
(Has a) known bug, outputfrequency is not exactly 10mhz (9,999,999.999,800 Hz).
This translates to ~2hzerror at
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