hau...@keteu.org said:
I am trying to avoid an extra A/D step here, but I have no experience with
it. Post-filter, I am satisfied that a simple one-bit D/A with passive
filtering will get me to 16 bits resolution for the VCXO control, enough for
ppb resolution.
One bit D/As need a filter.
Hi Hal,
I'm familiar with 1-bit D/As and plan to use something a bit more evolved
than the MCU/counter approach. I am already working in an FPGA as that is
absolutely required to deal with the 80-MSPS 16-bit radio data stream.
(This is an SDR project first, a GPSDO project second, or maybe
hau...@keteu.org said:
It was the other end of the PLL I was hoping to get some pointers on.
Specifically, I can implement the dividers and the standard double-flip-flop
PFD, but what best replaces the charge pump in a fully-digital
implementation? I will have down/up signals which are
Hi Mark,
that really is up to you and your skill-set. I don't use FPGA's in products
anymore because they are not field-serviceable generally, expensive,
usually require some sort of recurrent registration of the compiler, the ones
I
like have external program storage so are not easily
Said, would you suggest implementing the dividers and PFD in the FPGA, along
with the digital filtering? Or feeding the FPGA with some version of the
PFD output? I am trying to avoid an extra A/D step here, but I have no
experience with it. Post-filter, I am satisfied that a simple one-bit D/A
Hi Mark,
yes, the PLL is there to remove any tempco of the system and all error
sources etc, so you don't have to individually quantify the errors. That is the
nice thing about loops. You only need a good model if you have to work in
holdover without GPS disciplining.
You will need a
Mark,
typical GPS receivers do not lock their crystal to anything, they just use
a free-running one. Please search the archives for TVB hanging bridges
discussions to get good details on that phenomenon. The Trimble Thunderbolt
is one example of a unit that does lock its oscillator to
Nowadays you can get a great 10MHz OCXO on Ebay for $10, buy a
PLD/FPGA/Micro eval board for less than $30, and add a DAC and some
low-pass filtering
and voltage reference for probably less than $10. So you can do a
complete, high-end double-oven GPSDO for around $50.. Adding the Crystek
-
De : time-nuts [mailto:time-nuts-boun...@febo.com] De la part de Said Jackson
via time-nuts
Envoyé : dimanche 28 septembre 2014 07:50
À : Discussion of precise time and frequency measurement
Cc : time-nuts@febo.com
Objet : Re: [time-nuts] GPS-disciplining an ordinary VCXO?
Mark,
In the analog
Hi
A VCXO (as opposed to a TCVCXO) can have a pretty major temperature
coefficient. The more the oscillator moves as the room temp varies, the wider
your loop needs to be. Exactly how wide depends on a lot of things. Is it a
problem if the radio unlocks when a draft blows in through the open
Envoyé : dimanche 28 septembre 2014 07:50
À : Discussion of precise time and frequency measurement
Cc : time-nuts@febo.com
Objet : Re: [time-nuts] GPS-disciplining an ordinary VCXO?
Mark,
In the analog domain you can probably do a PLL with a 1Hz loop BW.
Using a PLL chip like ADF 4002
: Discussion of precise time and frequency measurement
Cc : time-nuts@febo.com
Objet : Re: [time-nuts] GPS-disciplining an ordinary VCXO?
Mark,
In the analog domain you can probably do a PLL with a 1Hz loop BW.
Using a PLL chip like ADF 4002 or similar. This means all the nasty
noise from
In my quest to learn Verilog and get my hands dirty with
software-defined radio, I'm currently designing a direct-sampling
shortwave receiver. This uses an 80-MSPS ADC, which requires a
low-phase-noise oscillator, e.g. Crystek CVHD-950 or Abracon ABLNO. It
would be nice to have some provision
Mark,
In the analog domain you can probably do a PLL with a 1Hz loop BW. Using a PLL
chip like ADF 4002 or similar. This means all the nasty noise from the NEO will
taint your PN up to 20Hz or more, very significantly close-in. If you don't
care about noise (jitter) below 100Hz then this is
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