In my quest to learn Verilog and get my hands dirty with software-defined radio, I'm currently designing a direct-sampling shortwave receiver. This uses an 80-MSPS ADC, which requires a low-phase-noise oscillator, e.g. Crystek CVHD-950 or Abracon ABLNO. It would be nice to have some provision for locking this oscillator to an external reference, hence my question:
All of the amateur GPSDO designs I've seen are disciplining an OCXO. I understand this is easier because the excellent short-term accuracy of the OCXO means the feedback can run slower, so even a 1 PPS signal can be used. I am wondering what sort of performance could be achieved by disciplining my VCXO directly with a good GPS module. I have a NEO-7N (Ublox) with configurable timepulse up to 10 MHz. Someone mentioned that this is derived from 48 MHz, so jitter is reduced if you pick an integer divisor. That is fine, but I don't have a feel for what other irregularities may be present in the timepulse output, and how they would affect the performance. I also don't know how to go about designing a PLL loop filter. I understand the goal is to marry the long-term GPS stability with the short-term VCXO stability but all I have is a phase-noise plot for the VCXO. How do you know where to split the difference? It is not essential to the larger project, but what I am ideally going for is 1 ppb frequency match between two ends of a radio link, and 1 ppb stability over data symbol times. That is, carrier stability of ~ 1/10 cycle at 10 MHz over one-second symbols. (Channel coherence imposes this limit.) I know the experts here can tell me whether this is impossible, totally doable, or somewhere in between! Thanks, Mark _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
