Sent: 08 June 2015 15:09
To: time-nuts@febo.com
Subject: Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider
On Sun, 07 Jun 2015 11:23:40 +0100, David C. Partridge wrote:
My reading so far of what's been said in this thread is that you might
get good results using a CPLD/FPGA
On Mon, 08 Jun 2015 16:27:26 +0100, David C. Partridge wrote:
I'm up for either ... My thoughts are to try it out on a development
board and if it works, maybe build a few for possible sale, and also
release Gerbers and VHDL files.
Regards,
David Partridge
I have these cheap cards ,
On Sun, 07 Jun 2015 11:23:40 +0100, David C. Partridge wrote:
My reading so far of what's been said in this thread is that you might
get good results using a CPLD/FPGA as a divider but ... .
..
..
..
Thanks again Dave
Is this going to be an open source project, or something you buy ?
CFO
My reading so far of what's been said in this thread is that you might get good
results using a CPLD/FPGA as a divider but ... .
Bruce pointed me to Rubiola's paper
http://rubiola.org/pdf-articles/conference/2013-ifcs-Frequency-dividers.pdf,
and while I'm sure the lambda divider is excellent,
Hi
As always, the real answer is “that depends”.
If you are dividing to 1 pps from 10 MHz, the CPLD or FPGA is a fine answer to
the question. It will give you some cool bells and whistles (like sync and
advance / retard) without adding anything to the budget. If you wish to re-sync
the
Hi
Last time I saw university multi project wafer prices, the cost was around $5K
for a
run on a “not state of the art” fab process. That included absolutely nothing
in the way of design assistance. It was strictly “we fab what you told us to
do”. The
“run date” for the chips was also a bit
rich...@karlquist.com said:
I used a CPLD in a 900 GHz (that's right 900 GHz) optical sampling scope
timebase. It was great because you just write a 17 bit counter in VHDL and
there it is. You don't have to know anything about building digital
hardware any more (40 years of experience
The counter only had to run at ~50 MHz, on account of our
mode locked laser ran at that frequency. I don't remember
what the CPLD was rated at.
Rick
On 6/5/2015 8:19 PM, Hal Murray wrote:
rich...@karlquist.com said:
I used a CPLD in a 900 GHz (that's right 900 GHz) optical sampling scope
Hi
On Jun 5, 2015, at 11:19 PM, Hal Murray hmur...@megapathdsl.net wrote:
rich...@karlquist.com said:
I used a CPLD in a 900 GHz (that's right 900 GHz) optical sampling scope
timebase. It was great because you just write a 17 bit counter in VHDL and
there it is. You don't have to know
Hi
Here’s an example:
http://parts.arrow.com/item/detail/arrow-development-tools/bemicromax10#pg2e
https://www.altera.com/products/fpga/max-series/max-10/overview.highResolutionDisplay.html
There are other outfits that make similar parts that are at least as good. This
is considered a
low end
On Sat, 6 Jun 2015 09:52:11 -0400
Bob Camp kb...@n1k.org wrote:
Was it a simple
counter or was there enable/up/down/load type gating involved?
What would you have done if you needed to run a bit faster?
Bought a faster FPGA or gone to an ASIC.
Could you buy a
faster chip?
I used a CPLD in a 900 GHz (that's right 900 GHz) optical
sampling scope timebase. It was great because you just
write a 17 bit counter in VHDL and there it is. You
don't have to know anything about building digital
hardware any more (40 years of experience wasted).
Nobody cares about look
Thanks Bruce. That is an excellent option.
I did a paper over a decade ago on the jitter and phase noise for Actel
(Now Microsemi) comparing their eX device to the Xilinx CPLD. It was
intended to show the eX device was preferable to the Xilinx CPLD. It makes
a difference as to what device is
Hi
As always, the real answer it “that depends”.
If your objective is wide band phase noise and you want to start from 100 MHz
and get 10 MHz (fig 6 in
the Lamda paper), you can get at least another 6 db with a simple divide by 10
chip than with all the
fancy stuff.
Bob
On Jun 3, 2015,
Is this a sensible thing to consider doing? Or would I be better sticking to
AC/HC/AHC/LVC logic?
Regards,
David Partridge
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Is this a sensible thing to consider doing? Or would I be better sticking to
AC/HC/AHC/LVC logic?
Regards,
David Partridge
Yes, please consider it. I would be very interested in the results.
We measured under 2 ps jitter for the PIC dividers [1] used with the cute
little TADD-2 board
Programmable logic rocks. If you need a 13 bit counter, you can do that. It
is easy to create alarms and special controls.
Jerry
On Jun 2, 2015 2:22 PM, David C. Partridge david.partri...@perdrix.co.uk
wrote:
Is this a sensible thing to consider doing? Or would I be better sticking
to
Hi
A lot depends on exactly which CPLD or which FPGA you are looking at and how
they put the guts of it together. If you find one that is “just right” it
*might* be within
10 db of high speed CMOS. Since there is a 20 db delta between the HC you
mention
and the AC that leaves a bit of room.
david.partri...@perdrix.co.uk said:
Is this a sensible thing to consider doing? Or would I be better sticking
to AC/HC/AHC/LVC logic?
A CPLD is a fine way to divide by a large number. Even the smaller FPGAs are
probably overkill but they should work fine.
If you are interested in jitter,
Am 02.06.2015 um 21:27 schrieb Tom Van Baak:
Is this a sensible thing to consider doing? Or would I be better sticking to
AC/HC/AHC/LVC logic?
Regards,
David Partridge
Yes, please consider it. I would be very interested in the results.
I have made a stamp sized board that has a Xilinx 2C64
On Tue, 2 Jun 2015 14:13:04 +0100
David C. Partridge david.partri...@perdrix.co.uk wrote:
Is this a sensible thing to consider doing?
Or would I be better sticking to AC/HC/AHC/LVC logic?
It depends ;-)
For most things it should be ok. You can reach lower levels of noise
with single 74xxx
On Tuesday, June 02, 2015 02:13:04 PM David C. Partridge wrote:
Is this a sensible thing to consider doing? Or would I be better sticking
to AC/HC/AHC/LVC logic?
`
Regards,
David Partridge
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You can always cleanup the outputs of the CPLD or FPGA by resynchronising the
outputs to the input clock using a dedicated D flipflop for each output.
Bruce
On Wednesday, 3 June 2015 3:22 PM, Bob Camp kb...@n1k.org wrote:
Hi
A lot depends on exactly which CPLD or which FPGA you
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