well. thank you everyone for your contributions !
I had a good night in reading the references.
I agree the cascaded band-limited limiter strategy is eminently suitable.
That LT part looks like an excellent option, of course,
horses-for-courses caveat applies for freqs and risetimes...
On
Hi,
Yes, indeed, so for many purposes the 6957 is probably good enough, and
actually better than many classical approaches (i.e. direct
comparators). It is when you design for a fixed or very narrow range of
frequencies that you should consider rolling your own, assuming the
performance of the
Hi
Assuming we are still talking about a test instrument that needs to handle a
variety of levels
and a range of frequencies, the 6957 is probably as good as anything.
With a “full up” Collins style circuit, you very much need to optimize for a
specific input.
Change that and you change the
Hi,
On 2019-07-27 12:07, Attila Kinali wrote:
> On Sat, 27 Jul 2019 18:21:50 +1200 (NZST)
> Bruce Griffiths wrote:
>
>> The LTC6957 is a better choice for squaring up sinewaves:
>> http://www.ko4bb.com/getsimple/index.php?id=phase-noise-and-other-measurements-with-a-timepod
> If you want to have
In all our critical work we use the LTC6957,we call it the Bruce circuit, only
problem at 78 and 80 difficult to solder
Bert Kehren
In a message dated 7/27/2019 4:04:50 AM Eastern Standard Time,
bruce.griffi...@xtra.co.nz writes:
The LTC6957 is a better choice for squaring up sinewaves:
The LTC6957 is a better choice for squaring up sinewaves:
http://www.ko4bb.com/getsimple/index.php?id=phase-noise-and-other-measurements-with-a-timepod
CERN amongst others use it. The pin programmable filtering allows its bandwidth
to be optimised to suit the input signal frequency and amplitude.
Hi
there is quite a bit done in this area of FPGAs, IDELAYS etc for this
application. and also quite a bit written already on TIMENUTS I find
from archives.
From my POV, the pressure on the design is the input circuitry...My gut
is to start with a ADCMP572 and drive several FPGA pins with
> Was considering 16 LVDS receivers and IDELAYS to emulate a single fast
> comparator,
I haven't done serious work with FPGAs in 10 or 15 years.
That seems like an obvious hack, but it depends on the implementation details
inside the FPGA. What's the granularity? How much does it change
I'm currently getting schematics together for just such a box, to be
open source etc. maybe it can be a TAPR project I dunno.
I'll release round 1 schematics shortly.
Most of my ZCD work to this point usually uses LVDS receivers either
discrete or FPGA IOBUF
and more lately the ADCMP572
