As we moved data_crc() invocation from jffs2_1pass_build_lists() to
jffs2_1pass_read_inode() data_crc is going to be calculated on each
inode access. This patch adds caching of data_crc() results. There
is no significant improvement in speed (because of flash access
caching added in previous patch
This patch adds support for reading fs information from summary
node instead of scanning full eraseblock.
Signed-off-by: Ilya Yanok [EMAIL PROTECTED]
---
fs/jffs2/jffs2_1pass.c | 187 +++-
fs/jffs2/summary.h | 163
Hello everybody,
here is a set of changes we made to improve U-Boot JFFS2 code
performance. We still can't reach Linux's performance but improvements
are significant.
Any comments are welcome.
Regards, Ilya.
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Rewrites jffs2_1pass_build_lists() function in style of Linux's
jffs2_scan_medium() and jffs2_scan_eraseblock().
This includes:
- Caching flash acceses
- Smart dealing with free space
Signed-off-by: Alexey Neyman [EMAIL PROTECTED]
Signed-off-by: Ilya Yanok [EMAIL PROTECTED]
---
On 00:27 Mon 13 Oct , Wolfgang Denk wrote:
Dear Jean-Christophe,
In message [EMAIL PROTECTED] you wrote:
On 10:36 Fri 29 Aug , Magnus Lilja wrote:
The i.MX31 has three SPI buses and each bus has several chip selects
and the MC13783 chip can be connected to any of these. The
On 00:27 Mon 13 Oct , Wolfgang Denk wrote:
Dear Jean-Christophe,
In message [EMAIL PROTECTED] you wrote:
On 10:36 Fri 29 Aug , Magnus Lilja wrote:
Add support for the Freescale i.MX31 PDK (a.k.a 3DS) board. Ethernet and
MC13873 RTC support is enabled by this patch.
On 00:19 Mon 13 Oct , Wolfgang Denk wrote:
Dear Jean-Christophe,
In message [EMAIL PROTECTED] Markus Kammerstetter wrote:
Hi,
I added support for the Olimex SAM9L-9260 development board to the
current git source tree.
The original code is from the at91sam9260ek implementation
Dear Ilya,
In message [EMAIL PROTECTED] you wrote:
here is a set of changes we made to improve U-Boot JFFS2 code
performance. We still can't reach Linux's performance but improvements
are significant.
Any comments are welcome.
Are these patches independent of each other, or are all
Dear Jean-Christophe PLAGNIOL-VILLARD,
In message [EMAIL PROTECTED] you wrote:
doc/README.mx31 | 19 +++
drivers/rtc/mc13783-rtc.c |6 --
include/configs/imx31_litekit.h |3 +++
include/configs/mx31ads.h |3 +++
4
On 10:25 Mon 13 Oct , Wolfgang Denk wrote:
Dear Jean-Christophe PLAGNIOL-VILLARD,
In message [EMAIL PROTECTED] you wrote:
On 10:36 Fri 29 Aug , Magnus Lilja wrote:
Add support for the Freescale i.MX31 PDK (a.k.a 3DS) board. Ethernet
and
MC13873 RTC support is
On Thursday 09 October 2008, Ed Swarthout wrote:
The flash_unlock_seq requires a sector for AMD_LEGACY.
Fix a retcode check typeo.
Applied to cfi/master. Thanks.
Best regards,
Stefan
=
DENX Software Engineering GmbH, MD:
Dear Stefan Roese,
In message [EMAIL PROTECTED] you wrote:
The following changes since commit df4a0796e86662536df2387ddcf969c2a704bcc2:
Wolfgang Denk (1):
Merge branch 'master' of ssh://10.10.0.7/home/wd/git/u-boot/master
are available in the git repository at:
Dear Kumar,
In message [EMAIL PROTECTED] you wrote:
For some reason we duplicated the majority of code in lib_ppc/interrupts.c
not show how that happened, but there is no good reason for it.
Use the interrupt_init_cpu() and timer_interrupt_cpu() since its why
they exist.
Signed-off-by:
Dear Luigi 'Comio' Mantellini,
In message [EMAIL PROTECTED] you wrote:
Date: Sat, 13 Sep 2008 10:04:32 +0200
Subject: [PATCH] Fix lzma uncompress call (image_start wrongly used instead=
image_len)
Signed-off-by: Luigi 'Comio' Mantellini [EMAIL PROTECTED]
---
common/cmd_bootm.c |2
Dear Hugo Villeneuve,
In message [EMAIL PROTECTED] you wrote:
ARM DaVinci: Remove redundant setting of GD_FLG_RELOC for sffsdr
board.
...
Jean-Christophe,
did you integrate that patch in your tree?
Obviously not, but since this is a board-specific patch I pulled it
directly.
Best
On Mon, 2008-10-13 at 00:53 +0200, Wolfgang Denk wrote:
Dear Ed Swarthout,
In message [EMAIL PROTECTED] you wrote:
Fixes boot crash from bad string pointers in get_table_entry_name
when flash is erased or differs from current u-boot image.
Signed-off-by: Ed Swarthout [EMAIL PROTECTED]
Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
board/amcc/canyonlands/bootstrap.c | 12
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/board/amcc/canyonlands/bootstrap.c
b/board/amcc/canyonlands/bootstrap.c
index 1d125b6..5d832de 100644
---
Dear Jon,
In message [EMAIL PROTECTED] you wrote:
6185 08/19 Kumar Gala [U-Boot] [PATCH] 86xx: remove redudant code
with lib_ppc/interrupts.c
6767 08/28 Nick Spence[U-Boot] [PATCH] mpc86xx: use r4 instead of
r2 in lock_ram_in_cache a
Sorry, got buried here. If
hello,
Does anyone ever try to load a WinCE kernel image(NK.bin or NK.nb0)?
Thanks!
Jerry
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The following changes since commit 50a874b3b0272f32e3627732fab90b27fbd35066:
Stefan Roese (1):
Merge branch 'master' of /home/stefan/git/u-boot/u-boot
are available in the git repository at:
git://www.denx.de/git/u-boot-ppc4xx.git master
Adam Graham (1):
ppc4xx: Reset and
Dear Stefan Roese,
In message [EMAIL PROTECTED] you wrote:
The following changes since commit 50a874b3b0272f32e3627732fab90b27fbd35066:
Stefan Roese (1):
Merge branch 'master' of /home/stefan/git/u-boot/u-boot
are available in the git repository at:
Dear Kim,
In message [EMAIL PROTECTED] Anton
Vorontsov wrote:
Currently 64M of LBC SDRAM are mapped at 0xF000 which makes
it difficult to use (b/c then the memory is discontinuous and
there is quite big memory hole between the DDR/SDRAM regions).
This patch reworks LBC SDRAM setup so
Previously only the NOR flash mapping was written into the ranges
property of the ebc node. This patch now writes all enabled chip
select areas into the ranges property.
Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
cpu/ppc4xx/fdt.c | 45
On Sat, Oct 11, 2008 at 10:55:37AM +0200, Dirk Behme wrote:
It's looking decent. I have some concerns about the ECC switching,
though.
Yes, I know, agreed. But changing existing kernels isn't easy, too.
I meant the implementation (specifically, the re-init of things done by
Dear Nick Spence,
In message [EMAIL PROTECTED] you wrote:
This is needed in unlock_ram_in_cache() because it is called from C and
will corrupt the small data area anchor that is kept in R2.
lock_ram_in_cache() is modified similarly as good coding practice, but
is not called from C.
On Mon, 2008-10-13 at 13:58 +0200, Wolfgang Denk wrote:
Dear Jon,
In message [EMAIL PROTECTED] you wrote:
6185 08/19 Kumar Gala [U-Boot] [PATCH] 86xx: remove redudant
code with lib_ppc/interrupts.c
6767 08/28 Nick Spence[U-Boot] [PATCH] mpc86xx: use r4 instead
On Fri, Oct 3, 2008 at 10:46 AM, Haiying Wang
[EMAIL PROTECTED] wrote:
MPC8572DS has two i2c buses. This patch moves the DDR SPD_EEPROM to i2c bus 1
according to the board spec, and adds the 2nd i2c bus offset.
Signed-off-by: Haiying Wang [EMAIL PROTECTED]
Applied 1-3, and they were pulled.
On Fri, Oct 3, 2008 at 11:36 AM, Haiying Wang
[EMAIL PROTECTED] wrote:
Fix some bugs:
1. Correctly set intlv_ctl in cs_config.
2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
3. Set base_address and total memory for each ddr controller in memory
controller
On Wed, Oct 8, 2008 at 3:36 PM, Kumar Gala [EMAIL PROTECTED] wrote:
Commit 445a7b38308eb05b41de74165b20855db58c7ee5 introduced the following
compile warnings:
cmd_i2c.c:112: warning: missing braces around initializer
cmd_i2c.c:112: warning: (near initialization for 'i2c_no_probes[0]')
Signed-off-by: Kumar Gala [EMAIL PROTECTED]
---
common/cmd_bootm.c | 149 -
include/image.h| 20 -
lib_ppc/bootm.c| 272 ++--
3 files changed, 347 insertions(+), 94 deletions(-)
* Added flushing the data
Signed-off-by: Kumar Gala [EMAIL PROTECTED]
---
cpu/74xx_7xx/cache.S | 10 +-
cpu/mpc86xx/cache.S | 10 +-
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/cpu/74xx_7xx/cache.S b/cpu/74xx_7xx/cache.S
index eac4544..62a6683 100644
--- a/cpu/74xx_7xx/cache.S
+++
On Oct 8, 2008, at 8:48 PM, Jerry Van Baren wrote:
Kumar Gala wrote:
* Use new find_cmd_tbl() to process sub-commands
If this looks good I'll go ahead and clean it up for the other
arches and OSes.
Hi Kumar,
Thanks to your sequence hint, interrupt command hint, and one
additional
On Wed, Oct 8, 2008 at 11:38 PM, Ed Swarthout
[EMAIL PROTECTED] wrote:
Signed-off-by: Ed Swarthout [EMAIL PROTECTED]
Acked-by: Andy Fleming [EMAIL PROTECTED]
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On Wed, Oct 8, 2008 at 11:38 PM, Ed Swarthout
[EMAIL PROTECTED] wrote:
Signed-off-by: Ed Swarthout [EMAIL PROTECTED]
Applied to 85xx-next
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On Wed, Oct 8, 2008 at 11:37 PM, Ed Swarthout
[EMAIL PROTECTED] wrote:
Signed-off-by: Ed Swarthout [EMAIL PROTECTED]
Applied to 85xx-next
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On Thu, Oct 9, 2008 at 1:25 AM, Ed Swarthout [EMAIL PROTECTED] wrote:
Debug sessions may have left enabled laws.
Changing lawbar with an unkown enabled tgtid could cause problems.
Signed-off-by: Ed Swarthout [EMAIL PROTECTED]
Applied to 85xx-next
On Thu, Oct 9, 2008 at 1:26 AM, Ed Swarthout [EMAIL PROTECTED] wrote:
This allows a second core to restart without causing a PIC reset.
Internal interupt changes:
Enable L2 error interrupt IIVPR0 and give it vector 0x100.
Use correct interrupt (8) for mpc8572 pcie3.
Add pcie3 interrupt (11)
On Mon, 2008-10-13 at 14:14 -0500, Andy Fleming wrote:
On Wed, Oct 8, 2008 at 11:38 PM, Ed Swarthout
[EMAIL PROTECTED] wrote:
Signed-off-by: Ed Swarthout [EMAIL PROTECTED]
Acked-by: Andy Fleming [EMAIL PROTECTED]
When agent/end-point, I thought the CPU must enable inbound PCI
configuration
Hi ML,
i'm working on a SoC (mips based) that uses a denali ddr2 controller.
I noticed that also ppc4xx uses the same IP (or it's very similar).
I have a stupid trouble: i need to do a software reset of the denali,
but I cannot reconfigure it twice... losting the ddr memory space.
Of course, at
On Wed, Oct 8, 2008 at 11:38 PM, Ed Swarthout
[EMAIL PROTECTED] wrote:
Signed-off-by: Ed Swarthout [EMAIL PROTECTED]
Applied to 85xx-next
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Dear Ed Swarthout,
In message [EMAIL PROTECTED] you wrote:
Signed-off-by: Ed Swarthout [EMAIL PROTECTED]
---
drivers/pci/fsl_pci_init.c | 17 +++--
1 files changed, 15 insertions(+), 2 deletions(-)
Applied, thanks.
Best regards,
Wolfgang Denk
--
DENX Software Engineering
Dear Stefan Roese,
In message [EMAIL PROTECTED] you wrote:
OK, I added this patch [1/6] to the u-boot-cfi-flash next branch. Here the
pull
request for the *next* branch:
The following changes since commit 8fd4166c467a46773f80208bda1ec3b4757747bc:
Stefan Roese (1):
ppc4xx:
Dear Bartlomiej Sieka,
In message [EMAIL PROTECTED] you wrote:
The auto-update feature allows to automatically download software updates
from a TFTP server and store them in Flash memory during boot. Updates are
contained in a FIT file and protected with SHA-1 checksum.
More detailed
Dear Bartek,
in message [EMAIL PROTECTED] you wrote:
This is the second version of the patch series adding support for automatic
software updates from a TFTP server. V2 adds millisecond granularity of the
TFTP timeouts and addresses comments posted to the ML for the first version.
First
On Thu, Oct 9, 2008 at 10:40 PM, Jason Jin [EMAIL PROTECTED] wrote:
From: Liu Yu [EMAIL PROTECTED]
This patch based on Andy's work.
Including command 'pixis_set_sgmii' support.
Signed-off-by: Liu Yu [EMAIL PROTECTED]
Applied to 85xx-next
___
From: Peter Tyser [mailto:[EMAIL PROTECTED]
When agent/end-point, I thought the CPU must enable inbound
PCI configuration cycles by poking the PBFR Register (offset
0x44) for PCI, or the Configuration Ready Register (offset
0x4b0 for PCIe) after configuring its own inbound BARs.
That is
This patch series does $SUBJ.
The first patch changes the way the existing linker scripts locate the boot
page, reset vector, and bss section. This method works for any size of u-boot
image (the previous one didn't work images that weren't 512K) and any location
flash is mapped to.
At this
Dear Trent,
In message [EMAIL PROTECTED] you wrote:
At this point all the mpc85xx linker scripts are exactly the same, except for
one line that defines the flash bank size, so they are combined into one
script in cpu/mpc85xx/u-boot.lds. A common flash bank size that will work for
all
It wasn't used in one instance where the end of the rotext section is
aligned to 256 bytes.
Maybe this alignment isn't necessary? I have to wonder about the alignment
of the .data.init and .text.init sections too, since they don't appear to
even exist.
Signed-off-by: Trent Piepho [EMAIL
The boot page and reset vector need to be at the absolute address
0xf000 and 0xfffc, respectively, when the CPU boots.
However, their location in the U-Boot image is relative to the address that
flash is mapped at. For instance, mpc8572ds maps the 128MB flash boot bank
to 0xe800,
On Thu, 2 Oct 2008 19:17:33 +0400
Anton Vorontsov [EMAIL PROTECTED] wrote:
The MPC837xE-MDS board's CPLD can auto-detect if the board is on the PIB,
standalone or acting as a PCI agent. User's Guide says:
- When the CPLD recognizes its location on the PIB it automatically
configures RCW
On Thu, 9 Oct 2008 10:29:14 +0530
Selvamuthukumar [EMAIL PROTECTED] wrote:
Reference manual states that MxMR[MAD] increment is the indication
of write to UPM array is complete. Honour that. Also, make the dummy
write explicit.
Signed-off-by: Selvamuthukumar [EMAIL PROTECTED]
---
Ignore
On Mon, 13 Oct 2008 14:40:02 +0200
Wolfgang Denk [EMAIL PROTECTED] wrote:
Signed-off-by: Anton Vorontsov [EMAIL PROTECTED]
---
board/freescale/mpc8360emds/mpc8360emds.c | 39
-
include/configs/MPC8360EMDS.h | 25 --
2 files
On Wed, 10 Sep 2008 18:12:37 +0400
Anton Vorontsov [EMAIL PROTECTED] wrote:
Currently 64M of LBC SDRAM are mapped at 0xF000 which makes
it difficult to use (b/c then the memory is discontinuous and
there is quite big memory hole between the DDR/SDRAM regions).
This patch reworks LBC
On Oct 9, 2008, at 10:41 PM, Jason Jin wrote:
SGMII and SATA share the serdes on MPC8536 CPU, When SATA disabled
and the
driver still try to access the SATA registers, the cpu will hangup.
This patch try to fix this by reading the serdes status before the
SATA
initialize.
Signed-off-by: Nobuhiro Iwamatsu [EMAIL PROTECTED]
---
include/configs/rsk7203.h |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/include/configs/rsk7203.h b/include/configs/rsk7203.h
index d99e4f3..1f20e57 100644
--- a/include/configs/rsk7203.h
+++
From: Joakim Tjernlund [mailto:[EMAIL PROTECTED]
The __eabi_uconvert() function skips NULL ptrs.
Perhaps this is the missing piece needed in start.S for PPC?
I'm not seeing any zeros in the .got2 or .fixup entries
in the .reloc section on 85xx when compiling with -mrelocatable.
So I
richardretanubun wrote:
richardretanubun wrote:
The current uec_miiphy_read and uec_miiphy_write hardcode access
devlist[0]
This patch makes these function use the devname argument that is
passed in to
allow access to the phy registers of other devices in devlist[].
Signed-of-by:
richardretanubun wrote:
Fixed compiler warning declared but unused eth5_uec_info and
eth6_uec_info.
Signed-off-by: Richard Retanubun [EMAIL PROTECTED]
---
Hi Ben,
Thanks for applying the patch. I got a compiler warning when using it,
here is a patch to fix that.
Thanks for all the help
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