Hi Tom,
Thanks for reply and need more help...
on host machine i can easily see the all partition by applying dfu-util
-l.
and i am able to download images from pc to dfu-devices and it running
fine, but in case of uploading (from dfu-device to PC), my system just
copied only 1 byte data,
On 06/21/2013 06:40 AM, Vipin Kumar wrote:
On 6/20/2013 7:26 PM, Axel Lin wrote:
2013/6/20 Marek Vasutma...@denx.de
Dear Axel Lin,
In current gpio_set_value() implementation, it always sets the gpio control
bit no matter the value argument is 0 or 1. Thus the GPIOs never set to
low. This
Hi Axel,
On 21/06/13 06:07, Axel Lin wrote:
AM33XX has 4 gpio banks, thus the valid gpio range should be 0 ... 127.
Signed-off-by: Axel Lin axel@ingics.com
---
v2: define OMAP_MAX_GPIO and use it.
This change is mainly based on Stefan's comment, however I use
OMAP_MAX_GPIO instead of
2013/6/21 Lubomir Popov lpo...@mm-sol.com:
Hi Axel,
On 21/06/13 06:07, Axel Lin wrote:
AM33XX has 4 gpio banks, thus the valid gpio range should be 0 ... 127.
Signed-off-by: Axel Lin axel@ingics.com
---
v2: define OMAP_MAX_GPIO and use it.
This change is mainly based on Stefan's
The functionality env_import will be used in the SPL. They
had been excluded by ifndef CONFIG_SPL_BUILD. Now, put it
into the SPL.
Signed-off-by: Ying Zhang b40...@freescale.commailto:b40...@freescale.com
---
Compared with the original version, Changed as below:
1. Split from boot
Hi Axel,
On 21/06/13 10:13, Axel Lin wrote:
2013/6/21 Lubomir Popov lpo...@mm-sol.com:
Hi Axel,
On 21/06/13 06:07, Axel Lin wrote:
AM33XX has 4 gpio banks, thus the valid gpio range should be 0 ... 127.
Signed-off-by: Axel Lin axel@ingics.com
---
v2: define OMAP_MAX_GPIO and use it.
One more thing that perhaps seems more reasonable in general:
These OMAP_MAX_GPIO defines could go into the corresponding .../arch-omap*.h
files, where the base addresses are defined, and the number of GPIOs is
implicitly obvious. And we shall have no ugly #ifdefs in the GPIO driver.
Tom, what
AM33XX has 4 gpio banks, thus the valid gpio range should be 0 ... 127.
Signed-off-by: Axel Lin axel@ingics.com
Acked-by: Stefan Roese s...@denx.de
---
v2: define OMAP_MAX_GPIO and use it.
v3: no change, just for adding patch 2/2.
drivers/gpio/omap_gpio.c | 8 +++-
1 file changed, 7
OMAP54XX and DRA7XX SoCs have 8 banks per 32 GPIOs, that is, 256 in total.
The DRA7xx config defines CONFIG_DRA7XX, but also includes omap5_common.h,
where CONFIG_OMAP54XX is defined (due to sharing of many internal IPs with
the OMAP5, including GPIO).
Reported-by: Lubomir Popov lpo...@mm-sol.com
Hello Lubomir,
Am 21.06.2013 09:44, schrieb Lubomir Popov:
One more thing that perhaps seems more reasonable in general:
These OMAP_MAX_GPIO defines could go into the corresponding .../arch-omap*.h
files, where the base addresses are defined, and the number of GPIOs is
implicitly obvious.
2013/6/21 Heiko Schocher h...@denx.de:
Hello Lubomir,
Am 21.06.2013 09:44, schrieb Lubomir Popov:
One more thing that perhaps seems more reasonable in general:
These OMAP_MAX_GPIO defines could go into the corresponding .../arch-omap*.h
files, where the base addresses are defined, and the
OMAP54XX and DRA7XX SoCs have 8 banks per 32 GPIOs, that is, 256 in total.
Fix the gpio bank setting.
Signed-off-by: Axel Lin axel@ingics.com
---
arch/arm/cpu/armv7/omap5/hwinit.c | 4 +++-
arch/arm/include/asm/arch-omap5/gpio.h | 2 ++
2 files changed, 5 insertions(+), 1 deletion(-)
Now the omap_gpio driver is used by AM33XX, OMAP3/4, OMAP54XX and DRA7XX SoCs.
These SoCs have various gpio count. Thus introduce get_omap_gpio_count()
function to get correct gpio count.
Signed-off-by: Axel Lin axel@ingics.com
---
arch/arm/cpu/armv7/am33xx/board.c | 5 +
Hi Stefan,
On Fri, 21 Jun 2013 04:13:17 +0200, Stefan Roese s...@denx.de wrote:
Fix a problem with a re-assignment of r8 in the SPL version.
This patch now moves the call to s_init() to a later stage, right before
calling board_init_f(). And makes sure that r8 is correctly initialized
SPL already has GD set to the correct location (in s_init), we mustn't
move it around now since some data (clocks etc) is already present.
This error was detected on the SPL port for the Compulab CM-T35 board
(OMAP3530).
Signed-off-by: Stefan Roese s...@denx.de
Cc: Tom Rini tr...@ti.com
Cc:
Hi Tom,
Thanks for your quick reply.
2013/6/20 Tom Rini tr...@ti.com
On Thu, Jun 20, 2013 at 12:27:02PM +0200, Enric Balletbo Serra wrote:
Hi all,
I've some problems trying to boot a zImage with following command after
load the zImage and the fdt file on memory:
U-Boot fdt addr
Hi Heiko, Axel,
On 21/06/13 11:44, Heiko Schocher wrote:
Hello Lubomir,
Am 21.06.2013 09:44, schrieb Lubomir Popov:
One more thing that perhaps seems more reasonable in general:
These OMAP_MAX_GPIO defines could go into the corresponding .../arch-omap*.h
files, where the base addresses
Axel,
Why do you introduce a function when this stuff is constant and known
to the compiler? Just put a #define in every header. You are now
uselessly inflating code...
Regards,
Lubo
On 21/06/13 11:50, Axel Lin wrote:
Now the omap_gpio driver is used by AM33XX, OMAP3/4, OMAP54XX and DRA7XX
From: Andy Fleming [mailto:aflem...@gmail.com]
Sent: Thursday, June 20, 2013 12:37 AM
To: Zhang Ying-B40530; jagannadha.sutradharudu-t...@xilinx.com
Cc: U-Boot list; Wood Scott-B07421; Xie Xiaobo-R63061; Zhang Ying-B40530
Subject: Re: [PATCH 8/8] powerpc/p1022ds: boot from spi flash with SPL
Hi Stefan,
On Fri, 21 Jun 2013 11:10:10 +0200, Stefan Roese s...@denx.de wrote:
SPL already has GD set to the correct location (in s_init), we mustn't
move it around now since some data (clocks etc) is already present.
Actually the commit message is not accurate any more, as it states
s_init
On 21.06.2013 12:30, Albert ARIBAUD wrote:
SPL already has GD set to the correct location (in s_init), we mustn't
move it around now since some data (clocks etc) is already present.
Actually the commit message is not accurate any more, as it states
s_init should keep setting gd -- sorry for
Fix a problem with a re-assignment of r8 in the SPL version.
This patch now moves the call to s_init() to a later stage, right before
calling board_init_f(). And makes sure that r8 is correctly initialized
before s_init() is called. r8 now is only written in crt0.S.
This error was detected on
The omap_gpio driver is used by AM33XX, OMAP3/4, OMAP54XX and DRA7XX SoCs.
These SoCs have different gpio count but currently omap_gpio driver uses hard
coded 192 which is wrong.
This patch fixes this issue by:
1. Move define of OMAP_MAX_GPIO to all arch/arm/include/asm/arch-omap*/gpio.h.
2.
Hi Stefan,
On Fri, 21 Jun 2013 12:42:46 +0200, Stefan Roese s...@denx.de wrote:
Fix a problem with a re-assignment of r8 in the SPL version.
This patch now moves the call to s_init() to a later stage, right before
calling board_init_f(). And makes sure that r8 is correctly initialized
Add USB EHCI, storage and network support.
Tested on Tegra30 Cardhu, and Tegra114 Dalmore
platforms. All works well.
Signed-off-by: Jim Lin ji...@nvidia.com
---
Changes in v2:
- Add support for Beaver board.
Changes in v3:
- None
Changes in v4:
- None
Changes in v5:
- None
Add DT node for USB EHCI function.
Add support for T30-Cardhu, T30-Beaver, T114-Dalmore boards.
Signed-off-by: Jim Lin ji...@nvidia.com
---
Changes in v2:
- Remove PLL parameters from dt file
Changes in v3:
- Change VBus GPIO from H.05 to DD.04 for Beaver board.
Changes in v4:
- Change Beaver
Tegra30 and Tegra114 are compatible except PLL parameters.
Tested on Tegra30 Cardhu, and Tegra114 Dalmore
platforms. All works well.
Signed-off-by: Jim Lin ji...@nvidia.com
---
Changes in v2:
- Move common definitions into arch-tegra/usb.h and
chip specific definitions into
Hi Axel,
On 21/06/13 13:54, Axel Lin wrote:
The omap_gpio driver is used by AM33XX, OMAP3/4, OMAP54XX and DRA7XX SoCs.
These SoCs have different gpio count but currently omap_gpio driver uses hard
coded 192 which is wrong.
This patch fixes this issue by:
1. Move define of OMAP_MAX_GPIO to
- Added debug's on spi_flash_read_common()
- Added space
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v3:
-
Changes for v2:
-
drivers/mtd/spi/spi_flash.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git
Move common flash write code into spi_flash_write_common().
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Acked-by: Simon Glass s...@chromium.org
---
Changes for v3:
- Used proper comments on spi_flash_write_common
Changes for v2:
-
drivers/mtd/spi/spi_flash.c
From: Jagannadha Sutradharudu Teki jagannadha.sutradharudu-t...@xilinx.com
Warning for 16MiB flashes to #define CONFIG_SPI_FLASH_BAR
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v3:
-
Changes for v2:
-
drivers/mtd/spi/spi_flash.c | 6 ++
1
From: Jagannadha Sutradharudu Teki jagannadha.sutradharudu-t...@xilinx.com
Placed the sf calls in proper order - erase/write/read
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v3:
-
Changes for v2:
-
drivers/mtd/spi/spi_flash.c | 184
Add support for Spansion S25FL512S_64K SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v5:
- none
Changes for v4:
- none
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/spansion.c | 7 +++
1 file
Add support for Numonyx N25Q1024 SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v5:
- none
Changes for v4:
- none
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/stmicro.c | 6 ++
1 file changed, 6
This patch updated the spi_flash read func to support all
sizes of flashes using bank reg addr facility.
The same support has been added in below patch for erase/write
spi_flash functions:
sf: Support all sizes of flashes using bank addr reg facility
(sha1:
This is a v5 patch series with some modifications on previous series
with same head sf: Update sf framework to support all sizes of flashes
The current implementation in sf supports 3-byte address mode due to
this up to 16MB amount of flash is able to access for those flashes
which has an actual
Add support for Numonyx N25Q512 SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v5:
- none
Changes for v4:
- none
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/stmicro.c | 6 ++
1 file changed, 6
Bank/Extended addr commands are specific to particular
flash vendor so discover them based on the idocode0.
Assign the discovered bank commands to spi_flash members
so-that the bank read/write will use their specific operations.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Defined bank addr code on CONFIG_SPI_FLASH_BAR macro, to reduce the
size for existing boards which has 16Mbytes SPI flashes.
It's upto user which has provision to use the bank addr code for
flashes which has 16Mbytes.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Reviewed-by:
Dear Rajeshwari Shinde,
On 17 May 2013 20:03, Rajeshwari Shinde rajeshwar...@samsung.com wrote:
Add required compatible information for s5p serial driver
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
Acked-by: Simon Glass
Use the existing spi_flash_addr() for 3-byte addressing
cmd filling in write call.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Reviewed-by: Simon Glass s...@chromium.org
---
Changes for v5:
- none
Changes for v4:
- none
Changes for v3:
- none
Changes
Add support for Numonyx N25Q512A SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v5:
- none
Changes for v4:
- none
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/stmicro.c | 6 ++
1 file changed, 6
Flag status register polling is required for micron 512Mb flash
devices onwards, for performing erase/program operations.
Like polling for WIP(Write-In-Progress) bit in read status register,
spi_flash_cmd_wait_ready will poll for PEC(Program-Erase-Control)
bit in flag status register.
Read the flash bank addr register to get the state of bank in
a perticular flash. and also bank write happens only when there is
a change in bank selection from user.
bank read only valid for flashes which has 16Mbytes those are
opearted in 3-byte addr mode, each bank occupies 16Mytes.
Suppose
Add support for Numonyx N25Q1024A SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v5:
- none
Changes for v4:
- none
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/stmicro.c | 6 ++
1 file changed, 6
Updated the spi_flash framework to handle all sizes of flashes
using bank/extd addr reg facility
The current implementation in spi_flash supports 3-byte address mode
due to this up to 16Mbytes amount of flash is able to access for those
flashes which has an actual size of 16MB.
As most of the
There is no other call other than spi_flash_cmd_wait_ready(),
hence removed spi_flash_cmd_poll_bit and use the poll status code
spi_flash_cmd_wait_ready() itself.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Reviewed-by: Simon Glass s...@chromium.org
---
Changes for v5:
This patch provides support to program a flash bank address
register.
extended/bank address register contains an information to access
the 4th byte addressing in 3-byte address mode.
reff' the spec for more details about bank addr register
in Page-63, Table 8.16
Hi Rob,
On Sun, Jun 16, 2013 at 9:29 PM, Joe Hershberger
joe.hershber...@gmail.com wrote:
Hi Rob,
On Sun, Jun 16, 2013 at 10:24 AM, Rob Herring robherri...@gmail.com wrote:
On Tue, May 14, 2013 at 3:32 PM, Joe Hershberger
joe.hershber...@gmail.com wrote:
Hi Rob,
On Tue, May 14, 2013 at
Dear Rajeshwari Shinde,
On 17 May 2013 20:03, Rajeshwari Shinde rajeshwar...@samsung.com wrote:
This patch adds FDT support to the serial s5p driver.
At present disabling the serial console (from the device tree) crashes
U-Boot. Add checks for this case, so that execution can continue
On the xscale, the icache must be invalidated and the write buffers drained
after writing code over the data bus, even if the caches are disabled. Tested
on the pxa270.
Signed-off-by: Mike Dunn miked...@newsguy.com
---
arch/arm/lib/relocate.S |9 +
1 files changed, 9 insertions(+),
These patches fix a memory coherency problem that sometimes occurs on xscale
after code relocation. The first patch changes the options passed to the
compiler so that the __XSCALE__ macro is defined. This is used in the second
patch to limit the change to xscale cores, where the necessary cache
Pass '-mcpu=xscale' to the compiler instead of march and mtune. This will cause
gcc to define the __XSCALE__ macro.
Signed-off-by: Mike Dunn miked...@newsguy.com
---
arch/arm/cpu/pxa/config.mk |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/pxa/config.mk
On 06/21/2013 05:05 AM, Jim Lin wrote:
Add DT node for USB EHCI function.
Add support for T30-Cardhu, T30-Beaver, T114-Dalmore boards.
Changes in v5:
- Move changes on fdtdec.h and fdtdec.c to patch 2/3
- Modify PHY type to hsic for USB2 port
HSIC is an odd choice; ULPI is much more
Dear Piotr Wilczek,
On 21 May 2013 21:54, Piotr Wilczek p.wilc...@samsung.com wrote:
This patch add new functions to pmic max77686 to set voltage and mode.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
CC: Minkyu Kang
On 06/20/2013 11:19:19 PM, Heiko Schocher wrote:
Hello Scott,
Am 20.06.2013 19:52, schrieb Scott Wood:
adjust_size_for_badblocks reduces the the operation size to account
nitpicking:
please only one the.
Thanks, I'll fix when applying.
-Scott
___
On Wed, Jun 05, 2013 at 14:51 +0200, Gerhard Sittig wrote:
this change set adjusts the configuration of the 'ifm AC14xx' board
to get closer to mainline philosophy and slightly improves builtin
diagnostics and robustness after setup failure
changes in v2:
- address a potential NULL
Add the libdwc3 to the Makefile so that drivers/usb/dwc3 is included
in the build
Signed-off-by: Dan Murphy dmur...@ti.com
---
Makefile |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/Makefile b/Makefile
index ef154aa..e0a15cf 100644
--- a/Makefile
+++ b/Makefile
@@
This patch series has been generated in an effort to get comments on
the implementation of the dwc code within the uBoot.
The first patch is the one of major concern as this patch will make an
attempt to commonize the usb headers so that there is re-use and prepare
the usb headers for future usb
Add and enable the USB OTG clocks.
Signed-off-by: Dan Murphy dmur...@ti.com
---
arch/arm/cpu/armv7/omap5/hw_data.c | 14 ++
arch/arm/cpu/armv7/omap5/prcm-regs.c |1 +
arch/arm/include/asm/arch-omap5/clocks.h |4
arch/arm/include/asm/omap_common.h |1
Hello,
On Thu, Jun 13, 2013 at 2:01 PM, Andre Przywara
andre.przyw...@linaro.orgwrote:
For the KVM and XEN hypervisors to be usable, we need to enter the
kernel in HYP mode. Now that we already are in non-secure state,
HYP mode switching is within short reach.
While doing the non-secure
Hello All,
In my device tree blob, i would like to add some interrupt to the
protected-source list dynamically in the u-boot before launching the linux
kernel.
mpic: pic@4 {
interrupt-controller;
#address-cells = 0;
#interrupt-cells = 2;
reg =
Hello Wolfgang,
On 06/21/2013 07:33 AM, Wolfgang Denk wrote:
We observed the very same issue with the verry first prototype
implementation of Falcon mode on an AM3517 based board. [..]
For the am3517 the only thing needed is to add SRAM
to the known memory. See [1], that should change the
On Fri, Jun 21, 2013 at 08:46:47PM +0200, Jeroen Hofstee wrote:
Hello Wolfgang,
On 06/21/2013 07:33 AM, Wolfgang Denk wrote:
We observed the very same issue with the verry first prototype
implementation of Falcon mode on an AM3517 based board. [..]
For the am3517 the only thing needed is
On Fri, Jun 21, 2013 at 10:56:33PM +0530, Kamaraj P wrote:
Hello All,
In my device tree blob, i would like to add some interrupt to the
protected-source list dynamically in the u-boot before launching the linux
kernel.
mpic: pic@4 {
interrupt-controller;
On 06/21/2013 12:26:33 PM, Kamaraj P wrote:
Hello All,
In my device tree blob, i would like to add some interrupt to the
protected-source list dynamically in the u-boot before launching the
linux
kernel.
mpic: pic@4 {
interrupt-controller;
#address-cells = 0;
On Fri, Jun 21, 2013 at 01:27:41PM -0500, Dan Murphy wrote:
This patch series has been generated in an effort to get comments on
the implementation of the dwc code within the uBoot.
The first patch is the one of major concern as this patch will make an
attempt to commonize the usb headers
Hello Daniel,
sorry for being late with my questions.
Daniel Schwierzeck wrote on 2013-06-09:
MIPS: bootm: refactor initialisation of kernel cmdline
MIPS: bootm: refactor initialisation of kernel environment
MIPS: bootm: make initialisation of Linux environment optional
MIPS: bootm:
On Thu, Apr 25, 2013 at 03:51:11PM +0800, Xie Xiaobo wrote:
TWR-P1025 Specification:
---
Memory subsystem:
512MB DDR3 (on board DDR)
64Mbyte 16bit NOR flash
One microSD Card slot
Ethernet:
eTSEC1: Connected to Atheros AR8035 GETH PHY
eTSEC3: Connected
On Mon, May 27, 2013 at 10:51:46AM +1200, Chris Packham wrote:
From: Chris Packham chris.pack...@alliedtelesis.co.nz
Instead of assuming that SYS_TEXT_BASE is 0xFFF8 calculate the initial
pbl command offset by subtracting the image size from the top of the
24-bit address range. Also
On Tue, May 07, 2013 at 04:30:50PM +0800, Liu Gang wrote:
When a T4 board boots from SRIO or PCIE, it needs to finish these processes:
1. Set all the cores in holdoff status.
2. Set the boot location to one PCIE or SRIO interface by RCW.
3. Set a specific TLB entry for the
On Thu, Jun 13, 2013 at 10:14:00AM +0530, Prabhakar Kushwaha wrote:
init_tlbs() initialize all the TLB entries required for the system.
So disable DEBUG TLB entry before TLB entries initialization.
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Applied, with fixes.
diff --git
On Mon, Apr 01, 2013 at 12:12:45PM +0530, Priyanka Jain wrote:
BSC9131RDB supports Sysclk
-66MHz if jumper J16 is close (default state)
-100MHz if jumper J16 is open
Add targets
-BSC9131RDB_NAND_SYSCLK100 : for NAND boot at Sysclk 100MHz
-BSC9131RDB_SPIFLASH_SYSCLK100: for SPI boot at
On Thu, Apr 04, 2013 at 02:40:32PM +0530, Priyanka Jain wrote:
BSC9131RDB has 1GB DDR.
Out of this, only 880MB is passed on to Linux via bootm_size.
Remaining
-16MB is reserved for PowerPC-DSP shared control area
-128MB is reserved for DSP private area.
Also 256MB, out of this 880MB is
On Fri, Apr 12, 2013 at 03:56:28PM +0800, Mingkai Hu wrote:
To avoid sign extension problem, use explicit casting to cast
the SDRAM size to type phys_size_t, or else, if the SDRAM size
is 2G(0x8000), it will be extended to 0x8000
when phys_size_t is type 'unsigned long long'.
On Tue, Apr 16, 2013 at 01:27:44PM +0530, Prabhakar Kushwaha wrote:
IFC errata A003399 is valid for IFC NOR boot i.e.if no on-board NOR flash or
no NOR boot, do not compile its workaround.
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Applied, thanks!
Andy
On Thu, Apr 04, 2013 at 09:31:54AM +0530, Priyanka Jain wrote:
BSC9131RDB is a Freescale Reference Design Board for
BSC9131 SoC which is a integrated device that contains
one powerpc e500v2 core and one DSP starcore.
To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
On Tue, Apr 16, 2013 at 01:27:59PM +0530, Prabhakar Kushwaha wrote:
Linker script is not able find start.o binary. So add its absolute path in
u-boot-spl.lds. This change is similar to u-boot-nand.lds
common/Makefile: Avoid compiling unnecssary files
fsl_ifc_spl.c : It is is responsible
On Tue, Apr 16, 2013 at 01:28:40PM +0530, Prabhakar Kushwaha wrote:
- Add NAND boot target
- defines contants
- Add spl_minimal.c to initialise DDR
- update TLB, LAW entries as per NAND boot
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Applied, thanks! Fixed typo.
On Tue, Apr 16, 2013 at 01:28:12PM +0530, Prabhakar Kushwaha wrote:
- defines contants
- Add spl_minimal.c to initialise DDR
- update TLB entries as per NAND boot
- remove nand_spl support for P1010RDB
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Applied, thanks! Fixed
On Tue, Apr 16, 2013 at 01:28:25PM +0530, Prabhakar Kushwaha wrote:
- Add NAND boot target
- defines contants
- Add spl_minimal.c to initialise DDR
- update TLB entries as per NAND boot
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Applied, thanks! Fixed typo
Andy
On Thu, Apr 18, 2013 at 07:31:01PM -0700, York Sun wrote:
BSC9132 has 3 IFC banks.
Signed-off-by: York Sun york...@freescale.com
Applied, thanks!
Andy
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On Sun, Apr 21, 2013 at 01:11:02PM -0300, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
Freescale documentation presents the PowerPC core names in lower case, such as
e300, e500, e600, etc.
Change the upper case occurrences into lower case so that the core names
On Tue, May 07, 2013 at 04:30:48PM +0800, Liu Gang wrote:
When a b4860qds board boots from SRIO or PCIE, it needs to finish these
processes:
1. Set all the cores in holdoff status.
2. Set the boot location to one PCIE or SRIO interface by RCW.
3. Set a specific TLB entry for
On Tue, May 07, 2013 at 04:30:47PM +0800, Liu Gang wrote:
B4860QDS can support the feature of Boot from SRIO/PCIE, and the macro
CONFIG_SRIO_PCIE_BOOT_MASTER will enable the master module of this feature
when building the u-boot image.
You can get some description about this macro in README
On Tue, May 07, 2013 at 11:19:55AM +0530, Prabhakar Kushwaha wrote:
e500v2 processor does not support 8K page size TLB entries.
So create new TLB entry only during NAND SPL boot.
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Applied, thanks!
Andy
On Tue, May 07, 2013 at 04:30:45PM +0800, Liu Gang wrote:
1. Misalignment will be found in the doc/README.srio-pcie-boot-corenet
file when the tabs are set to 8 characters. And the standard for
u-boot should be 8 character tabs! So this issue should be amended.
2. Add a NOTE for the
On Wed, May 15, 2013 at 05:50:13PM -0500, Scott Wood wrote:
Erratum A-006593 is Atomic store may report failure but still allow
the store data to be visible.
The workaround is: Set CoreNet Platform Cache register CPCHDBCR0 bit
21 to 1'b1. This may have a small impact on synthetic write
On Thu, May 16, 2013 at 10:18:13AM +0800, Mingkai Hu wrote:
From: Mingkai Hu mingkai...@freescale.com
Calculate reserved fields according to IFC bank count
1. Move csor_ext register behind csor register and fix res offset
2. Move ifc bank count to config_mpc85xx.h to support 8 bank count
On Fri, May 17, 2013 at 01:40:52PM +0530, Prabhakar Kushwaha wrote:
Relax parameters to give address latching more time to setup.
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Applied, thanks!
Andy
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On Tue, May 07, 2013 at 04:30:46PM +0800, Liu Gang wrote:
Currently, the macro CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER can enable
the master module of Boot from SRIO and PCIE on a platform. But this
is not a silicon feature, it's just a specific booting mode based on
the SRIO and PCIE interfaces.
On Tue, May 07, 2013 at 04:30:49PM +0800, Liu Gang wrote:
T4 can support the feature of Boot from SRIO/PCIE, and the macro
CONFIG_SRIO_PCIE_BOOT_MASTER will enable the master module of this feature
when building the u-boot image.
You can get some description about this macro in README file,
On Mon, May 20, 2013 at 02:07:23PM +0800, ying.zh...@freescale.com wrote:
From: Ying Zhang b40...@freescale.com
For SD/SPI 2-stage bootloader, the On-Chip Rom code loads the SPL into L2
SRAM,
then jump to it to begin execution. After that, the SPL loads the final uboot
image into DDR, then
On Fri, May 17, 2013 at 02:22:34PM +0530, Prabhakar Kushwaha wrote:
PCIe TLB should be created with CONFIG_PCI defined
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Applied, thanks!
Andy
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On Mon, May 20, 2013 at 02:07:25PM +0800, ying.zh...@freescale.com wrote:
From: Ying Zhang b40...@freescale.com
There will need the environment in SPL for reasons other than network
support (in particular, hwconfig contains info for how to set up DDR).
Add a new symbol
On Mon, May 20, 2013 at 02:07:26PM +0800, ying.zh...@freescale.com wrote:
From: Ying Zhang b40...@freescale.com
Move the common makefile line shared by the SPL and non-SPL to the public
area,
so that we can avoid excessive SPL symbols. Some of them will be used by the
SPL later.
This
On Sun, May 26, 2013 at 03:00:30PM +0800, Axel Lin wrote:
If a variable is used as array subscript, it's valid value range is
0 ... ARRAY_SIZE -1.
Signed-off-by: Axel Lin axel@ingics.com
Applied, thanks!
Andy
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On Fri, May 31, 2013 at 08:48:04AM -0700, York Sun wrote:
pixis_reset help command prints the message without a new line \n,
which makes the prompt on the same line.
Signed-off-by: York Sun york...@freescale.com
Applied, thanks!
Andy
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On Fri, Jun 14, 2013 at 04:21:48PM +0800, Chunhe Lan wrote:
P1023RDB Specification:
---
Memory subsystem:
512MB DDR3 (Fixed DDR on board)
64MB NOR flash
128MB NAND flash
Ethernet:
eTSEC1: Connected to Atheros AR8035 GETH PHY
eTSEC2: Connected to
The following changes since commit 7315cfd9e1922ee1c3c5f016e5a3b16199122172:
NET: Fix system hanging if NET device is not installed (2013-06-19 08:32:44
-0400)
are available in the git repository at:
git://www.denx.de/git/u-boot-mpc85xx.git master
for you to fetch changes up to
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