T2080QDS PEX1/Slot#1 will down-train from x4 to x2,
with SRDS_PRTCL_S1 = 0x66 and SRDS_PRTCL_S2 = 0x15.
Soft reset PCIe can fix this issue.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
changes for v2
- modify the commit message
changes for v3
- use CONFIG_FSL_PCIE_RESET
Hi,
On 25-03-15 23:35, Paul Kocialkowski wrote:
Le mardi 24 mars 2015 à 09:01 +0100, Hans de Goede a écrit :
Hi,
On 24-03-15 00:12, Rob Herring wrote:
On Mon, Mar 23, 2015 at 6:30 AM, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 22-03-15 22:01, Rob Herring wrote:
snip
There is
On Wed, 2015-03-25 at 16:49 -0400, Tom Rini wrote:
On Wed, Mar 25, 2015 at 08:54:16PM +0100, Sjoerd Simons wrote:
On Wed, 2015-03-25 at 12:58 -0400, Tom Rini wrote:
On Wed, Mar 25, 2015 at 09:32:45AM +0100, Sjoerd Simons wrote:
On Wed, 2015-03-25 at 01:11 -0400, Tom Rini wrote:
On
Please ignore my question because it is answered by [PATCH v2 34/80].
On 03/26/2015 11:38 AM, Jim Lin wrote:
-Original Message-
From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Simon Glass
Sent: Thursday, March 26, 2015 2:23 AM
To: U-Boot Mailing List
Cc: Marek Vasut;
Le jeudi 26 mars 2015 à 10:11 +0100, Paul Kocialkowski a écrit :
Le jeudi 26 mars 2015 à 09:53 +0100, Hans de Goede a écrit :
Hi,
On 25-03-15 23:35, Paul Kocialkowski wrote:
Le mardi 24 mars 2015 à 09:01 +0100, Hans de Goede a écrit :
Hi,
On 24-03-15 00:12, Rob Herring wrote:
defconfig files are added and SFP version for these platforms
is updated.
Signed-off-by: Gaurav Rana gaurav.r...@freescale.com
---
arch/powerpc/include/asm/config_mpc85xx.h | 1 +
arch/powerpc/include/asm/fsl_secure_boot.h | 2 ++
board/freescale/t104xrdb/MAINTAINERS | 2 ++
Hi Sebastian,
On 26/03/2015 09:02, Sebastian Andrzej Siewior wrote:
On 03/25/2015 04:53 PM, Stefano Babic wrote:
On 03/03/2015 17:45, Sebastian Andrzej Siewior wrote:
with WCR_WDW set, the watchdog won't trigger if we bootet linux and idle
around while the watchdog is not triggered. It seems
Le jeudi 26 mars 2015 à 09:53 +0100, Hans de Goede a écrit :
Hi,
On 25-03-15 23:35, Paul Kocialkowski wrote:
Le mardi 24 mars 2015 à 09:01 +0100, Hans de Goede a écrit :
Hi,
On 24-03-15 00:12, Rob Herring wrote:
On Mon, Mar 23, 2015 at 6:30 AM, Hans de Goede hdego...@redhat.com
On 3/26/2015 11:05 AM, Fan Peng-B51431 wrote:
Hi Haikun,
On 3/26/2015 10:39 AM, Wang Haikun-B53464 wrote:
On 3/25/2015 10:10 PM, Fan Peng-B51431 wrote:
Hi Haikun,
On 3/25/2015 8:35 PM, Haikun Wang wrote:
From: Haikun Wang haikun.w...@freescale.com
Atmel AT45DB series devices commands is
From: Andrej Rosano and...@inversepath.com
Move the MX5 based boards to arch/arm/cpu/armv7/mx5, following the
commit: 89ebc82137bebb11a8191f8b9cbf08f2533ae8bc
Signed-off-by: Andrej Rosano and...@inversepath.com
Cc: Stefano Babic sba...@denx.de
Cc: Vagrant Cascadian vagr...@debian.org
---
Reading the GPIOs for getting the boot mode does not show the correct result
for USB boot mode in case the recovery switch, eg. BM2 for switching from NAND
to USB boot mode, is hold down while plugging in USB and released before U-Boot
is loaded by mxsldr.
This state is stored in the
On 3/26/2015 6:50 PM, Wang Haikun-B53464 wrote:
On 3/26/2015 11:05 AM, Fan Peng-B51431 wrote:
Hi Haikun,
On 3/26/2015 10:39 AM, Wang Haikun-B53464 wrote:
On 3/25/2015 10:10 PM, Fan Peng-B51431 wrote:
Hi Haikun,
On 3/25/2015 8:35 PM, Haikun Wang wrote:
From: Haikun Wang
From: Andrej Rosano and...@inversepath.com
Hello,
this series adds support for USB armory board. The patches are
prepared against imx tree as it uses the new arch/board approach.
The first patch add introduces the arch/board approach for mx5,
as already done for mx6.
The second patch adds
From: Andrej Rosano and...@inversepath.com
Add support for Inverse Path USB armory board, an open source
flash-drive sized computer based on Freescale i.MX53 SoC.
http://inversepath.com/usbarmory
Signed-off-by: Andrej Rosano and...@inversepath.com
Cc: Stefano Babic sba...@denx.de
Cc: Chris
Hello,
On 03/24/2015 07:01 AM, Heiko Schocher wrote:
Hello Simon, Przemyslaw,
Am 24.03.2015 00:38, schrieb Simon Glass:
Hi Przemyslaw,
On 10 March 2015 at 04:30, Przemyslaw Marczak p.marc...@samsung.com
wrote:
This change adds driver model support to software emulated
i2c bus driver. To
Hello Masahiro,
On 03/25/2015 04:35 AM, Masahiro Yamada wrote:
Hi.
2015-03-10 19:30 GMT+09:00 Przemyslaw Marczak p.marc...@samsung.com:
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Masahiro Yamada yamad...@jp.panasonic.com
I am no longer working for Panasonic.
The old email
Hello Simon,
On 03/24/2015 12:38 AM, Simon Glass wrote:
Hi Przemyslaw,
On 10 March 2015 at 04:30, Przemyslaw Marczak p.marc...@samsung.com wrote:
This change adds driver model support to software emulated
i2c bus driver. To bind the driver, proper device-tree node
must be defined, with the
Hello Simon,
On 03/24/2015 12:39 AM, Simon Glass wrote:
Hi,
On 10 March 2015 at 04:30, Przemyslaw Marczak p.marc...@samsung.com wrote:
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Masahiro Yamada yamad...@jp.panasonic.com
Cc: Mike Frysinger vap...@gentoo.org
Cc: Simon Glass
Hi,
On 25-03-15 17:03, Iain Paton wrote:
board/sunxi/board.c tries to set ldo3 to 2.8v however drivers/power/axp209.c
contains an incorrect limit on ldo3 of 2.275v
The origin of the incorrect limit seems likely due to some inconsistencies
in the axp209 datasheet. ldo3 is described with
Hi,
On 25-03-15 14:39, Ian Campbell wrote:
Of 4 boards in our automated test system 2 do not have reliable
networking with the default TX delay of 0x0. Increasing to 0x1 seems
to make things reliable on all 4 boards.
Some previous ad-hpoc tests with tx delay set to 0, 1, 2 and 3 on one
of the
Hi Jörg,
On 26/03/2015 10:39, Jörg Krause wrote:
Reading the GPIOs for getting the boot mode does not show the correct result
for USB boot mode in case the recovery switch, eg. BM2 for switching from NAND
to USB boot mode, is hold down while plugging in USB and released before
U-Boot
is
Hi Tom,
Please pull u-boot-sunxi/master into master for a small 2 bugfixes
for v2015.04:
The following changes since commit f643d9294f45487f22e8f33d6572530f17eff4e9:
config_distro_bootcmd.h: Prefer booting from bootable paritions (2015-03-25
12:15:18 -0400)
are available in the git
Hello, Dave
On 3/26/2015 4:45 PM, Rajiv Dave wrote:
Hi,
We are using an Atmel AT91SAM9263 processor which supports 1 Bit ECC flash
devices that have Block 0 Valid with no ECC. These devices are now obsolete.
We have fitted a board with a MT29F2G08ABAEWP-E-E, which has an internal
Hardware ECC
Define CONFIG_DEFAULT_DEVICE_TREE for ls1021a series boards.
Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
configs/ls1021aqds_ddr4_nor_defconfig| 1 +
configs/ls1021aqds_nand_defconfig| 1 +
configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 1 +
From: Haikun Wang haikun.w...@freescale.com
Enable Driver Model SPI for ls1021aqds board.
DSPI and QSPI are compatible under Driver Model SPI.
Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
include/configs/ls1021aqds.h | 14 +-
1 file changed, 13 insertions(+), 1
From: Haikun Wang haikun.w...@freescale.com
Enable Driver Model SPI for ls1021atwr board.
DSPI and QSPI are compatible under Driver Model SPI.
Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
include/configs/ls1021atwr.h | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
Freescale PCIe controllers v3.0 and later need to set bit
CFG_READY to allow all inbound configuration transactions
to be processed normally when in EP mode. However, bit
CFG_READY has been moved from PCIe configuration space to
CCSR PCIe configuration register comparing previous version.
The
On 03/26/2015 06:31 PM, Marcel Ziswiler wrote:
Fix FUNCMUX_NDFLASH_KBC_8_BIT and pingroup ATC clashing.
Please note that the first patch has already been submitted once but
based on feedback from Stephen I now split it up into a generic fix
part plus a board specific ATC pingroup clashing
This adjusts (micro)frame length to appropriate value thus
avoiding USB devices to time out over a longer run
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
Depends on fsl/usb: Add USB XHCI support
http://patchwork.ozlabs.org/patch/373593/
drivers/usb/host/xhci-fsl.c | 9
On Thu, Mar 26, 2015 at 4:11 AM, Paul Kocialkowski cont...@paulk.fr wrote:
Le jeudi 26 mars 2015 à 09:53 +0100, Hans de Goede a écrit :
Hi,
On 25-03-15 23:35, Paul Kocialkowski wrote:
Le mardi 24 mars 2015 à 09:01 +0100, Hans de Goede a écrit :
Hi,
On 24-03-15 00:12, Rob Herring wrote:
Oleks,
Each patch should be sent as a separated plain text email, not an attachment.
without MIME encoding. The point is reviewers can reply and comment in line.
You see when I reply your email, the attachment is lost. Try to use git
send-email utility. It would be a good idea to send to
On 26 March 2015 15:18:56 CET, Stephen Warren swar...@wwwdotorg.org wrote:
I assume all the white-space and line reordering changes are so that a
diff of colibri_t20.h and colibri_t30.h shows minimal differences?
Exactly.
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PING
It might warrant
Hi,
First of all I'm not sure this is a regression, but I'm afraid
I do not have time to dig deeper so I thought I should report
it anyways and then others can try to reproduce it.
I'm seeing the following happen when using a usb stick
with a musb-new otg controller in host mode on an allwinner
clock divisors table was missing an entry for 912MHz. The same table is
used for sun7i where the default boot clock is 912MHz, resulting in A20
boards being overclocked to 960MHz
Signed-off-by: Iain Paton ipat...@gmail.com
---
arch/arm/cpu/armv7/sunxi/clock_sun4i.c | 1 +
1 file changed, 1
in order to allow for this to be set differently per board, remove the
define from the associated soc headers and allow the user to choose a
value through a Kconfig setting
Signed-off-by: Iain Paton ipat...@gmail.com
---
board/sunxi/Kconfig | 8
include/configs/sun4i.h | 1 -
following kernel patches to reduce the cpu clock to 912MHz due to reported
instability at 1008MHz, select 912MHz as the boot speed for the a10-lime
Signed-off-by: Iain Paton ipat...@gmail.com
---
configs/A10-OLinuXino-Lime_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git
On Thu, 2015-03-26 at 17:16 -0400, Oleksandr G Zhadan wrote:
From: Oleksandr Zhadan ol...@arcturusnetworks.com
Signed-off-by: Oleksandr Zhadan ol...@arcturusnetworks.com
Signed-off-by: Michael Durrant mdurr...@arcturusnetworks.com
---
arch/powerpc/include/asm/arch-mpc85xx/gpio.h |2
Fix FUNCMUX_NDFLASH_KBC_8_BIT and pingroup ATC clashing.
Please note that the first patch has already been submitted once but
based on feedback from Stephen I now split it up into a generic fix
part plus a board specific ATC pingroup clashing workaround. That's why
I call this series already v2
Pingroup ATC seems to come out of reset with config set to NAND, so we
need to explicitly configure some other function to this group in order
to avoid clashing settings.
Signed-off-by: Marcel Ziswiler mar...@ziswiler.com
---
board/toradex/colibri_t20/colibri_t20.c | 6 ++
1 file changed, 6
From: Lucas Stach d...@lynxeye.de
Even the 8-bit case needs KBCB configured, as pin D7 is located in this
pingroup.
Please note that pingroup ATC seems to come out of reset with its
config set to NAND so one needs to explicitly configure some other
function to this group in order to avoid
On 25/03/15 17:58, Tom Rini wrote:
On Wed, Mar 25, 2015 at 01:07:47PM +0900, Chanwoo Choi wrote:
Hi Kamil,
I tested this patch-set in STM32 Discovery board. After applied this
patch-set on latest u-boot, I could not see the normal u-boot log. I
saw broken console log. I used the USART1 port
On Wednesday, March 25, 2015 at 07:22:03 PM, Simon Glass wrote:
This CONFIG is not used anywhere in U-Boot, so drop it.
Signed-off-by: Simon Glass s...@chromium.org
Acked-by: Marek Vasut ma...@denx.de
Best regards,
Marek Vasut
___
U-Boot mailing
On Wednesday, March 25, 2015 at 07:21:48 PM, Simon Glass wrote:
This series adds driver model support to USB. The intent is to permit the
various subsystems (OHCI, EHCI, XHCI) to co-exist and allow any number of
USB ports of different types.
With the RFC series, only USB controllers had a
On Thu, Mar 26, 2015 at 4:49 AM, and...@inversepath.com wrote:
From: Andrej Rosano and...@inversepath.com
Move the MX5 based boards to arch/arm/cpu/armv7/mx5, following the
commit: 89ebc82137bebb11a8191f8b9cbf08f2533ae8bc
Signed-off-by: Andrej Rosano and...@inversepath.com
Cc: Stefano
On Thu, Mar 26, 2015 at 4:49 AM, and...@inversepath.com wrote:
From: Andrej Rosano and...@inversepath.com
Hello,
this series adds support for USB armory board. The patches are
prepared against imx tree as it uses the new arch/board approach.
The first patch add introduces the arch/board
On Thu, 2015-03-26 at 15:52 +0530, Gaurav Rana wrote:
defconfig files are added and SFP version for these platforms
is updated.
Signed-off-by: Gaurav Rana gaurav.r...@freescale.com
---
arch/powerpc/include/asm/config_mpc85xx.h | 1 +
arch/powerpc/include/asm/fsl_secure_boot.h | 2 ++
On 2015-03-26, and...@inversepath.com wrote:
From: Andrej Rosano and...@inversepath.com
Add support for Inverse Path USB armory board, an open source
flash-drive sized computer based on Freescale i.MX53 SoC.
http://inversepath.com/usbarmory
Tested-By: Vagrant Cascadian vagr...@debian.org
On 03/26/2015 02:16 PM, Oleksandr G Zhadan wrote:
From: Oleksandr Zhadan ol...@arcturusnetworks.com
Please add commit message to explain why and what you are changing.
Signed-off-by: Oleksandr Zhadan ol...@arcturusnetworks.com
Signed-off-by: Michael Durrant mdurr...@arcturusnetworks.com
On 03/26/2015 02:14 PM, Oleksandr G Zhadan wrote:
From: Oleksandr Zhadan ol...@arcturusnetworks.com
Please add commit message to explain what you are doing.
Please run checkpatch before sending it. You have tons of issues there.
York
___
U-Boot
Reading the boot mode pins after power-up does not necessarily represent the
boot mode used by the ROM loader. For example the state of a pin may have
changed because a recovery switch which was pressed to enter USB mode is
already released after plugging in USB.
The ROM loader stores the value a
On Do, 2015-03-26 at 10:39 +0100, Jörg Krause wrote:
Reading the GPIOs for getting the boot mode does not show the correct result
for USB boot mode in case the recovery switch, eg. BM2 for switching from NAND
to USB boot mode, is hold down while plugging in USB and released before
U-Boot
is
On Thu, Mar 26, 2015 at 3:23 PM, Andrej Rosano and...@inversepath.com wrote:
Please note that the patch is prepared against imx tree and not the
mainline one, where the arch/board approach is not yet merged.
OK, it all works for me.
--
GDB has a 'break' feature; why doesn't it have 'fix'
Hi Chris,
On Thu, Mar 26, 2015 at 02:53:58PM -0700, Chris Kuethe wrote:
On Thu, Mar 26, 2015 at 4:49 AM, and...@inversepath.com wrote:
From: Andrej Rosano and...@inversepath.com
Hello,
this series adds support for USB armory board. The patches are
prepared against imx tree as it
From: Oleksandr Zhadan ol...@arcturusnetworks.com
Signed-off-by: Oleksandr Zhadan ol...@ivyking.arcturusnetworks.com
Signed-off-by: Michael Durrant mdurr...@arcturusnetworks.com
---
arch/powerpc/cpu/mpc85xx/Kconfig |4 +
board/Arcturus/ucp1020/Kconfig | 44 ++
Hi all,
I just tried to build the latest master mainline u-boot for a xilinx zynq
7010 board called the red pitaya. I'm not affiliated at all with the board,
just trying to use it with a recent version of u-boot (and linux).
Unfortunately it gets stuck in a reset loop (I wasn't able to nail down
Hi Hannes,
On 03/25/2015 11:24 PM, Hannes Petermaier wrote:
+static void console_calc_rowcol(struct console_t *pcons)
+{
+pcons-cols = pcons-lcdsizex / VIDEO_FONT_WIDTH;
+#if defined(CONFIG_LCD_LOGO) !defined(CONFIG_LCD_INFO_BELOW_LOGO)
+pcons-rows = (pcons-lcdsizey - BMP_LOGO_HEIGHT);
From: Oleksandr Zhadan ol...@arcturusnetworks.com
Signed-off-by: Oleksandr Zhadan ol...@arcturusnetworks.com
Signed-off-by: Michael Durrant mdurr...@arcturusnetworks.com
---
arch/powerpc/include/asm/arch-mpc85xx/gpio.h |2 ++
arch/powerpc/include/asm/mpc85xx_gpio.h |6 --
2
Hi,
We are using an Atmel AT91SAM9263 processor which supports 1 Bit ECC flash
devices that have Block 0 Valid with no ECC. These devices are now obsolete.
We have fitted a board with a MT29F2G08ABAEWP-E-E, which has an internal
Hardware ECC engine. Would you know how provide support for this
Masahiro Yamada (2):
kbuild: merge generic-asm-offsets.h and asm-offsets.h rules
kbuild: remove redundant line from (generic-)asm-offsets.h
Michal Marek (1):
kbuild: Don't reset timestamps in include/generated if not needed
Kbuild | 73
The rules cmd_generic-offsets and cmd_offsets are almost the
same. (The difference is only the include guards.)
They can be merged.
This commit is mostly inspired by the following commit of Linux.
commit 39664e2f3cdef98f42437e903159a6044a1d99d6
Author: Masahiro Yamada
From: Masahiro Yamada yamad...@jp.panasonic.com
This line produces an extra comment line for generic-asm-offsets.h
and asm-offsets.h.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
Signed-off-by: Michal Marek mma...@suse.cz
[ imported from Linux Kernel, commit 343d3e6cc861,
with
From: Michal Marek mma...@suse.cz
Use filechk to generate asm-offsets.h and generic-asm-offsets.h.
Based on a patch by Valdis Kletnieks.
Reported-by: Valdis Kletnieks valdis.kletni...@vt.edu
Acked-by: Valdis Kletnieks valdis.kletni...@vt.edu
Reviewed-by: Masahiro Yamada
The SD clock could be generated by platform clock or peripheral
clock for some platforms. This patch adds peripheral clock
support for kernel for T1024/T1040/T2080. To enable it,
define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK.
Signed-off-by: Yangbo Lu yangbo...@freescale.com
Cc: York Sun
Add adapter card type identification support by reading
FPGA STAT_PRES1 register SDHC Card ID[0:2] bits. To use this function,
define CONFIG_FSL_ESDHC_ADAPTER_IDENT.
Signed-off-by: Yangbo Lu yangbo...@freescale.com
Cc: York Sun york...@freescale.com
---
arch/powerpc/include/asm/global_data.h |
Enable eSDHC adapter card type identification and this will do
some corresponding operations and set 'adapter-type' property
for device tree according SDHC Card ID.
Signed-off-by: Yangbo Lu yangbo...@freescale.com
Cc: York Sun york...@freescale.com
---
include/configs/T208xQDS.h | 1 +
1 file
Enable eSDHC peripheral clock support for kernel, and linux will
use SD clock generated by peripheral clock instead of platform
clock.
Signed-off-by: Yangbo Lu yangbo...@freescale.com
Cc: York Sun york...@freescale.com
---
include/configs/T208xQDS.h | 1 +
1 file changed, 1 insertion(+)
diff
On 25/03/2015 21:24, Vagrant Cascadian wrote:
On 2015-03-25, Stefano Babic wrote:
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b9ebee1..a490084 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -462,6 +462,10 @@ config TARGET_MX53SMD
bool Support mx53smd
select
On 03/25/2015 04:53 PM, Stefano Babic wrote:
On 03/03/2015 17:45, Sebastian Andrzej Siewior wrote:
with WCR_WDW set, the watchdog won't trigger if we bootet linux and idle
around while the watchdog is not triggered. It seems the timer makes
progress very slowly if at all. I managed to remain
On x86 systems this device is commonly used to provide legacy port access.
It is sort-of a replacement for the old ISA bus.
Add a uclass for this, and allow it to have child devices.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/lib/Makefile | 1 +
This code appears to be missing a piece that is needed on some keyboards
to enable the keyboard. Add this in.
This makes the keyboard work correctly on chromebook_link.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Rebase to dm/next
drivers/input/i8042.c | 7 +++
1
This command is supposed to reinit the device. At present with driver
model is does nothing. Implement this feature.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/misc/cros_ec.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git
This is not needed now that we have moved to driver model.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
include/fdtdec.h | 1 -
lib/fdtdec.c | 1 -
2 files changed, 2 deletions(-)
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 814be1c..a5f4bcd 100644
---
This is the last driver to be converted. It requires an LPC bus and a
special check_version() method.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Support pre-driver-model too so we can rebase on dm/next
configs/chromebook_link_defconfig | 1 +
drivers/misc/cros_ec.c
The U-Boot device trees are slightly different in a few places. Adjust them
to remove most of the differences. Note that U-Boot does not support the
concept of interrupts as distinct from GPIOs, so this difference remains.
For sandbox, use the same keyboard file as for ARM boards and drop the
This is not needed now that we have moved chromebook_link and cros_ec to
driver model.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
include/fdtdec.h | 1 -
lib/fdtdec.c | 1 -
2 files changed, 2 deletions(-)
diff --git a/include/fdtdec.h b/include/fdtdec.h
index
Move CONFIG_CROS_EC_SANDBOX to Kconfig.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Add new patch to move CONFIG_CROS_EC_SANDBOX to Kconfig
drivers/misc/Kconfig | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index
Oleks,
Please resend the patches in plain text to the mailing list so reviewers can
comment inline.
Thanks.
York
On 03/26/2015 07:58 AM, Oleksandr G Zhadan wrote:
Hi,
Please review and add next patches:
[PATCH 1/2] Modify MPC85XX gpio related header files to fix common/cmd_gpio.c
Convert this driver over to use driver model. Since all x86 platforms use
it, move x86 to use driver model for SPI and SPI flash. Adjust all dependent
code and remove the old x86 spi_init() function.
Note that this does not make full use of the new PCI uclass as yet. We still
scan the bus looking
Since driver model will probe the EC when it is first used, we do not
need to init it explicitly.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
board/coreboot/coreboot/coreboot.c | 5 -
board/google/chromebook_link/link.c | 3 ---
2 files changed, 8 deletions(-)
At present x86 does not use driver model for SPI or LPC (low-pin-count, a
bus used to talk to the EC on Chromebooks).
This series:
- moves the ICH SPI driver over to driver model
- moves the cros_ec LPC driver to driver model
- removes non-driver-model cros_ec code (since now I2C, SPI and LPC are
On 03/25/2015 07:17 PM, Marcel Ziswiler wrote:
Bring the Colibri T20 configuration in-line with Apalis/Colibri T30.
I assume all the white-space and line reordering changes are so that a
diff of colibri_t20.h and colibri_t30.h shows minimal differences?
diff --git
The PCH (Platform Controller Hub) is on the PCI bus, so show it as such.
The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the
right place also.
Rename the compatible strings to be more descriptive since this board is the
only user. Once we are using driver model fully on
Now that driver model handles cros_ec init, we can drop this special code.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
common/cros_ec.c | 5 -
include/cros_ec.h | 7 ---
2 files changed, 12 deletions(-)
diff --git a/common/cros_ec.c b/common/cros_ec.c
index
Since all supported boards enable this option now, we can remove it along
with the old code.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/sandbox/Kconfig | 3 -
board/samsung/smdk5420/Kconfig | 6 --
common/cros_ec.c | 30 +-
Permit use of a udevice to talk to SPI flash. Ultimately we would like
to retire the use of 'struct spi_flash' for this purpose, so create the
new API for those who want to move to it.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/mtd/spi/sf-uclass.c | 16
On 03/25/2015 07:17 PM, Marcel Ziswiler wrote:
Fix ASIX USB to Ethernet chip reset.
Acked-by: Stephen Warren swar...@nvidia.com
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On 03/25/2015 06:31 PM, Marcel Ziswiler wrote:
In accordance with our other modules supported by U-Boot and as agreed
upon for Apalis/Colibri T30 [1] get rid of the carrier board post fix
in the board/configuration/device-tree naming.
[1]
Add a simple uclass for this chip which is often found in x86 systems
where the CPU is a separate device.
The device can have children, so make it scan the device tree for these.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/cpu/ivybridge/bd82x6x.c | 9
Since driver model will probe the EC when it is first used, we do not
need to init it explicitly.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
board/samsung/common/board.c| 12
include/configs/exynos5420-common.h | 2 --
include/configs/smdk5250.h
Since driver model will probe the EC when it is first used, we do not
need to init it explicitly.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
board/sandbox/sandbox.c | 12
include/configs/sandbox.h | 1 -
2 files changed, 13 deletions(-)
diff --git
On Thu, Mar 26, 2015 at 02:47:17PM +0100, Kamil Lulko wrote:
On 25/03/15 17:58, Tom Rini wrote:
On Wed, Mar 25, 2015 at 01:07:47PM +0900, Chanwoo Choi wrote:
Hi Kamil,
I tested this patch-set in STM32 Discovery board. After applied this
patch-set on latest u-boot, I could not see the normal
Hi Stefano,
On Do, 2015-03-26 at 13:31 +0100, Stefano Babic wrote:
Hi Jörg,
On 26/03/2015 10:39, Jörg Krause wrote:
Reading the GPIOs for getting the boot mode does not show the correct result
for USB boot mode in case the recovery switch, eg. BM2 for switching from
NAND
to USB boot
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