Add README.nios2 about how to add nios2 boards to u-boot.
Signed-off-by: Thomas Chou
Acked-by: Marek Vasut
---
v2
add ref and fix words as suggested by Marek.
v3
add a dollar sign before a command.
remove u-boot,dm-pre-reloc property. it is not needed
On Mon, Oct 19, 2015 at 12:48:35PM +0200, Stefan Roese wrote:
> Hi Maxime,
>
> On 18.10.2015 11:34, Maxime Ripard wrote:
> >>On 01-10-15 11:41, Stefan Roese wrote:
> >>>The ICnova-A20-SWAC is a baseboard, equipped with the ICnova-A20 SoM from
> >>>In-Circuit:
> >>>
>
Hi Ryan,
On 21.10.2015 15:48, Ryan Harkin wrote:
Perhaps also the "c", "w", "l" and "ll" in "cword" should be renamed
to "u8", "u16", "u32" and "u64"? We aren't actually looking for a
"char" in this file, but an 8 bit value, for example.
Correct. But I suspect that u8 etc will not be
On Wed, Oct 21, 2015 at 06:38:23PM +0530, Vignesh R wrote:
> Hi Lokesh,
>
> On 10/21/2015 06:10 PM, Lokesh Vutla wrote:
> > Hi Vignesh,
> >
> > On Wednesday 21 October 2015 10:10 AM, Vignesh R wrote:
> >> This adds support to update firmware on qspi flash present on
> >> am437x-sk-evm and
On Wed, Oct 21, 2015 at 08:05:33AM -0500, George McCollister wrote:
> Advantech SOM-6896 is a Broadwell U based COM Express Compact Module
> Type 6. This patch adds support for it as a coreboot payload.
>
> On board SATA and SPI are functional. On board Ethernet isn't functional
> but since it's
On 21 October 2015 at 13:49, Ryan Harkin wrote:
> On 21 October 2015 at 13:40, Stefan Roese wrote:
>> Hi Ryan,
>>
>> On 21.10.2015 13:34, Ryan Harkin wrote:
>>>
>>> On 21 October 2015 at 11:24, Stefan Roese wrote:
Hi Ryan,
On Mon, Oct 12, 2015 at 03:43:01PM +0200, Maxime Ripard wrote:
> Hi,
>
> I'm currently writing the support in U-Boot for NAND-backed devices
> using fastboot [1], and that work derived a bit to supporting the
> sparse images.
>
> For "regular" images that are being stored, we expect a pair of
>
Advantech SOM-6896 is a Broadwell U based COM Express Compact Module
Type 6. This patch adds support for it as a coreboot payload.
On board SATA and SPI are functional. On board Ethernet isn't functional
but since it's optional and ties up a PCIe x4 that is otherwise brought
out, this isn't a
Hi Maxime,
On 21.10.2015 16:31, Maxime Ripard wrote:
On 18.10.2015 11:34, Maxime Ripard wrote:
On 01-10-15 11:41, Stefan Roese wrote:
The ICnova-A20-SWAC is a baseboard, equipped with the ICnova-A20 SoM from
In-Circuit:
http://wiki.in-circuit.de/index.php5?title=ICnova_A20_SODIMM
add missing definitions for the ubi/ubifs sync
with linux 4.2, also change "#define kfree ..."
into a static inline, so prevent ubi compile error:
CC drivers/mtd/ubi/fastmap.o
drivers/mtd/ubi/fastmap.c: In function 'scan_pool':
drivers/mtd/ubi/fastmap.c:475:3: error: called object 'free'
sync ubi,ubifs code in U-Boot with linux 4.2
commit 64291f7db5bd8150a74ad2036f1037e6a0428df2
Author: Linus Torvalds
Date: Sun Aug 30 11:34:09 2015 -0700
Linux 4.2
This update is needed, as it turned out, that fastmap
was in experimental/broken state in
On Wed, Oct 21, 2015 at 9:10 PM, Thomas Chou wrote:
> As the virtual address and physical address mapping of nios2 with
> MMU are different. Add a check of MMU, and fix the mapping.
>
> Signed-off-by: Thomas Chou
> ---
> arch/nios2/include/asm/io.h |
The PEB array is an array of __be32, so let's fix the
scan_pool() prototype accordingly.
Signed-off-by: Ezequiel Garcia
Signed-off-by: Heiko Schocher
---
only repost this patch, as it belongs into this serie
drivers/mtd/ubi/fastmap.c | 4 ++--
1
Hello Simon,
On Mon, 19 Oct 2015 06:49:56 -0600, Simon Glass
wrote:
> This function will be used by both SPL and U-Boot proper. So move it into
> a common place. Also change the #ifdef so that the early malloc() area is
> not set up in SPL if CONFIG_SYS_SPL_MALLOC_START is
On 10/05/2015 04:58 PM, Stephen Warren wrote:
From: Stephen Warren
Implement the procedure that the TRM mandates to initialize PLLREFE and
PLLE. This makes the PLL actually lock.
Note that this section of the TRM is being cleaned up to remove some
confusion. The set of
On 10/19/2015 04:58 AM, Gong Qianyu wrote:
> From: Gong Qianyu
>
> get_clocks() should not be limited by ESDHC.
>
> Signed-off-by: Gong Qianyu
> ---
> V6:
> - No change.
> V5:
> - No change.
> V4:
> - No change.
> V3:
> - Removed
On 10/20/2015 03:31 PM, Tom Warren wrote:
This is the normal Tegra SPI driver modified to work with the
QSPI controller in Tegra210. It does not do 2x/4x transfers
or any other QSPI protocol.
Author: Yen Lin
Signed-off-by: Yen Lin
Signed-off-by: Tom Warren
Stephen,
-Original Message-
From: Stephen Warren [mailto:swar...@wwwdotorg.org]
Sent: Wednesday, October 21, 2015 9:52 AM
To: Tom Warren
Cc: u-boot@lists.denx.de; jt...@openedev.com; Stephen Warren
; tomcwarren3...@gmail.com
Subject: Re: [U-Boot]
On 21 October 2015 at 16:25, Hoefle Marco wrote:
>
> Hello,
> I saw that here is also a mailing list dedicated to device model issues but
> it looks obsolete (last post February 2014) so I am using this forum.
Please note its driver model - not a device model.
>
>
On 10/05/2015 12:08 PM, Stephen Warren wrote:
From: Stephen Warren
The implementation of noncached_init() uses define MMU_SECTION_SIZE.
Define this on ARM64.
Move the prototype of noncached_{init,alloc}() to a location that
doesn't depend on !defined(CONFIG_ARM64).
Note
On 10/03/2015 08:30 AM, Simon Glass wrote:
On 3 October 2015 at 00:44, Stephen Warren wrote:
From: Stephen Warren
PCI addresses are always represented as 3 cells in DT. (one cell for bus
and device, and two cells for a 64-bit addres). This does not
Stephen,
-Original Message-
From: Stephen Warren [mailto:swar...@wwwdotorg.org]
Sent: Wednesday, October 21, 2015 9:40 AM
To: Tom Warren
Cc: u-boot@lists.denx.de; Simon Glass ; Stephen Warren
; Thierry Reding
On 21 October 2015 at 22:10, Hoefle Marco wrote:
> Hello Jagan,
> Thank you for your reply.
> Please find my comments bellow. I missed to mention that I am using mainline
> 2015.07
>
>
>> -Original Message-
>> From: Jagan Teki [mailto:jt...@openedev.com]
>>
On 10/05/2015 10:45 AM, Joe Hershberger wrote:
On Fri, Oct 2, 2015 at 6:44 PM, Stephen Warren wrote:
From: Stephen Warren
Casting from dev->priv to pci_dev_t changes the value's size on a 64-bit
system. This causes the compiler to complain about
Hi Siarhei
On 21 October 2015 at 07:28, Siarhei Siamashka
wrote:
> On Mon, 31 Aug 2015 00:33:16 +0530
> Anand Moon wrote:
>
>> At the last moment I got this to work on my odroidxu3 board.
>>
>> One problem I would like to address out is usb
Hi Siarhei ,
On 21 October 2015 at 07:28, Siarhei Siamashka
wrote:
> On Mon, 31 Aug 2015 00:33:16 +0530
> Anand Moon wrote:
>
>> At the last moment I got this to work on my odroidxu3 board.
>>
>> One problem I would like to address out is usb
Hello,
I saw that here is also a mailing list dedicated to device model issues but it
looks obsolete (last post February 2014) so I am using this forum.
I have a problem nearly identically to
http://lists.denx.de/pipermail/u-boot/2015-April/210754.html
The SPI initialization does not work:
On 10/05/2015 05:00 PM, Stephen Warren wrote:
From: Stephen Warren
Tegra peripherals can generally access a 32-bit physical address space,
and I believe this applies to PCIe. Clip the PCI region that refers to
DRAM so it fits into 32-bits to avoid issues.
Tom,
Is this
Hello Jagan,
Thank you for your reply.
Please find my comments bellow. I missed to mention that I am using mainline
2015.07
> -Original Message-
> From: Jagan Teki [mailto:jt...@openedev.com]
> Sent: Mittwoch, 21. Oktober 2015 18:28
> To: Hoefle Marco
> Cc:
On 10/05/2015 05:02 PM, Stephen Warren wrote:
From: Stephen Warren
Tegra210's PCI controller is largely identical to Tegra124, and hence
shares the same binding. However, it has a unique compatible value due
to the existence of at least one new HW bug that would prevent any
On 10/05/2015 04:59 PM, Stephen Warren wrote:
From: Stephen Warren
A future patch will soon move some of the XUSB padctl code into a common
file in arch/arm/mach-tegra. Rename the existing dummy XUSB padctl file
to avoid conflicting with that, or being confusing.
Tom,
Is
On 10/19/2015 04:58 AM, Gong Qianyu wrote:
> From: Mingkai Hu
>
> Config Security Level Register is different between different SoCs,
> so put the CSL register definition into the arch specific directory.
>
> Signed-off-by: Mingkai Hu
>
On 10/21/2015 10:58 AM, Tom Warren wrote:
Stephen Warren wrote atWednesday, October 21, 2015 9:52 AM:
On 10/20/2015 03:31 PM, Tom Warren wrote:
This is the normal Tegra SPI driver modified to work with the QSPI
controller in Tegra210. It does not do 2x/4x transfers or any other
QSPI protocol.
On 10/17/2015 11:50 AM, Simon Glass wrote:
This function looks up the controller and returns a pointer to each region
type.
Patches 6, 7,
Acked-by: Stephen Warren
___
U-Boot mailing list
U-Boot@lists.denx.de
On 10/17/2015 11:49 AM, Simon Glass wrote:
This is not supported with driver model, so print a message instead of
generating a build error. Rescanning PCI is not yet implemented.
diff --git a/common/cmd_pci.c b/common/cmd_pci.c
@@ -457,7 +457,11 @@ static int do_pci(cmd_tbl_t *cmdtp, int
On 10/17/2015 11:50 AM, Simon Glass wrote:
Provide a few functions to support using 32-bit access to emulate 8- and
16-bit access.
Reviewed-by: Stephen Warren
___
U-Boot mailing list
U-Boot@lists.denx.de
On 10/17/2015 11:50 AM, Simon Glass wrote:
SDRAM doesn't always start at 0. Adjust the region mapping so that it works
on platforms where SDRAM is somewhere else.
This needs testing on other platforms.
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
@@ -729,8 +729,11 @@
On 10/17/2015 11:49 AM, Simon Glass wrote:
Move this option to Kconig and fix up all users.
What are your thoughts on how/when to merge this? The series (mainly the
final patch) conflicts with my series to add Tegra210 support, plus one
of them needs rebasing onto the other so that either
On 10/17/2015 11:50 AM, Simon Glass wrote:
At present we add a new resource entry for every range entry. But some range
entries refer to configuration regions. To make this work, avoid adding two
regions of the same time. The later ranges will overwrite the earlier
(configuration) ones.
On 10/17/2015 11:50 AM, Simon Glass wrote:
Adjust the Tegra PCI driver to support driver model and move all boards over
at the same time. This can make use of some generic driver model code, such
as the range decoding logic.
FYI, this patch has quite a few conflicts with my series to add
On Wed, Oct 21, 2015 at 04:57:04PM +0200, Maxime Ripard wrote:
> Hi Tom,
>
> On Tue, Oct 20, 2015 at 03:46:36PM -0400, Tom Rini wrote:
> > On Thu, Oct 15, 2015 at 02:34:17PM +0200, Maxime Ripard wrote:
> >
> > > So far the fastboot code was only supporting MMC-backed devices for its
> > >
Hi Stephen,
On 21 October 2015 at 10:31, Stephen Warren wrote:
>
> On 10/03/2015 08:30 AM, Simon Glass wrote:
>>
>> On 3 October 2015 at 00:44, Stephen Warren wrote:
>>>
>>> From: Stephen Warren
>>>
>>> PCI addresses are always
Hi,
On 20 October 2015 at 07:05, Rob Herring wrote:
> On Tue, Oct 20, 2015 at 3:15 AM, Linus Walleij
> wrote:
>> On Tue, Oct 20, 2015 at 10:10 AM, Linus Walleij
>> wrote:
>>> On Mon, Oct 19, 2015 at 9:21 PM, Rob Herring
Hi Stephen,
On Wed, Oct 21, 2015 at 11:32 AM, Stephen Warren wrote:
> On 10/05/2015 10:45 AM, Joe Hershberger wrote:
>>
>> On Fri, Oct 2, 2015 at 6:44 PM, Stephen Warren
>> wrote:
>>>
>>> From: Stephen Warren
>>>
>>> Casting
Stephen,
> -Original Message-
> From: Stephen Warren [mailto:swar...@wwwdotorg.org]
> Sent: Monday, October 05, 2015 4:03 PM
> To: u-boot@lists.denx.de; Simon Glass ; Tom Warren
> ; Stephen Warren
> Cc: Thierry Reding
On 18 October 2015 at 21:18, Bin Meng wrote:
> On Mon, Oct 19, 2015 at 9:51 AM, Simon Glass wrote:
>> Add support for the debug UART on link. This is useful for early debugging.
>>
>> Signed-off-by: Simon Glass
>> ---
>>
>> Changes in
On 18 October 2015 at 21:17, Bin Meng wrote:
> Hi Simon,
>
> On Mon, Oct 19, 2015 at 9:51 AM, Simon Glass wrote:
>> We want to be able to add other common code to this function. So change the
>> driver's version to have an underscore before it, just like
>>
On 18 October 2015 at 21:17, Bin Meng wrote:
> On Mon, Oct 19, 2015 at 9:51 AM, Simon Glass wrote:
>> It is useful to see a message from the debug UART early during boot so that
>> you know things are working. Add an option to enable this. The message will
On 18 October 2015 at 21:17, Bin Meng wrote:
> On Mon, Oct 19, 2015 at 9:51 AM, Simon Glass wrote:
>> Some boards need to set things up before the debug UART can be used. On
>> these boards a call to debug_uart_init() is insufficient. When this option
>> is
On 18 October 2015 at 21:17, Bin Meng wrote:
> On Mon, Oct 19, 2015 at 9:51 AM, Simon Glass wrote:
>> If the debug UART is enabled, get it ready for use at the earliest possible
>> opportunity. This is not actually very early, but until we have a stack it
> -Original Message-
> From: Stephen Warren [mailto:swar...@wwwdotorg.org]
> Sent: Wednesday, October 21, 2015 4:11 PM
> To: Tom Warren
> Cc: u-boot@lists.denx.de; Simon Glass ; Stephen Warren
> ; Thierry Reding
On 10/21/2015 05:03 PM, Tom Warren wrote:
Stephen,
-Original Message-
From: Stephen Warren [mailto:swar...@wwwdotorg.org]
Sent: Monday, October 05, 2015 4:03 PM
To: u-boot@lists.denx.de; Simon Glass ; Tom Warren
; Stephen Warren
Hi Tom,
This includes support for booting VxWorks, the Advantech SOM-6896, MRC
fixes (speeds up boot), expanded video support and some debug UART
improvements.
The following changes since commit 5ec0003b19cbdf06ccd6941237cbc0d1c3468e2d:
Prepare v2015.10 (2015-10-19 19:59:38 -0400)
are
On 18 October 2015 at 20:41, Bin Meng wrote:
> Hi Simon,
>
> On Mon, Oct 19, 2015 at 10:38 AM, Simon Glass wrote:
>> Hi Bin,
>>
>> On 18 October 2015 at 20:32, Bin Meng wrote:
>>> Hi Simon,
>>>
>>> On Mon, Oct 19, 2015 at 10:26 AM,
On 18 October 2015 at 20:23, Bin Meng wrote:
> On Mon, Oct 19, 2015 at 5:55 AM, Simon Glass wrote:
>> The current check is incorrect and will fail when any non-zero byte is read.
>> Fix it.
>>
>> Signed-off-by: Simon Glass
>> ---
>>
>>
On 18 October 2015 at 20:23, Bin Meng wrote:
> On Mon, Oct 19, 2015 at 5:55 AM, Simon Glass wrote:
>> For consistency, use 'ret' to handle a return value.
>>
>> Signed-off-by: Simon Glass
>> ---
>>
>> arch/x86/cpu/ivybridge/sdram.c | 16
On Wednesday, October 21, 2015 at 04:42:03 PM, Thomas Chou wrote:
> Add README.nios2 about how to add nios2 boards to u-boot.
>
> Signed-off-by: Thomas Chou
> Acked-by: Marek Vasut
Nice :-)
Best regards,
Marek Vasut
On Wednesday, October 21, 2015 at 03:10:44 PM, Thomas Chou wrote:
> As the virtual address and physical address mapping of nios2 with
> MMU are different. Add a check of MMU, and fix the mapping.
>
> Signed-off-by: Thomas Chou
> ---
> arch/nios2/include/asm/io.h | 6 +-
On 10/21/2015 05:24 PM, Tom Warren wrote:
>Stephen Warren wrote at Wednesday, October 21, 2015 4:11 PM:
>> On 10/21/2015 05:03 PM, Tom Warren wrote:
>>> Stephen,
>>>
>>>Stephen Warren wrote at Monday, October 05, 2015 4:03 PM:
p2371-2180 has two PCI ports; a regular x4 slot and a x1 M.2 slot.
On Wednesday, October 21, 2015 at 03:09:27 PM, Thomas Chou wrote:
> Hi Marek,
Hi!
> On 10/19/2015 08:31 PM, Marek Vasut wrote:
> >> + /* decode regs, assume address-cells and size-cells are both one */
> >> + list = fdt_getprop(blob, node, "reg-names", );
> >> + if (!list)
> >> +
On Wednesday, October 21, 2015 at 03:05:03 PM, Thomas Chou wrote:
> Convert altera_tse to driver model and phylib.
>
> Signed-off-by: Thomas Chou
> ---
> v2
> remove volatile and use I/O accessors as suggested by Marek.
> use virt_to_phys() to get dma address.
> add
Hi Thomas,
On 21 October 2015 at 07:05, Thomas Chou wrote:
>
> Convert altera_tse to driver model and phylib.
>
> Signed-off-by: Thomas Chou
> ---
> v2
> remove volatile and use I/O accessors as suggested by Marek.
> use virt_to_phys() to get dma
On the BeagleBone these i2c1 pins are routed to the expanasion header, where
they can be defined as either pr1_usart0_Xxd/pwm0/spi0/i2c1, dont assume i2c1
Fixes: https://e2e.ti.com/support/arm/sitara_arm/f/791/p/313894/1387696
Signed-off-by: Robert Nelson
Reported-by:
Hi Tom,
On Tue, Oct 20, 2015 at 03:46:36PM -0400, Tom Rini wrote:
> On Thu, Oct 15, 2015 at 02:34:17PM +0200, Maxime Ripard wrote:
>
> > So far the fastboot code was only supporting MMC-backed devices for its
> > flashing operations (flash and erase).
> >
> > Add a storage backend for
On 18 October 2015 at 20:23, Bin Meng wrote:
> On Mon, Oct 19, 2015 at 5:55 AM, Simon Glass wrote:
>> The RTC can fail, so check the return value for reads.
>>
>> Signed-off-by: Simon Glass
>> ---
>>
>> arch/x86/cpu/ivybridge/sdram.c |
Hi Patrick,
On 21 October 2015 at 06:14, Patrick Delaunay
wrote:
> code under flag CONFIG_PARTITION_TYPE_GUID
> add parameter "type" to select partition type guid
>
> example of use with gpt command :
>
> partitions = uuid_disk=${uuid_gpt_disk}; \
>
+U-Boot
Hi Marco,
On 20 October 2015 at 06:56, Hoefle Marco wrote:
>
> Hello Simon,
> I read your presentation regarding driver model for u-boot. We want to port
> our old u-boot for Microblaze to an up to date one.
> I am struggling with the device tree -> driver
On 21 October 2015 at 08:07, Tom Rini wrote:
> On Wed, Oct 21, 2015 at 08:05:33AM -0500, George McCollister wrote:
>
>> Advantech SOM-6896 is a Broadwell U based COM Express Compact Module
>> Type 6. This patch adds support for it as a coreboot payload.
>>
>> On board SATA and
On 18 October 2015 at 20:27, Simon Glass wrote:
> Hi Bin,
>
> On 18 October 2015 at 20:23, Bin Meng wrote:
>> Hi Simon,
>>
>> On Mon, Oct 19, 2015 at 5:55 AM, Simon Glass wrote:
>>> At present a missing $ causes this code to hang when
On 18 October 2015 at 20:23, Bin Meng wrote:
> Hi Simon,
>
> On Mon, Oct 19, 2015 at 5:55 AM, Simon Glass wrote:
>> Use this option instead of a private CONFIG_CACHE_MRC_BIN option.
>>
>
> The CONFIG_CACHE_MRC_BIN option seems to be used to program the MTRR
On 18 October 2015 at 20:23, Bin Meng wrote:
> On Mon, Oct 19, 2015 at 5:55 AM, Simon Glass wrote:
>> This code takes about 450ms without the MRC cache and about 27ms with the
>> cache. Add a debug timer so that this time can be displayed.
>>
>>
On 18 October 2015 at 20:23, Bin Meng wrote:
> On Mon, Oct 19, 2015 at 5:55 AM, Simon Glass wrote:
>> From: Bin Meng
>>
>> This works correctly now, so enable it.
>>
>> Signed-off-by: Bin Meng
>> Dropped malloc()
On 18 October 2015 at 20:22, Bin Meng wrote:
> On Mon, Oct 19, 2015 at 5:55 AM, Simon Glass wrote:
>> Add a comment to make it clear to which block the #endif relates.
>>
>> Signed-off-by: Simon Glass
>> ---
>>
>> drivers/rtc/mc146818.c
This board runs a P5020 or P5040 chip, and utilizes
an EEPROM with similar formatting to the Freescale P5020DS.
Large amounts of this code were developed by
Adrian Cox
Signed-off-by: Andy Fleming
---
arch/powerpc/cpu/mpc85xx/Kconfig | 4 +
The code is from Adrian Cox, and is patterned after similar
support in Linux (drivers/rtc/rtc-ds1307.c:1121-1135). This
chip is used on the Cyrus board from Varisys.
Signed-off-by: Andy Fleming
---
drivers/rtc/Makefile | 2 +-
drivers/rtc/ds1307.c | 34
Much of this code is patterned off the P5020DS support.
The Cyrus board uses an MCP79411 rtc chip, so we add
support for that before adding the board.
Andy Fleming (2):
rtc: Add MCP79411 support to DS1307 rtc driver
mpc85xx: Add support for the Varisys Cyrus board
On 08/30/15 11:42, Nikita Kiryanov wrote:
> Add support for loading splash image from USB drive formatted with a
> filesystem.
>
> Cc: Igor Grinberg
> Cc: Tom Rini
> Signed-off-by: Nikita Kiryanov
[...]
> +#ifdef
Convert altera_tse to driver model and phylib.
Signed-off-by: Thomas Chou
---
v2
remove volatile and use I/O accessors as suggested by Marek.
use virt_to_phys() to get dma address.
add free_pkt() ops.
add timeout to loop.
allocate cache aligned rx buffer.
Advantech SOM-6896 is a Broadwell U based COM Express Compact Module
Type 6. This patch adds support for it as a coreboot payload.
On board SATA and SPI are functional. On board Ethernet isn't functional
but since it's optional and ties up a PCIe x4 that is otherwise brought
out, this isn't a
Hi Lokesh,
On 10/21/2015 06:10 PM, Lokesh Vutla wrote:
> Hi Vignesh,
>
> On Wednesday 21 October 2015 10:10 AM, Vignesh R wrote:
>> This adds support to update firmware on qspi flash present on
>> am437x-sk-evm and am43xx-epos-evm via DFU.
>>
>> On device:
>> => setenv dfu_alt_info
On Wed, Oct 21, 2015 at 01:24:42PM +0100, Peter Robinson wrote:
> On Wed, Oct 21, 2015 at 12:55 PM, Tom Rini wrote:
> > On Wed, Oct 21, 2015 at 09:37:13AM +0100, Peter Robinson wrote:
> >> >>> Felipe Balbi writes:
> >> >>> > Fix the following build break:
> >>
On Wed, Oct 21, 2015 at 12:29:46AM +, Luka Perkov wrote:
> Hi Tom,
>
> can you please pull various mvebu enhancements from Stefan?
>
> The following changes since commit 5ec0003b19cbdf06ccd6941237cbc0d1c3468e2d:
>
> Prepare v2015.10 (2015-10-19 19:59:38 -0400)
>
> are available in the
Hi Marek,
On 10/19/2015 08:31 PM, Marek Vasut wrote:
+ /* decode regs, assume address-cells and size-cells are both one */
+ list = fdt_getprop(blob, node, "reg-names", );
+ if (!list)
+ return -ENOENT;
+ end = list + len;
+ cell = fdt_getprop(blob,
On Tue, Oct 20, 2015 at 11:02:54PM +0200, Hans de Goede wrote:
> Hi Tom,
>
> Here is the first pull-req for sunxi, it contains some none
> sunxi specific patches which I've picked up as sunxi is the first
> user of them, these patches have been reviewed by you and/or
> Simon Glass.
>
>
On Wed, Oct 21, 2015 at 08:44:15AM +, Joakim Tjernlund wrote:
> On Tue, 2015-10-20 at 17:21 -0400, Tom Rini wrote:
> > On Tue, Oct 20, 2015 at 04:06:51PM -0500, Andy Fleming wrote:
> > > On Fri, Oct 16, 2015 at 8:14 AM, Joakim Tjernlund
> > > wrote:
> > > > On
As the virtual address and physical address mapping of nios2 with
MMU are different. Add a check of MMU, and fix the mapping.
Signed-off-by: Thomas Chou
---
arch/nios2/include/asm/io.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git
On 21 October 2015 at 13:50, Tom Rini wrote:
> On Wed, Oct 21, 2015 at 12:00:03PM +0100, Ryan Harkin wrote:
>> On 20 October 2015 at 16:38, Tom Rini wrote:
>>
>> > On Tue, Oct 20, 2015 at 08:05:40AM +0200, Linus Walleij wrote:
>> >
>> > > Only compile in
On Wed, 2015-10-21 at 09:12 -0400, Tom Rini wrote:
> On Wed, Oct 21, 2015 at 08:44:15AM +, Joakim Tjernlund wrote:
> > On Tue, 2015-10-20 at 17:21 -0400, Tom Rini wrote:
> > > On Tue, Oct 20, 2015 at 04:06:51PM -0500, Andy Fleming wrote:
> > > > On Fri, Oct 16, 2015 at 8:14 AM, Joakim
Hi,
On 10/20/2015 10:57 AM, Siarhei Siamashka wrote:
> Hello,
>
> Currently SD card support seems to be broken at least on the ODROID-X
> board in U-Boot v2015.10. Checking older U-Boot releases shows that
> it used to work in v2014.10, and bisecting points to the commit
>
Hi Simon,
On 10/22/2015 10:15 AM, Simon Glass wrote:
+ writel(0, _sgdma->control);
+ ret = alt_sgdma_wait_transfer(rx_sgdma);
+ if (ret == -ETIMEDOUT)
+ writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK,
+ _sgdma->control);
+
+ writel(0,
Enable the IP feature's snoop signal to support
hardware snoop for cache coherence.
SNPCNFGCR contains the bits to drive snoop signal
for various masters.
Signed-off-by: Yuan Yao
---
arch/arm/cpu/armv7/ls102xa/soc.c | 8
Hi Ryan,
On 21.10.2015 11:54, Ryan Harkin wrote:
cword.l is an unsigned long int, but it is intended to be 32 bits long.
Unfortunately, it's 64-bits long on a 64-bit system, meaning that a
64-bit system cannot use 32-bit wide CFI flash parts.
Similar problems also exist with the other cword
Signed-off-by: Yuan Yao
---
arch/arm/cpu/armv7/ls102xa/soc.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 6036473..97ba6d5 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
cword.l is an unsigned long int, but it is intended to be 32 bits long.
Unfortunately, it's 64-bits long on a 64-bit system, meaning that a
64-bit system cannot use 32-bit wide CFI flash parts.
Similar problems also exist with the other cword sizes.
Also, this patch introduced compiler
Add support for storing the environment in CFI NOR flash on Juno and FVP
models.
I also removed some config values that are not used by CFI flash parts.
Juno has 1 flash part with 259 sectors. The first 255 sectors are
0x4 (256kb) and are followed by 4 sectors of 0x1 (64KB).
FVP models
This patch allows vexpress64 targets to be compiled when
CONFIG_SYS_FLASH_CFI is enabled.
I considered using #warning instead of #error, but this just clutters up
the build output and hides real warnings.
Without this patch, you see errors during compilation like this:
Whilst adding NOR support for Juno and FVP models, I encountered a
problem in cfi_flash.c. It is using "unsigned long" to represent a
32-bit value. This does not work on 64-bit systems such as vexpress64.
I fixed it up in patch 1/3, however, I'm not convinced that my mod is
the correct one.
EDDRTQCFG Registers are Integration Strap values which controls
performance parameters for DDR Controller.
The bit 25 is used to disable priorities within DDR since DDR
are connected backwards on Rev2.0.
Signed-off-by: Yuan Yao
---
arch/arm/cpu/armv7/ls102xa/soc.c | 13
Hello Albert,
On Tue, Oct 20, 2015 at 02:59:10PM +0200, Albert ARIBAUD wrote:
>Hello Peng,
>
>On Tue, 20 Oct 2015 15:41:30 +0800, Peng Fan
>wrote:
>> Hi Albert,
>>
>> On Tue, Oct 20, 2015 at 09:32:51AM +0200, Albert ARIBAUD wrote:
>> >Hello Peng,
>> >
>> >On Tue, 20 Oct
Hello Siarhei, Anand,
On 10/21/2015 11:57 AM, Anand Moon wrote:
Hi Siarhei ,
On 21 October 2015 at 07:28, Siarhei Siamashka
wrote:
On Mon, 31 Aug 2015 00:33:16 +0530
Anand Moon wrote:
At the last moment I got this to work on my odroidxu3
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