On Tue, Oct 25, 2016 at 4:16 AM, André Przywara wrote:
> On 24/10/16 09:20, Jagan Teki wrote:
>> On Sun, Oct 23, 2016 at 3:22 AM, André Przywara
>> wrote:
>>> On 22/10/16 18:10, Jagan Teki wrote:
>>>
>>> Hi,
>>>
On Fri, Oct 21, 2016 at 6:54 AM, Andre Przywara
wrote:
> OHCI has a
On Tue, Oct 25, 2016 at 10:05 AM, Amit Tomer wrote:
> Hello!
>
>>
>> Since the driver is dm-driven this config not need.
>
> I tried not to use this config but then driver don't get compiled.
>
> You're talking about CONFIG_USB_EHCI and CONFIG_USB_EHCI_SUNXI, right ?
CONFIG_USB_MAX_CONTROLLER_C
On 10/26/2016 04:03 AM, Jaehoon Chung wrote:
> Hi,
>
> On 10/25/2016 06:13 AM, Simon Glass wrote:
>> On 24 October 2016 at 10:24, Sylvain Lesne wrote:
>>>
>>> Now that CONFIG_BLK and CONFIG_MMC_OPS are enabled by default with
>>> CONFIG_DM_MMC, the DWMMC driver on the socfpga platform fails at
>>
From: Yuan Yao
The default configuration for QSPI AHB bus can't support 16MB+.
But some flash on NXP layerscape board are more than 16MB.
Signed-off-by: Yuan Yao
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c| 37 ++
.../include/asm/arch-fsl-layerscape/immap_lsch2.
Hi,
On 10/25/2016 06:13 AM, Simon Glass wrote:
> On 24 October 2016 at 10:24, Sylvain Lesne wrote:
>>
>> Now that CONFIG_BLK and CONFIG_MMC_OPS are enabled by default with
>> CONFIG_DM_MMC, the DWMMC driver on the socfpga platform fails at
>> runtime.
>>
>> This adds the missing fields in the dri
On 10/21/2016 08:52 PM, Jaehoon Chung wrote:
> To prevent the wrong value check the SD version.
>
> Signed-off-by: Jaehoon Chung
Applied on u-boot-mmc. Thanks!
Best Regards,
Jaehoon Chung
> ---
> drivers/mmc/sdhci.c | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --g
On 10/24/2016 05:51 PM, Peng Fan wrote:
> Hi Chung,
> On Mon, Oct 24, 2016 at 03:22:22PM +0900, Jaehoon Chung wrote:
>> If vmmc didn't supply, we didn't know which card didn't supply vmmc.
>> And changed from "put" to "debug".
>>
>> Signed-off-by: Jaehoon Chung
>
> Reviewed-by: Peng Fan
Applied
This commit simplifies the initial configuration performed
by pxa3xx_nand_scan. No functionality change is intended.
[ Linux commit 154f50fbde539c20bbf74854461d932ebdace4d5 ]
Cc: Ezequiel García
Signed-off-by: Chris Packham
---
Changes in v2:
- New
drivers/mtd/nand/pxa3xx_nand.c | 30 +++
This commit is needed to properly support the 8-bits ECC configuration
with 4KB pages.
When pages larger than 2 KB are used on platforms using the PXA3xx
NAND controller, the reading/programming operations need to be split
in chunks of 2 KBs or less because the controller FIFO is limited to
about
The Data Flash Control Register (NDCR) contains two types
of parameters: those that are needed for device identification,
and those that can only be set after device identification.
Therefore, the driver can't set them all at once and instead
needs to configure the first group before nand_scan_ide
The read ID count should be made as large as the maximum READ_ID size,
so there's no need to have dynamic size. This commit sets the hardware
maximum read ID count, which should be more than enough on all cases.
Also, we get rid of the read_id_bytes, and use a macro instead.
[ Linux commit b226eca
The chunk size represents the size of the data chunks, which
is used by the controllers that allow to split transfered data.
However, the initial chunk size is used in a non-splitted way,
during device identification. Therefore, it must be large enough
for all the NAND commands issued during devic
When 2 commands are submitted in a row, and the second is very quick,
the completion of the second command might never come. This happens
especially if the second command is quick, such as a status read
after an erase
[ Linux commit 21fc0ef9652f0c809dc0d3e0a67f1e1bf6ff8255 ]
Cc: Robert Jarzmik
S
When the nand is first probe, and upon the first command start, the
status bits should be cleared before the interrupts are unmasked.
[ Linux commit 0b14392db2e998157d924085d7913e537ec26121 ]
Cc: Robert Jarzmik
Signed-off-by: Chris Packham
---
Changes in v2:
- Add reference to Linux commit sha
Don't store struct mtd_info in struct pxa3xx_nand_host. Instead use the
one that is already part of struct nand_chip. This brings us in line
with current U-boot and Linux conventions.
Signed-off-by: Chris Packham
---
Changes in v2:
- Drop irrelevant Cc from commit message
drivers/mtd/nand/pxa3
Since the pxa3xx_nand driver was added there has been a discrepancy in
pxa3xx_nand_set_sdr_timing() around the setting of tWP_min and tRP_min.
This brings us into line with the current Linux code.
Signed-off-by: Chris Packham
---
Changes in v2:
- None
drivers/mtd/nand/pxa3xx_nand.c | 4 ++--
1
The initial buffer is used for the initial commands used to detect
a flash device (STATUS, READID and PARAM).
ONFI param page is 256 bytes, and there are three redundant copies
to be read. JEDEC param page is 512 bytes, and there are also three
redundant copies to be read. Hence this buffer should
I'm looking into the NAND support for the db-88f6820-amc board.
There are a number of changes in the pxa3xx_nand driver in Linux that
are relevant (not specifically to this boards but to Armada boards in
general). Some of these changes are cleanups and some are actual bug
fixes.
I'd really appreci
The main PLL frequency is 2GHz for Armada-XP and 1GHZ for Armada 375,
38x and 39x.
[ Linux commit ae142bd9976532aa5232ab0b00e621690d8bfe6a ]
Signed-off-by: Chris Packham
---
See
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=ae142bd99765
I've set the value for ARMAD
On 25/10/16 08:52, Alexander Graf wrote:
Hi Alex,
thanks for looking at this!
>
> On 25/10/2016 02:51, Andre Przywara wrote:
>> On systems using the generic timer routines defined in lib/time.c we
>> use timebase_l and timebase_h fields from the gd to detect wraparounds
>> in our tick counter.
On 10/08/2016 14:56, Simon Glass wrote:
> Hi Alex,
>
> On 10 August 2016 at 05:49, Alexander Graf wrote:
>> On 08/07/2016 01:23 AM, Simon Glass wrote:
>>>
>>> Add the required pieces to support the EFI loader on x86.
>>>
>>> Since U-Boot only builds for 32-bit on x86, only a 32-bit EFI applicat
On 10/24/2016 12:51 AM, Wenbin song wrote:
> The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment
> and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] is used to choose
> which offset will be used.
>
> The LS1043A rev1.0 silicon only supports the CIG offset with 4K alig
Von: Jaehoon Chung [jh80.ch...@samsung.com]
Gesendet: Freitag, 21. Oktober 2016 14:11
>>>From my tests it should be somewhere between these two commits:
>> 1c62d999528da1f052cb4b07cbb540b148c52537OK
>> ceec08f50b66df0c988033842ec057a32658cfe0NOK
> Thanks for checking..Could you share whi
On 10/13/2016 11:36 PM, Sriram Dash wrote:
> Defines get_svr() for mpc512x devices
>
> Signed-off-by: Sriram Dash
> Reviewed-by: Bin Meng
> ---
> Changes in v2:
> - cosmetic changes
>
> arch/powerpc/cpu/mpc512x/start.S | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/powerpc/
On 17 October 2016 at 16:17, Simon Glass wrote:
> On 17 October 2016 at 08:24, George McCollister
> wrote:
>> The Atmel AT97SC3204 is also TIS compliant.
>> Modify the tpm_tis_lpc driver to check for the vid/did used by the
>> Atmel AT97SC3204 and report an appropriate description.
>>
>> Signed-o
On 17 October 2016 at 19:54, Simon Glass wrote:
> On 17 October 2016 at 19:09, Tom Rini wrote:
>> Now that we free resources in sandbox_fs_ls Coverity is letting us know
>> that in some cases we might leak. So in case of error we should still
>> let os_dirent_free free anything that was allocate
On 17 October 2016 at 16:17, Simon Glass wrote:
> On 16 October 2016 at 09:13, Stefan Brüns
> wrote:
>> GCC 6.2 reasonably complains about the current code:
>>
>> ../cmd/tpm_test.c: In function ‘do_tpmtest’:
>> ../cmd/tpm_test.c:540:3: warning: this ‘for’ clause does not guard...
>> [-Wmisleadi
On 10/24/2016 11:55 PM, Prabhakar Kushwaha wrote:
>
>> -Original Message-
>> From: york sun
>> Sent: Monday, October 24, 2016 9:41 PM
>> To: Prabhakar Kushwaha ; u-
>> b...@lists.denx.de
>> Cc: o...@buserror.net
>> Subject: Re: [PATCH] Kconfig: ifc: Moving IFC_BANK_COUNT from Kconfig to
>>
Add support for distro_bootcmd on MMC and fall back to prior
behavior if distro_bootcmd fails.
Tested on Beagleboad xM to boot GRUB2 (and then Linux kernel) in EFI mode
from MMC.
Signed-off-by: Guillaume GARDET
Cc: Tom Rini
---
include/configs/omap3_beagle.h | 76 ---
> -Original Message-
> From: york sun
> Sent: Tuesday, October 25, 2016 12:37 AM
> To: Priyanka Jain ; u-boot@lists.denx.de;
> Prabhakar Kushwaha
> Cc: Raghav Dogra
> Subject: Re: [PATCH 5/5][v2] armv8/fsl-lsch3: Update code to release
> secondary cores
>
> On 10/24/2016 08:49 AM, york
> -Original Message-
> From: york sun
> Sent: Tuesday, October 25, 2016 12:15 AM
> To: Prabhakar Kushwaha ; Pratiyush
> Srivastava ; u-boot@lists.denx.de; Mingkai
> Hu
> Cc: Hou Zhiqiang
> Subject: Re: [PATCH] armv8/ls1043a: Add the OCRAM initialization
>
> On 10/23/2016 06:59 AM, Prab
> -Original Message-
> From: york sun
> Sent: Tuesday, October 25, 2016 12:33 AM
> To: Priyanka Jain ; u-boot@lists.denx.de;
> Prabhakar Kushwaha
> Cc: Priyanka Jain
> Subject: Re: [PATCH 0/5][v2] Update LS2080A SoC code to support LS2088A
> SoC
>
> On 10/24/2016 01:32 AM, Priyanka Jai
Hi Stefano,
On Mon, Oct 24, 2016 at 7:51 PM, Jagan Teki wrote:
> On Mon, Oct 24, 2016 at 7:31 PM, Stefano Babic wrote:
>> On 24/10/2016 15:15, Jagan Teki wrote:
>>> On Mon, Oct 24, 2016 at 6:04 PM, Stefano Babic wrote:
Hi Jagan,
>>
Please wait, I am confused. You have sent a comp
Hi York,
>-Original Message-
>From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of york sun
>Sent: Monday, October 24, 2016 9:45 PM
>To: Prabhakar Kushwaha ; Pratiyush Srivastava
>; u-
>b...@lists.denx.de; Mingkai Hu
>Cc: Hou Zhiqiang
>Subject: Re: [U-Boot] [PATCH] armv8/ls10
On 10/24/2016 10:27 AM, york@nxp.com wrote:
>
> Please clarify, before this patch the code runs through this section for
> LS2080A but actually it has no effect, correct?
>
Never mind. I just realized CONFIG_FSL_TZASC_400 wasn't defined before.
York
___
The patch set implement USB PHY errata workaround which are
required for LS series of freescale platforms which have
Synopsis UTMI PHY
Suresh Gupta (8):
armv8: Add workaround for USB erratum A-009008
armv8: Add workaround for USB erratum A-009798
armv8: Add workaround for USB erratum A-00899
Low Frequency Periodic Signaling (LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter settings
Change settings required for transmitter signal swings to pass
compliance tests.
Signed-off-by: Sriram Dash
Signed-off-by: Rajesh Bhagat
---
arch/arm/cpu/ar
On 25/10/2016 02:51, Andre Przywara wrote:
> On systems using the generic timer routines defined in lib/time.c we
> use timebase_l and timebase_h fields from the gd to detect wraparounds
> in our tick counter. The tick calculcation algorithm silently assumes
> that a long is only 32 bits, which l
Add serdes protocol support for
Serdes1 protocol: 0x39, 0x4B, 0x4C, 0x4D
Serdes2 protocol: 0x47, 0x57
Signed-off-by: Priyanka Jain
---
arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c |6 +
board/freescale/ls2080aqds/eth.c | 122 +++-
2 files changed, 125
The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receiver
Compliance test failure for a 100mV threshold.
The changes shift the threshold from ~100mV towards ~130mV resulting
in passing of USB High Speed Receiver Sensitivity
On 25.10.2016 09:22, Chris Packham wrote:
Prevent cache misalignment message by ensuring that a whole cache line
is flushed.
Signed-off-by: Chris Packham
---
cmd/load.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/cmd/load.c b/cmd/load.c
index 65557e4f9ec3..77c3359b29b7
Signed-off-by: Priyanka Jain
---
drivers/net/ldpaa_eth/ldpaa_eth.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c
b/drivers/net/ldpaa_eth/ldpaa_eth.c
index 75b2b6b..4e61700 100644
--- a/drivers/net/ldpaa_eth/ldpaa_eth.c
+++ b/drivers/
> -Original Message-
> From: york sun
> Sent: Monday, October 24, 2016 9:41 PM
> To: Prabhakar Kushwaha ; u-
> b...@lists.denx.de
> Cc: o...@buserror.net
> Subject: Re: [PATCH] Kconfig: ifc: Moving IFC_BANK_COUNT from Kconfig to
> config.h
>
> On 10/23/2016 07:04 AM, Prabhakar Kushwaha wr
Prevent cache misalignment message by ensuring that a whole cache line
is flushed.
Signed-off-by: Chris Packham
---
cmd/load.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/cmd/load.c b/cmd/load.c
index 65557e4f9ec3..77c3359b29b7 100644
--- a/cmd/load.c
+++ b/cmd/load.c
@@
Low Frequency Periodic Signaling (LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter settings
Change settings required for transmitter signal swings to pass
compliance tests.
Signed-off-by: Sriram Dash
Signed-off-by: Rajesh Bhagat
---
arch/arm/cpu/ar
USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature
Optimal eye at TXVREFTUNE value to 1001 is observed, change
set the same value.
Signed-off-by: Sriram Dash
---
arch/arm/cpu/armv7/ls102xa/Kconfig
USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature
Optimal eye at TXVREFTUNE value to 1001 is observed, change
set the same vale.
Signed-off-by: Sriram Dash
Signed-off-by: Rajesh Bhagat
---
arch/ar
Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values
Changes identified in test setup makes the Rx compliance test pass
Signed-off-by: Sriram Dash
Signed-off-by: Rajesh Bhagat
---
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 +++
arch
The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receive
Compliance test failure for a 100mV threshold.
The changes shift the threshold from ~100mV towards ~130mV resulting
in passing of USB High Speed Receiver Sensitivity
Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values
Changes identified in test setup makes the Rx compliance test pass
Signed-off-by: Sriram Dash
Signed-off-by: Rajesh Bhagat
---
arch/arm/cpu/armv7/ls102xa/Kconfig| 4
arch
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