On Fri, Oct 28, 2016 at 07:05:42PM +0200, Andreas Bießmann wrote:
> Hi Tom,
>
> please pull the following changes into u-boot/master for 2016.11.
>
> One of the patches introduce a build warning (-Wunused-function) which is
> removed with the following patch. This is due to introducing the new
On Fri, Oct 28, 2016 at 04:44:35PM +0200, Stefano Babic wrote:
> Hi Tom,
>
> please pull from u-boot-imx, thanks !
>
> There are two major patchsets in this PR:
>
> - plugin support from Peng
> - Jagan's support for Engicam i.CoreM6 , with several
> move to Kconfig.
>
>
> The following
On Fri, Oct 28, 2016 at 11:47:18AM +0900, Jaehoon Chung wrote:
> Dear Tom,
>
> Could you these patches on u-boot/master?
>
> The following changes since commit b03380805b5a184b7017dc428a53c8e1e9c9f99c:
>
> i2c: designware: Avoid overwriting the cmd_data register (2016-10-24
> 18:15:47
The cros_ec_decode_region() function is only used in combination
with the crosec cmds. Move the function to the correct place.
Signed-off-by: Moritz Fischer
Cc: Simon Glass
Cc: Masahiro Yamada
Cc: u-boot@lists.denx.de
On Sat, Oct 29, 2016 at 1:30 AM, Hans de Goede wrote:
> Hi Chen-Yu,
>
> On 28-10-16 12:21, Chen-Yu Tsai wrote:
>>
>> Hi everyone,
>>
>> This series adds full SPL with DRAM initialization for sun9i (A80).
>> The bulk of the work was done by the people at Theobroma Systems.
>>
On 10/28/2016 11:32 AM, Stephen Warren wrote:
> On 10/28/2016 12:17 PM, york sun wrote:
>> On 10/28/2016 10:57 AM, Stephen Warren wrote:
>>> On 10/28/2016 11:38 AM, york sun wrote:
On 10/26/2016 02:02 PM, york@nxp.com wrote:
>
> I came back from my testing and I have more
Hi Jagan,
On 28.10.16 20:07, Jagan Teki wrote:
> On Fri, Oct 28, 2016 at 10:19 PM, Andreas Bießmann
> wrote:
>> Dear Wenyou Yang,
>>
>> Wenyou Yang writes:
>>> Add driver model support while retaining the existing legacy code.
>>> This allows the
On 10/28/2016 10:50 PM, Marcel Ziswiler wrote:
> Optional driver model handling integration.
>
> Signed-off-by: Marcel Ziswiler
> ---
>
> drivers/serial/serial_pxa.c | 181
> ++
> include/dm/platform_data/serial_pxa.h |
Migrate the PXA serial driver to be configured via Kconfig.
Signed-off-by: Marcel Ziswiler
---
configs/colibri_pxa270_defconfig | 1 +
configs/h2200_defconfig | 1 +
configs/zipitz2_defconfig| 1 +
drivers/serial/Kconfig | 6 ++
This series integrates both Kconfig as well as optional driver model
support for the PXA serial driver. As I do not have any of the other
hardware available for testing for now I only transitioned the
Colibri PXA270 to actually make use of DM_SERIAL. As space on this
mostly NOR based hardware is
As the upcoming driver model integration takes up some more precious flash
space first make sure to drop expensive LZMA support.
Signed-off-by: Marcel Ziswiler
---
include/configs/colibri_pxa270.h | 1 -
1 file changed, 1 deletion(-)
diff --git
Add serial platform data to board file.
Enable driver model for PXA serial driver.
Signed-off-by: Marcel Ziswiler
---
board/toradex/colibri_pxa270/colibri_pxa270.c | 18 --
configs/colibri_pxa270_defconfig | 2 ++
Optional driver model handling integration.
Signed-off-by: Marcel Ziswiler
---
drivers/serial/serial_pxa.c | 181 ++
include/dm/platform_data/serial_pxa.h | 56 +++
2 files changed, 174 insertions(+), 63
On Fri, Oct 28, 2016 at 12:41:05PM -0700, Simon Glass wrote:
> Hi Tom,
>
> On 28 October 2016 at 11:59, Tom Rini wrote:
> > On Thu, Oct 27, 2016 at 08:18:39PM -0600, Simon Glass wrote:
> >> Coverity complains that this can overflow. If we later increase the size
> >> of one
Hi Tom,
On 28 October 2016 at 11:59, Tom Rini wrote:
> On Thu, Oct 27, 2016 at 08:18:39PM -0600, Simon Glass wrote:
>> Coverity complains that this can overflow. If we later increase the size
>> of one of the strings in the table, it could happen.
>>
>> Adjust the code to
On 10/26/2016 02:02 PM, york@nxp.com wrote:
>
> I came back from my testing and I have more questions than answers.
>
> For _this_ patch, I proposed to flush cache before disabling them,
> noting once the dcache is disabled, the staled data in dirty cache is
> not visible to the core. My
On Thu, Oct 27, 2016 at 08:18:39PM -0600, Simon Glass wrote:
> Coverity complains that this can overflow. If we later increase the size
> of one of the strings in the table, it could happen.
>
> Adjust the code to protect against this.
>
> Signed-off-by: Simon Glass
>
On Fri, Oct 28, 2016 at 3:51 PM, Chen-Yu Tsai wrote:
> From: Philipp Tomsich
>
> This adds DRAM initialisation code for sun9i, which calculates the
> appropriate timings based on timing information for the supplied
> DDR3 bin and the clock
From: Shaohui Xie
LPUART0 is used by default, and it's using platform clock.
Signed-off-by: Shaohui Xie
---
changes in v2:
1. dropped CONFIG_LPUART_CLK.
2. uses CONFIG_SYS_FSL_DDR4 in defconfig.
arch/arm/dts/Makefile | 1 +
From: Shaohui Xie
It's not always true that LPUART clock is CONFIG_SYS_CLK_FREQ, this
patch provides a weak function get_lpuart_clk, so that the clock can be
ovreride on a specific board which uses different clock for LPUART.
Signed-off-by: Shaohui Xie
Hi York/Alison,
I have already sent patch to upstream at 10/13/2016.
And the u-boot have too many changes now.
Do you means that I will git the latest u-boot and repatch/ review/upstream it
again ?
> -Original Message-
> From: Alison Wang
> Sent: Thursday, October 27, 2016 3:43 PM
>
On Fri, Oct 28, 2016 at 3:51 PM, Chen-Yu Tsai wrote:
> From: Philipp Tomsich
>
> On sun9i, the GTBUS manages transaction priority and bandwidth
> for multiple read ports when accessing DRAM. The initialisation
> mirrors the settings from
On 10/28/2016 10:57 AM, Stephen Warren wrote:
> On 10/28/2016 11:38 AM, york sun wrote:
>> On 10/26/2016 02:02 PM, york@nxp.com wrote:
>>>
>>> I came back from my testing and I have more questions than answers.
>>>
>>> For _this_ patch, I proposed to flush cache before disabling them,
>>>
On 10/28/2016 12:17 PM, york sun wrote:
On 10/28/2016 10:57 AM, Stephen Warren wrote:
On 10/28/2016 11:38 AM, york sun wrote:
On 10/26/2016 02:02 PM, york@nxp.com wrote:
I came back from my testing and I have more questions than answers.
For _this_ patch, I proposed to flush cache
On Fri, Oct 28, 2016 at 10:19 PM, Andreas Bießmann
wrote:
> Dear Wenyou Yang,
>
> Wenyou Yang writes:
>>Add driver model support while retaining the existing legacy code.
>>This allows the driver to support boards that have converted to
>>driver
Signed-off-by: Jagan Teki
---
MAINTAINERS| 2 +-
doc/git-mailrc | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 8e67202..0bd8995 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -417,7 +417,7 @@ T: git
On 10/28/2016 11:38 AM, york sun wrote:
On 10/26/2016 02:02 PM, york@nxp.com wrote:
I came back from my testing and I have more questions than answers.
For _this_ patch, I proposed to flush cache before disabling them,
noting once the dcache is disabled, the staled data in dirty cache is
On Thu, Oct 27, 2016 at 2:20 AM, André Przywara wrote:
> On 26/10/16 19:51, Jagan Teki wrote:
> Hi,
>
>> On Fri, Oct 21, 2016 at 5:41 AM, Andre Przywara
>> wrote:
>>> The sun8i-emac driver works fine with the A64 Ethernet IP, but we are
>>>
Hi Chen-Yu,
On 28-10-16 12:21, Chen-Yu Tsai wrote:
Hi everyone,
This series adds full SPL with DRAM initialization for sun9i (A80).
The bulk of the work was done by the people at Theobroma Systems.
Their work can be found here:
https://git.theobroma-systems.com/armadillo-u-boot.git/
I
On Fri, Oct 28, 2016 at 10:36 PM, George McCollister
wrote:
> On Mon, Oct 10, 2016 at 1:57 PM, George McCollister
> wrote:
>> Many SPI NOR flash devices support status register protection through
>> one or two status register protection
Add constants for the MPZQLP2CTL DDR register for both
banks to allow setting the LPDDR2 timing values in
.cfg files using a named constant instead of hex addresses
as is currently done in mx6slevk and other board files.
Signed-off-by: Eric Nelson
---
On Mon, Oct 10, 2016 at 1:57 PM, George McCollister
wrote:
> Many SPI NOR flash devices support status register protection through
> one or two status register protection bits. Protection of the status
> register is essential in defending the device from rogue
Hi Tom,
please pull the following changes into u-boot/master for 2016.11.
One of the patches introduce a build warning (-Wunused-function) which is
removed with the following patch. This is due to introducing the new feature,
then switch to the feature and remove the old code in a two step
Dear Wenyou Yang,
Wenyou Yang writes:
>If 'ethaddr' is not set, we will get the ethernet address from AT24MAC,
>and set it to 'ethaddr' variable.
>
>Signed-off-by: Wenyou Yang
>Signed-off-by: Songjun Wu
>Reviewed-by:
Dear Wenyou Yang,
Wenyou Yang writes:
>Enable an early debug UART to debug problems when an ICE or other
>debug mechanism is not available.
>
>Signed-off-by: Wenyou Yang
>Reviewed-by: Simon Glass
>Reviewed-by: Andreas Bießmann
Dear Wenyou Yang,
Wenyou Yang writes:
>Since the introduction of pinctrl and clk driver, and the dts file,
>remove unneeded the pin configurations and the clock enabling code.
>
>Signed-off-by: Wenyou Yang
>Reviewed-by: Simon Glass
Dear Wenyou Yang,
Wenyou Yang writes:
>Move the config options from the include/configs/sama5d2_xplained.h
>to configs/sama5d2_xplained_*_defconfig.
>
>Signed-off-by: Wenyou Yang
>Reviewed-by: Andreas Bießmann
>---
>
Dear Wenyou Yang,
Wenyou Yang writes:
>Due to the peripheral and generated clock driver improvement,
>remove the unnecessary clock calling.
>
>Signed-off-by: Wenyou Yang
>Reviewed-by: Jaehoon Chung
>---
>
>Changes in v3:
> -
Dear Wenyou Yang,
Wenyou Yang writes:
>Add support to enable an early debug UART for debugging.
>
>Signed-off-by: Wenyou Yang
>Reviewed-by: Simon Glass
>Reviewed-by: Andreas Bießmann
>---
>
>Changes in v3:
Dear Wenyou Yang,
Wenyou Yang writes:
>Add ATMEL_USART option to support to enable the Atmel usart driver
>from Kconfig.
>
>Signed-off-by: Wenyou Yang
>Reviewed-by: Andreas Bießmann
>---
>
>Changes in v3:
> - Collect
Dear Wenyou Yang,
Wenyou Yang writes:
>Add driver model support while retaining the existing legacy code.
>This allows the driver to support boards that have converted to
>driver model as well as those that have not.
>
>Signed-off-by: Wenyou Yang
Dear Wenyou Yang,
Wenyou Yang writes:
>Due to the peripheral clock driver improvement, remove the
>unnecessary clock calling.
>
>Signed-off-by: Wenyou Yang
>Acked-by: Stephen Warren
>---
>
>Changes in v3: None
>Changes in v2:
>
Dear Wenyou Yang,
Wenyou Yang writes:
>Due to the peripheral clock driver improvement, remove the
>unnecessary clock calling.
>
>Signed-off-by: Wenyou Yang
>Reviewed-by: Andreas Bießmann
>---
>
>Changes in v3: None
>Changes
Dear Wenyou Yang,
Wenyou Yang writes:
>In order to make clk->dev available in ops->of_xlate() to get the
>clock ID from the 'reg' property of the clock node, assign the
>clk->dev before calling ops->of_xlate().
>
>Signed-off-by: Wenyou Yang
Dear Wenyou Yang,
Wenyou Yang writes:
>Fix the warning from dtc like,
>---8<
>Warning (unit_address_vs_reg): Node
>/ahb/apb/pmc@f0014000/periph64ck/sdmmc0_hclk has a reg or ranges property, but
>no unit name
>--->8
>
>Signed-off-by: Wenyou Yang
Dear Wenyou Yang,
Wenyou Yang writes:
>Due to the peripheral clock driver improvement, remove the
>unnecessary clock calling.
>
>Signed-off-by: Wenyou Yang
>Reviewed-by: Heiko Schocher
>---
>
>Changes in v3: None
>Changes in v2: None
Dear Wenyou Yang,
Wenyou Yang writes:
>Change the error return value -ENODEV from to -EINVAL for more
>reasonable.
>
>Signed-off-by: Wenyou Yang
>Reviewed-by: Heiko Schocher
>---
>
>Changes in v3: None
>Changes in v2: None
>
>
Dear Wenyou Yang,
Wenyou Yang writes:
>For the peripheral clock, provide the clock ops for the clock
>provider, such as spi0_clk. The .of_xlate is to get the clk->id,
>the .enable is to enable the spi0 peripheral clock, the .get_rate
>is to get the clock frequency.
>
>The
Dear Heiko Schocher,
Heiko Schocher writes:
>add at least icache support for at91 based boards.
>This speeds up NOR flash access on an at91sam9g15
>based board from 15.2 seconds reading 8 MiB from
>a SPI NOR flash to 5.7 seconds.
>
>Signed-off-by: Heiko Schocher
Dear "Robert P. J. Day",
Robert P. J. Day writes:
>Signed-off-by: Robert P. J. Day
>Reviewed-by: Andreas Bießmann
>---
>
> given that this misspelling is being used for partition names, i
>won't treat it as a normal typo, so
Dear Heiko Schocher,
Heiko Schocher writes:
>on at91sam9x5 PRES offset is 4 in the PMC master
>clock register.
>
>Signed-off-by: Heiko Schocher
>Acked-by: Wenyou Yang
>Acked-by: Andreas Bießmann
>---
>
>
Dear Wenyou Yang,
Wenyou Yang writes:
>The at91-pmc and at91-sckc aren't the clock providers, change their
>class ID from UCLASS_CLK to UCLASS_SIMPLE_BUS, they also don't
>need to bind the child nodes explicitly, the .post_bind callback
>of simple_bus uclass will do it for
Dear Heiko Schocher,
Heiko Schocher writes:
>add missing MPDDRC_MD defines
>
>Signed-off-by: Heiko Schocher
>Acked-by: Wenyou Yang
>Reviewed-by: Andreas Bießmann
>---
>
> arch/arm/mach-at91/include/mach/atmel_mpddrc.h |
Add IOM_GRP register definitions for i.MX6SL to allow them to be
named in DDR configuration (.cfg) files.
Signed-off-by: Eric Nelson
---
arch/arm/include/asm/arch-mx6/mx6sl-ddr.h | 13 +
1 file changed, 13 insertions(+)
diff --git
2016-10-29 0:32 GMT+09:00 york sun :
> On 10/27/2016 10:11 PM, Scott Wood wrote:
>> On 10/27/2016 04:27 AM, Prabhakar Kushwaha wrote:
>>> Hi Masahiro,
>>>
>>> I am not able to boot Linux onF PowerPC platform with ramdisk size > 100MB.
>>> I tried u-boot master with top commit as
On 10/27/2016 02:06 AM, Wenbin song wrote:
> The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment
> and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] is used to choose
> which offset will be used. If GIC_ADDR_BIT bit is set, 4K alignment is used,
> or else 64K
Add support for EFI console modes.
Mode 0 is always 80x25 and present by EFI specification.
Mode 1 is always 80x50 and not mandatory.
Mode 2 and above is freely usable.
If the terminal can handle mode 1, we mark it as supported.
If the terminal size is greater than mode 0 and different than mode
On 10/27/2016 10:11 PM, Scott Wood wrote:
> On 10/27/2016 04:27 AM, Prabhakar Kushwaha wrote:
>> Hi Masahiro,
>>
>> I am not able to boot Linux onF PowerPC platform with ramdisk size > 100MB.
>> I tried u-boot master with top commit as "
>> 5ac5861c4ba851b473e6a24940b412b397627d8d ".
>>
>> I
On Wed, 2016-10-26 at 16:30 +, Simon Glass wrote:
> Hi,
>
> On 21 October 2016 at 01:10, Marek Vasut wrote:
> >
> > On 10/21/2016 08:52 AM, Marcel Ziswiler wrote:
> > >
> > > Hi Simon
> > >
> > > On Thu, 2016-10-20 at 13:06 -0600, Simon Glass wrote:
> > > >
> > > > Only
On Freitag, 28. Oktober 2016 01:52:26 CEST Marek Vasut wrote:
[...]
> > +
> > +enum fdt_fsl_usb_erratum {
> > + A006261,
> > + A007075,
> > + A007792,
> > + A005697,
> > + A008751,
> > + FSL_USB_ERRATUM_END
>
> The compiler can assign completely arbitrary numbers to the enum
>
Hi Tom,
please pull from u-boot-imx, thanks !
There are two major patchsets in this PR:
- plugin support from Peng
- Jagan's support for Engicam i.CoreM6 , with several
move to Kconfig.
The following changes since commit ebf7fff20ab8127f318b238e47a21856497bd6fe:
spl: move
Hello,
On Thu, Oct 27, 2016 at 3:00 PM, Nicolae Rosia
wrote:
> [0] https://bugs.launchpad.net/qemu/+bug/1579327?comments=all
Booting a Linux kernel with -smp 4 works just fine, so I believe the
bug is in u-boot.
Thanks,
Nicolae
Thanks Scott,
> -Original Message-
> From: Scott Wood
> Sent: Friday, October 28, 2016 10:41 AM
> To: Prabhakar Kushwaha ; u-
> b...@lists.denx.de; yamada.masah...@socionext.com
> Cc: york sun
> Subject: Re: FSL PowerPC platform: Not able to
On 28/10/2016 16:02, Jagan Teki wrote:
> On Thu, Oct 27, 2016 at 7:37 PM, Stefano Babic wrote:
>> On 26/10/2016 18:35, Jagan Teki wrote:
>>> On Wed, Oct 26, 2016 at 8:38 PM, Stefano Babic wrote:
Hi Jagan,
On 25/10/2016 08:23, Jagan Teki wrote:
On Thu, Oct 27, 2016 at 7:37 PM, Stefano Babic wrote:
> On 26/10/2016 18:35, Jagan Teki wrote:
>> On Wed, Oct 26, 2016 at 8:38 PM, Stefano Babic wrote:
>>> Hi Jagan,
>>>
>>>
>>> On 25/10/2016 08:23, Jagan Teki wrote:
From: Jagan Teki
From: Jagan Teki
Add I2C support for Engicam i.CoreM6 qdl board.
icorem6qdl> i2c bus
Bus 0: i2c@021a
Bus 1: i2c@021a4000
Bus 2: i2c@021a8000
icorem6qdl> i2c dev 2
Setting bus to 2
icorem6qdl> i2c speed 10
Setting bus speed to 10 Hz
icorem6qdl> i2c
From: Jagan Teki
Better to print the hex value for bus address instead of
decimal, for more readbility on bus addressing.
Before:
--
U-Boot> i2c dev 1
Setting bus to 1
i2c bus 1 at 35274752, no gpio pinctrl state.
After:
--
U-Boot> i2c dev 1
Setting bus to 1
From: Jagan Teki
Some I2C bus devicetree nodes, doesn't require to have
gpio pinctrl so replace the dev_info to debug so the
print never comes on the console and for bus that uses
gpio pinctrl anyway have dev_err.
Before:
--
U-Boot> i2c dev 1
Setting bus to 1
i2c
From: Jagan Teki
Added kconfig for SYS_I2C_MXC driver.
Cc: Stefano Babic
Cc: Heiko Schocher
Cc: Matteo Lisi
Cc: Michael Trimarchi
Signed-off-by: Jagan Teki
From: Jagan Teki
Add custom splashscreen, engicam.bmp support for
Engicam i.CoreM6 qdl board.
Cc: Anatolij Gustschin
Cc: Stefano Babic
Cc: Matteo Lisi
Cc: Michael Trimarchi
From: Jagan Teki
This series support framebuffer and I2C on top of u-boot-imx.git with
latest u-boot.git merge.
Changes for v2:
- Rebase on u-boot-imx.git and u-boot.git
Jagan Teki (7):
video: Kconfig: Add VIDEO_IPV3 entry
imx6: icorem6: Add framebuffer support
From: Jagan Teki
Add IPUv3 framebuffer support for Engicam i.CoreM6 qdl board.
Cc: Anatolij Gustschin
Cc: Stefano Babic
Cc: Matteo Lisi
Cc: Michael Trimarchi
Signed-off-by:
From: Jagan Teki
Added kconfig entry for CONFIG_VIDEO_IPV3 driver.
Cc: Anatolij Gustschin
Cc: Stefano Babic
Cc: Matteo Lisi
Cc: Michael Trimarchi
Signed-off-by: Jagan Teki
On Wed, Sep 28, 2016 at 03:16:38PM +0800, Hongbo Zhang wrote:
> On Wed, Sep 28, 2016 at 1:23 AM, Tom Rini wrote:
> > On Tue, Sep 27, 2016 at 05:29:00PM +0800, macro.wav...@gmail.com wrote:
> >> From: Hongbo Zhang
> >>
> >> This patch set introduces ARMv8
On Fri, Oct 28, 2016 at 12:01:44PM +0530, Keerthy wrote:
> Clear the XN bit in the ARMV7_DCACHE_POLICY so as to mark
> the regions as execute okay.
>
> Signed-off-by: Keerthy
Reviewed-by: Tom Rini
--
Tom
signature.asc
Description: Digital signature
On Fri, Oct 28, 2016 at 12:01:43PM +0530, Keerthy wrote:
> While we setup the mmu initially we mark set_section_dcache with
> DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro
> is rightly defined with TTB_SECT_XN_MASK set so as to mark all the
> 4GB XN. In case of LPAE mode
On Fri, Oct 28, 2016 at 07:13:37AM -0400, Tom Rini wrote:
> From: Bin Meng
>
> Introduce CONFIG_PCI_PNP in Kconfig and move over boards' defconfig
> to use that.
>
> Signed-off-by: Bin Meng
> Reviewed-by: Tom Rini
> [trini:
On Wed, Oct 26, 2016 at 05:15:37PM -0400, Tom Rini wrote:
> Add 'PCI' as a menu option and migrate all existing users.
>
> Signed-off-by: Tom Rini
> Acked-by: Stephen Warren
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: Digital
From: Bin Meng
Introduce CONFIG_PCI_PNP in Kconfig and move over boards' defconfig
to use that.
Signed-off-by: Bin Meng
Reviewed-by: Tom Rini
[trini: Re-generate configs and include/configs/ changes]
Signed-off-by: Tom Rini
On Tue, Sep 27, 2016 at 11:00:33AM +0800, Wenyou Yang wrote:
> Due to the peripheral clock driver improvement, remove the
> unnecessary clock calling.
>
> Signed-off-by: Wenyou Yang
Reviewed-by: Andreas Bießmann
> ---
>
> Changes in v3: None
>
On Fri, 28 Oct 2016 11:33:19 +0200
Alexander Graf wrote:
> On 10/28/2016 10:04 AM, Emmanuel Vadot wrote:
> > Add support for EFI console modes.
> > Mode 0 is always 80x25 and present by EFI specification.
> > Mode 1 is always 80x50 and not mandatory.
> > Mode 2 and above is freely
Hi everyone,
This series adds full SPL with DRAM initialization for sun9i (A80).
The bulk of the work was done by the people at Theobroma Systems.
Their work can be found here:
https://git.theobroma-systems.com/armadillo-u-boot.git/
I picked the essential patches and cleaned them up a bit
From: Philipp Tomsich
On sun9i, the GTBUS manages transaction priority and bandwidth
for multiple read ports when accessing DRAM. The initialisation
mirrors the settings from Allwinner's boot0 for now, even though
this may not be optimal for all
From: Philipp Tomsich
This adds DRAM initialisation code for sun9i, which calculates the
appropriate timings based on timing information for the supplied
DDR3 bin and the clock speeds used.
With this DRAM setup, we have verified DDR3 clocks of up to 792MHz
In Allwinner's SDK the A80 is clocked to 1008 MHz by default.
Signed-off-by: Chen-Yu Tsai
---
board/sunxi/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index ee6ae37fb7ef..5cca1eae73b3 100644
---
Both the A80 Optimus board and the Cubieboard 4 use a zq value of
4145117, or 0x3f3fdd.
Signed-off-by: Chen-Yu Tsai
---
board/sunxi/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 5cca1eae73b3..e1d4ab148f08 100644
---
The A80 has SID e-fuses. Like other newer SoCs, the actual e-fuses
are at an offset of 0x200 within the SID address space.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 2 ++
1 file changed, 2 insertions(+)
diff --git
The A80 Optimus Board was launched with the Allwinner A80 SoC.
It was jointly developed by Allwinner and Merrii.
This board has a UART port, a JTAG connector, 2 USB host ports, a USB
3.0 OTG connector, an HDMI output, a micro SD slot, 16G eMMC flash,
2G DRAM, a camera sensor interface, a WiFi/BT
From: Philipp Tomsich
Since the A80 has many cores which we intend to use in SMP fashion,
we should set the SMP bit for the boot CPU.
[w...@csie.org: Added commit message]
Signed-off-by: Chen-Yu Tsai
---
arch/arm/mach-sunxi/board.c | 3 ++-
From: Philipp Tomsich
The A80 can support 8-bit eMMC with reset on the PC pingroups.
Signed-off-by: Chen-Yu Tsai
---
board/sunxi/board.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
From: Philipp Tomsich
This is a cleaned up version set_pll() from Allwinner's boot0 source
(bootloader/basic_loader/bsp/bsp_for_a80/common/common.c).
[w...@csie.org: Added commit message; style cleanup]
Signed-off-by: Chen-Yu Tsai
---
The Cubieboard4 is an A80 SoC based development board from Cubietech.
This board has a UART port, 4 USB host ports, a USB 3.0 OTG connector,
HDMI and VGA outputs, a micro SD slot, 8G eMMC flash, 2G DRAM, a WiFi/BT
combo chip, headphone and microphone jacks, IR receiver, and GPIO headers.
From: Philipp Tomsich
Now that DRAM initialization and clock setup is supported,
we can enable SPL for the A80.
[w...@csie.org: Added commit message]
Signed-off-by: Chen-Yu Tsai
---
board/sunxi/Kconfig | 1 +
1 file changed, 1 insertion(+)
On Wed, Aug 17, 2016 at 09:13:24AM +0200, Heiko Schocher wrote:
> on at91sam9x5 PRES offset is 4 in the PMC master
> clock register.
>
> Signed-off-by: Heiko Schocher
> Acked-by: Wenyou Yang
Acked-by: Andreas Bießmann
> ---
>
>
On 10/28/2016 10:04 AM, Emmanuel Vadot wrote:
Add support for EFI console modes.
Mode 0 is always 80x25 and present by EFI specification.
Mode 1 is always 80x50 and not mandatory.
Mode 2 and above is freely usable.
If the terminal can handle mode 1, we mark it as supported.
If the terminal size
Add support for EFI console modes.
Mode 0 is always 80x25 and present by EFI specification.
Mode 1 is always 80x50 and not mandatory.
Mode 2 and above is freely usable.
If the terminal can handle mode 1, we mark it as supported.
If the terminal size is greater than mode 0 and different than mode
Signed-off-by: Patrick Delaunay
---
drivers/dfu/dfu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c
index 20dfcbb..8dacc1a 100644
--- a/drivers/dfu/dfu.c
+++ b/drivers/dfu/dfu.c
@@ -482,7 +482,7 @@ int
On 10/27/2016 04:27 AM, Prabhakar Kushwaha wrote:
> Hi Masahiro,
>
> I am not able to boot Linux onF PowerPC platform with ramdisk size > 100MB.
> I tried u-boot master with top commit as "
> 5ac5861c4ba851b473e6a24940b412b397627d8d ".
>
> I tried git-bisect and figured out below patch causing
On Friday 28 October 2016 12:56 PM, Alexander Graf wrote:
On 28/10/2016 08:31, Keerthy wrote:
Clear the XN bit in the ARMV7_DCACHE_POLICY so as to mark
the regions as execute okay.
Signed-off-by: Keerthy
How did you ever get the bit set in DCACHE_WRITEALLOC or
Enable early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: Wenyou Yang
---
board/atmel/sama5d3_xplained/sama5d3_xplained.c | 16 +++-
configs/sama5d3_xplained_mmc_defconfig | 6 ++
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