On Mon, Feb 11, 2019 at 1:41 PM Anup Patel wrote:
>
> Some of the drivers (such as Cadence MACB ethernet driver) expect
> asm/arch/clk.h to be provided by arch support so we add place-holder
> asm/arch-generic/clk.h for RISC-V generic CPU.
>
> Signed-off-by: Anup Patel
> Reviewed-by: Lukas Auer
On Mon, Feb 11, 2019 at 1:41 PM Anup Patel wrote:
>
> We select CREATE_ARCH_SYMLINK for RISC-V so that we can have
> include/asm/arch linked to include/asm/arch-xyz.
>
> Signed-off-by: Anup Patel
> ---
> arch/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Bin Meng
This patch adds a comment to the header with the PCI_foo macros related
to DEVFN to explain the difference in U-Boot vs Linux.
Signed-off-by: Stefan Roese
Cc: Simon Glass
Cc: Bin Meng
---
include/pci.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/include/pci.h
On Sun, Jan 13, 2019 at 10:12 PM Hauke Mehrtens wrote:
>
> The Detection pin is at PF6 and not at PH13 like defined before. I
> checked the schematics and now I am am not seeing this error message any
> more:
> Loading Environment from FAT... Card did not respond to voltage select!
>
>
On Sun, Feb 10, 2019 at 3:46 PM Neil Armstrong wrote:
>
> There is no reason not to use the Linux "jedec,spi-nor" binding in u-boot.
> This patchset :
> - switches all DTS/DTSI files to "jedec,spi-nor"
> - remove the "spi-flash" compatible from sf-probe
> - switch GENERIC_SPI_FLASH to
On Fri, Feb 8, 2019 at 3:33 PM Heiko Schocher wrote:
>
> Add support for SPANSION s25fl064l
>
> Signed-off-by: Heiko Schocher
> ---
Applied to u-boot-spi/next
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
From: Eugen Hristev
SPL_GENERATE_ATMEL_PMECC_HEADER will generate a header for the SPL for NAND
information. The initial stage 1 bootloader will use this header in case the
NAND flash doesn't support commands to retrieve sector size, etc.
However this header is bad for different boot media, like
Hi Krzysztof,
> Detection of board type is done early - before power setup. In case
> of Odroid XU3/XU4/HC1 family, the detection is done using ADC which
> is supplied by LDO4/VDD_ADC regulator. This regulator could be turned
> off (e.g. by kernel before reboot); If ADC is used early, the
>
Hi Krzysztof,
> Add startup time to LDO regulators of S2MPS11 PMIC on Odroid
> XU3/XU4/HC1 family of boards to be sure the voltage is proper before
> relying on the regulator.
>
> The datasheet for all the S2MPS1x family is inconsistent here and does
> not specify unambiguously the value of ramp
Hi Krzysztof,
> According to datasheet, the output on LDO regulators will start
> appearing after 10-15 us.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> drivers/power/regulator/s2mps11_regulator.c | 9 -
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git
On Thu, Feb 7, 2019 at 4:52 PM Baruch Siach wrote:
>
> Commit dc146ca11187 ("Kconfig: Migrate CONFIG_BUILD_TARGET") made the
> mvebu default build target depend on CONFIG_SPL_BUILD. Unfortunately,
> there is no such Kconfig symbol. Use the CONFIG_SPL symbol instead to
> fix that.
>
> Cc: Jagan
Since Ethernet clock and reset is now handling via
CLK and RESET frameworks via driver API's remove
explicit ccm writes.
Signed-off-by: Jagan Teki
---
board/sunxi/gmac.c | 8
1 file changed, 8 deletions(-)
diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c
index
Add EPHY CLK and RESET support for sun8i_emac driver to
enable EPHY TX clock and EPHY reset pins via CLK and RESET
framework.
Cc: Joe Hershberger
Cc: Lothar Felten
Signed-off-by: Jagan Teki
---
drivers/net/sun8i_emac.c | 72 ++--
1 file changed, 55
EPHY CLK and RESET is availble in Allwinner H3 EMAC
via mdio-mux node of internal PHY. Add the respetive
clock and reset reg and bits.
Cc: Joe Hershberger
Signed-off-by: Jagan Teki
---
drivers/clk/sunxi/clk_h3.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/sunxi/clk_h3.c
Getting a RESET by index with device is not straight forward
for some use-cases like handling clock operations for child
node in parent driver. So we need to process the child node
in parent probe via ofnode and process RESET operation for child
without udevice but with ofnode.
So add
Getting a CLK by index with device is not straight forward
for some use-cases like handling clock operations for child
node in parent driver. So we need to process the child node
in parent probe via ofnode and process CLK operation for child
without udevice but with ofnode.
So add
clk_get_by_index_tail() now handle common clk get by index
code so use it in relevant places.
Cc: Stephen Warren
Signed-off-by: Jagan Teki
Reviewed-by: Simon Glass
---
drivers/clk/clk-uclass.c | 77 +---
1 file changed, 25 insertions(+), 52 deletions(-)
Add sample dm clk test for clk_get_by_index and
clk_get_by_index_nodev functionality code.
Cc: Stephen Warren
Cc: Simon Glass
Signed-off-by: Jagan Teki
---
test/dm/clk.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/test/dm/clk.c b/test/dm/clk.c
index
Add sample dm reset test for reset_get_by_index and
reset_get_by_index_nodev functionality code.
Cc: Stephen Warren
Cc: Simon Glass
Signed-off-by: Jagan Teki
---
test/dm/reset.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/test/dm/reset.c b/test/dm/reset.c
index
Add CLK and RESET support for sun8i_emac driver to
enable TX clock and reset pins via CLK and RESET
framework.
Cc: Joe Hershberger
Cc: Lothar Felten
Signed-off-by: Jagan Teki
---
drivers/net/sun8i_emac.c | 57 +---
1 file changed, 42 insertions(+), 15
- Implement EMAC, GMAC clocks via ccu_clk_gate for
all supported Allwinner SoCs.
- Implement EMAC, GMAC resets via ccu_reset for all
supported Allwinner SoCs.
Cc: Joe Hershberger
Signed-off-by: Jagan Teki
---
drivers/clk/sunxi/clk_a31.c | 2 ++
drivers/clk/sunxi/clk_a64.c | 2 ++
Unlike other Allwinner SoC's R40 GMAC clock control register
is locate in CCU, but rest located via syscon itself. Since
the phandle property for current code look for 'syscon' and
it will grab the respective ccu or syscon base address based
on DT property defined in respective SoC dtsi.
So, use
Implement EMAC clocks via ccu_clk_gate for Allwinner A10 SoC.
Which would eventually used in sunxi_emac.c driver.
Signed-off-by: Jagan Teki
---
drivers/clk/sunxi/clk_a10.c | 1 +
drivers/clk/sunxi/clk_a10s.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/clk/sunxi/clk_a10.c
Add CLk support for sunxi_emac to enable AHB_EMAC clock
via CLK framework.
Cc: Joe Hershberger
Signed-off-by: Jagan Teki
---
drivers/net/sunxi_emac.c | 28 ++--
image.map| 4
2 files changed, 26 insertions(+), 6 deletions(-)
create mode 100644
This is v2 version for Allwinner EMAC CLK, RESET support, which
was initially be a part of previous series[1].
Changes for v2:
- rebase on master
- add dm tests for new clk and reset functions.
Any inputs?
Jagan.
[1] https://patchwork.ozlabs.org/patch/959351/
Jagan Teki (13):
clk: sunxi:
On 11. 02. 19 7:20, Heiko Schocher wrote:
> Hello Michal,
>
> Am 08.02.2019 um 12:24 schrieb Michal Simek:
>> On 08. 02. 19 12:14, Michal Simek wrote:
>>> On 08. 02. 19 10:57, Heiko Schocher wrote:
Hello Michael,
Am 31.01.2019 um 16:30 schrieb Michal Simek:
> U-Boot with I2C_DM
From: Tien Fong Chee
Release cluster block immediately when no longer use would help to reduce
64KiB memory allocated to the memory pool.
Signed-off-by: Tien Fong Chee
---
changes for v3
- Dropped the if conditional because free(NULL) is valid.
---
fs/fat/fat.c | 10 +-
1 file
From: Tien Fong Chee
Drop the statically allocated get_contents_vfatname_block and
dynamically allocate a buffer only if required. This saves
64KiB of memory.
Signed-off-by: Stefan Agner
Signed-off-by: Tien Fong Chee
---
changes for v3
- Removed the cast on actsize
---
fs/fat/fat.c | 18
Hi Marek,
> When using CMD6 to switch eMMC card timing from HS200/HS400 to
> HS/legacy, do not poll for the completion status using CMD13, but
> rather wait 50mS.
Nit: mS -> ms
>
> Once the card receives the CMD6 and starts executing it, the bus is in
> undefined state until both the card
On Fri, 2019-02-01 at 23:06 -0700, Simon Glass wrote:
On Thu, 31 Jan 2019 at 04:34,
mailto:tien.fong.c...@intel.com>> wrote:
>
> From: Tien Fong Chee
> mailto:tien.fong.c...@intel.com>>
>
> Firmware loader would encounter problem if the block device is accessed
> before initializing it. This
This patch adds a comment to explain the use of the hardcoded value for
the number of address cells in mvebu_get_tgt_attr(). This should help to
rework this function, once CONFIG_OF_LIVE is enabled for MVEBU in
general.
Signed-off-by: Stefan Roese
Cc: Bin Meng
---
drivers/pci/pci_mvebu.c | 6
Hi Bin,
On 11.02.19 04:25, Bin Meng wrote:
Hi Stefan,
On Thu, Jan 31, 2019 at 10:41 PM Bin Meng wrote:
Hi Stefan,
On Fri, Jan 25, 2019 at 6:53 PM Stefan Roese wrote:
This patch adds DM_PCI support to the MVEBU PCIe driver. This is
necessary, since all PCI drivers have to be moved to DM
On Mon, Feb 11, 2019 at 7:06 PM Stefan Roese wrote:
>
> Hi Chris,
>
> On 11.02.19 02:11, Chris Packham wrote:
> > Hi Jagan,
> >
> > I've just tried this out on x530 and db-88f6820-amc (both ARCH_MVEBU).
> >
> > On Fri, Jan 18, 2019 at 8:23 PM Jagan Teki
> > wrote:
> >>
> >> Migrate
Hi Uri,
I see following warnings when building configs/cl-som-am57x_defconfig[1]
which means board has not be moved to U-Boot Driver Model and Device Tree.
Do you have plans to move configs/cl-som-am57x_defconfig to DM and enable
CONFIG_DM and other DM framework?
This is coming in the way of
On Tue, 2019-02-05 at 09:51 +0100, Marek Vasut wrote:
> On 2/1/19 5:50 PM, Chee, Tien Fong wrote:
> >
> > On Fri, 2019-02-01 at 09:29 +0100, Marek Vasut wrote:
> > >
> > > On 2/1/19 4:59 AM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Thu, 2019-01-31 at 15:54 +0100, Marek Vasut wrote:
>
Hello Michal,
Am 08.02.2019 um 12:24 schrieb Michal Simek:
On 08. 02. 19 12:14, Michal Simek wrote:
On 08. 02. 19 10:57, Heiko Schocher wrote:
Hello Michael,
Am 31.01.2019 um 16:30 schrieb Michal Simek:
U-Boot with I2C_DM enabled is not capable to list i2c busses connected
to i2c mux. For
Hi Chris,
On 11.02.19 02:11, Chris Packham wrote:
Hi Jagan,
I've just tried this out on x530 and db-88f6820-amc (both ARCH_MVEBU).
On Fri, Jan 18, 2019 at 8:23 PM Jagan Teki wrote:
Migrate CONFIG_BUILD_TARGET into Kconfig.
Signed-off-by: Jagan Teki
---
diff --git a/Kconfig b/Kconfig
This patch enables CONFIG_SYS_BOOT_RAMDISK_HIGH for RISC-V
because bootm will update initrd location in DTB only if
CONFIG_SYS_BOOT_RAMDISK_HIGH is enabled. If we don't enable
this option then bootm assumes DTB already has initrd details
which is not the case most of the time.
Signed-off-by:
From: Atish Patra
The readme guide describes the procedure to build, flash and boot Linux
using U-Boot on HiFive Unleashed. It also explains the current state of
U-boot support and future action items.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Reviewed-by: Lukas Auer
---
From: Atish Patra
Currently, timer driver is bound only for hart0.
There is no mandatory requirement that hart0 should always
come up. In fact, HiFive Unleashed SoC hart0 doesn't boot
in S-mode because it only has M-mode.
The timer driver should be bound for boot hart.
Signed-off-by: Atish
Add driver code for the SiFive FU540 PRCI IP block. This IP block
handles reset and clock control for the SiFive FU540 device and
implements SoC-level clock tree controls and dividers.
Based on code written by Wesley Terpstra
found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of:
This patch adds fixed-factor clock driver which derives clock
rate by dividing (div) and multiplying (mult) fixed factors
to a parent clock.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
---
arch/sandbox/dts/test.dts | 8
drivers/clk/Makefile | 4 +-
From: Atish Patra
It is possible that input clock is not available because clk
device was not available and 'clock-frequency' DT property is
also not available.
In this case, instead of failing we should just skip baudrate
config by returning zero.
Signed-off-by: Atish Patra
Signed-off-by:
This patch adds SiFive FU540 board support. For now, only
SiFive serial, SiFive PRCI, and Cadance MACB drivers are
only enabled. The SiFive FU540 defconfig by default builds
U-Boot for S-Mode because U-Boot on SiFive FU540 will run
in S-Mode as payload of BBL or OpenSBI.
Signed-off-by: Atish
From: Atish Patra
Fix MID bit field check to correctly identify all GEM hardwares.
The check is updated as per macb driver in Linux location:
/drivers/net/ethernet/cadence/macb_main.c:259
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Reviewed-by: Alexander Graf
Reviewed-by: Lukas
On 64bit systems, the DRAM top can be easily beyond 4GB and U-Boot
DMA mapping APIs will generate DMA addresses beyond 4GB. This
breaks DMA programming in 32bit DMA capable devices (such as
Cadence MACB ethernet). For example, If DRAM is more then 2GB
on QEMU sifive_u machine then Cadence MACB
From: Atish Patra
Compute the baud rate multipler with more precision.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Reviewed-by: Alexander Graf
Reviewed-by: Lukas Auer
---
drivers/serial/serial_sifive.c | 28 ++--
1 file changed, 26 insertions(+), 2
This patch adds asm/dma-mapping.h for Linux-like DMA mappings
APIs required by some of the drivers (such as, Cadance MACB
Ethernet driver).
Signed-off-by: Anup Patel
Reviewed-by: Bin Meng
Reviewed-by: Alexander Graf
Reviewed-by: Lukas Auer
---
arch/riscv/include/asm/dma-mapping.h | 38
Don't fail in macb_enable_clk() if clk_enable() returns
-ENOSYS because we get -ENOSYS for fixed-rate clocks.
Signed-off-by: Anup Patel
Reviewed-by: Bin Meng
---
drivers/net/macb.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/net/macb.c
The QEMU CPU support under arch/riscv is pretty much generic
and works fine for SiFive Unleashed as well. In fact, there
will be quite a few RISC-V SOCs for which QEMU CPU support
will work fine.
This patch renames cpu/qemu to cpu/generic to indicate the
above fact. If there are SOC specific
Some of the drivers (such as Cadence MACB ethernet driver) expect
asm/arch/clk.h to be provided by arch support so we add place-holder
asm/arch-generic/clk.h for RISC-V generic CPU.
Signed-off-by: Anup Patel
Reviewed-by: Lukas Auer
---
arch/riscv/include/asm/arch-generic/clk.h | 14
We select CREATE_ARCH_SYMLINK for RISC-V so that we can have
include/asm/arch linked to include/asm/arch-xyz.
Signed-off-by: Anup Patel
---
arch/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/Kconfig b/arch/Kconfig
index 35e2712fce..4ebc66227e 100644
--- a/arch/Kconfig
+++
This patchset adds SiFive Freedom Unleashed (FU540) support
to RISC-V U-Boot.
The patches are based upon latest U-Boot source tree
(git://git.denx.de/u-boot.git) at commit id
dbe70c7d4e3d5c705a98d82952e05a591efd0683
All drivers namely: SiFive PRCI, SiFive Serial, and Cadance
MACB Ethernet work
On Tue, 2019-02-05 at 09:46 +0100, Marek Vasut wrote:
> On 2/1/19 5:02 PM, Chee, Tien Fong wrote:
> >
> > On Fri, 2019-02-01 at 09:25 +0100, Marek Vasut wrote:
> > >
> > > On 2/1/19 4:48 AM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Thu, 2019-01-31 at 15:54 +0100, Marek Vasut wrote:
>
On 08/02/19 3:33 PM, Heiko Schocher wrote:
> Add support for SPANSION s25fl064l
>
> Signed-off-by: Heiko Schocher
> ---
>
> Changes in v2:
> - s/s25f064l/s25fl064l
> as Vignesh R suggested
>
> drivers/mtd/spi/spi-nor-ids.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git
Hi,
On 09/02/19 10:59 PM, Jagan Teki wrote:
> On Mon, Jan 7, 2019 at 2:24 PM Ye Li wrote:
>>
>> From: Han Xu
>>
>> Support to read the flag status in driver to avoid the spi-nor framework
>> wait_for_ready hang issue.
>>
>> Signed-off-by: Han Xu
>> ---
>> drivers/spi/fsl_qspi.c | 47
On 11/02/19 9:01 AM, Adam Ford wrote:
> On Tue, Feb 5, 2019 at 12:00 AM Vignesh R wrote:
>>
>> Switch spi_flash_* interfaces to call into new SPI NOR framework via MTD
>> layer. Fix up sf_dataflash to work in legacy way. And update sandbox to
>> use new interfaces/definitions
>>
>>
> -Original Message-
> From: Auer, Lukas [mailto:lukas.a...@aisec.fraunhofer.de]
> Sent: Monday, February 11, 2019 12:10 AM
> To: s...@chromium.org; michal.si...@xilinx.com; bmeng...@gmail.com;
> joe.hershber...@ni.com; r...@andestech.com;
> yamada.masah...@socionext.com;
> -Original Message-
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Monday, February 11, 2019 8:51 AM
> To: Anup Patel
> Cc: Rick Chen ; Joe Hershberger
> ; Michal Simek ; Michal
> Simek ; Lukas Auer
> ; Masahiro Yamada
> ; Simon Glass ;
> Alexander Graf ; Palmer Dabbelt ;
> Paul
> -Original Message-
> From: Tom Rini [mailto:tr...@konsulko.com]
> Sent: Monday, February 11, 2019 6:43 AM
> To: Auer, Lukas
> Cc: s...@chromium.org; michal.si...@xilinx.com; bmeng...@gmail.com;
> joe.hershber...@ni.com; r...@andestech.com;
> yamada.masah...@socionext.com;
On Mon, 2019-02-04 at 11:58 +0100, Fabien Parent wrote:
> Some MediaTek SoC need an additional clock "source_cg". Enable
> this new clock. We reuse the same clock name as in the kernel.
>
> Signed-off-by: Fabien Parent
Acked-by: Ryder Lee
> ---
> drivers/mmc/mtk-sd.c | 8
> 1 file
On Tue, Feb 5, 2019 at 12:00 AM Vignesh R wrote:
>
> Switch spi_flash_* interfaces to call into new SPI NOR framework via MTD
> layer. Fix up sf_dataflash to work in legacy way. And update sandbox to
> use new interfaces/definitions
>
> Signed-off-by: Vignesh R
> Tested-by: Simon Goldschmidt
>
Hi Stefan,
On Thu, Jan 31, 2019 at 10:41 PM Bin Meng wrote:
>
> Hi Stefan,
>
> On Fri, Jan 25, 2019 at 6:53 PM Stefan Roese wrote:
> >
> > This patch adds DM_PCI support to the MVEBU PCIe driver. This is
> > necessary, since all PCI drivers have to be moved to DM (driver model)
> > until the
On Sat, Feb 9, 2019 at 2:31 PM Anup Patel wrote:
>
> Some of the drivers expect asm/arch/clk.h to be provided by
> arch support code so we add place-holder asm/arch/clk.h for
> RISC-V support.
>
> Signed-off-by: Anup Patel
> ---
> arch/riscv/include/asm/arch/clk.h | 14 ++
> 1 file
On Mon, 2019-02-04 at 11:58 +0100, Fabien Parent wrote:
> Add clock driver for MediaTek MT8516 SoC.
>
> Signed-off-by: Fabien Parent
> ---
> drivers/clk/mediatek/Makefile | 1 +
> drivers/clk/mediatek/clk-mt8516.c | 802 +
>
On 2/10/19 10:47 AM, Auer, Lukas wrote:
On Sat, 2019-02-09 at 06:33 +, Anup Patel wrote:
From: Atish Patra
The readme guide describes the procedure to build, flash and boot
Linux
using U-boot on HiFive Unleashed. It also explains the current state
of
U-boot support and future action
On Sun, Feb 10, 2019 at 1:38 AM Jagan Teki wrote:
>
> On Fri, Jan 25, 2019 at 4:08 PM Chen-Yu Tsai wrote:
> >
> > As of commit aa8fee415f46 ("ARM: dts: sun8i: h3: Split out
> > non-SoC-specific parts of Bananapi M2 Plus") in the Linux kernel, the
> > device tree for the Bananapi M2+ has been
On Mon, 2019-02-04 at 11:58 +0100, Fabien Parent wrote:
> Add the implementation for the CLK_GATE_SETCLR_INV flag.
>
> Signed-off-by: Fabien Parent
Acked-by: Ryder Lee
> ---
> drivers/clk/mediatek/clk-mtk.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git
On Mon, 2019-02-04 at 11:58 +0100, Fabien Parent wrote:
> Add config for handling MT8516 SoC.
>
> Signed-off-by: Fabien Parent
Acked-by: Ryder Lee
> ---
> drivers/mmc/mtk-sd.c | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
>
On Mon, 2019-02-04 at 11:58 +0100, Fabien Parent wrote:
> Add Pinctrl driver for MediaTek MT8516 SoC.
>
> Signed-off-by: Fabien Parent
> ---
> drivers/pinctrl/mediatek/Kconfig | 4 +
> drivers/pinctrl/mediatek/Makefile | 1 +
> drivers/pinctrl/mediatek/pinctrl-mt8516.c |
Hi,
I am trying to get a uboot image for a AP143 reference board (Mips)
The "make" gives the error below
Can you help ?
Thank you
[root/ u-boot]# make menuconfig
scripts/kconfig/mconf Kconfig
configuration written to .config
*** End of the configuration.
*** Execute 'make' to
SPL_BUILD is defined by Makefile.spl when building the SPL part of the
image. It can't be used by Kconfig. SPL is known to Kconfig and is
defined if the target uses an SPL. Make the condition for BUILD_TARGET
depend on ARCH_MVEBU && SPL so that the overall build produces
u-boot-spl.kwb.
Fixes:
MV_DDR_FREQ_SAR lets the DDR frequency be determined by hardware
strapping. This also has the side effect of running the DDR clock in
synchronous mode with the CPU core clock rather than from an independent
PLL. We've seen this improve reliability in operation across a number of
boards and
On Sun, Feb 10, 2019 at 06:31:02PM +, Auer, Lukas wrote:
> On Sat, 2019-02-09 at 06:31 +, Anup Patel wrote:
> > Currently, the mrproper make target tries to force remove all
> > "arch/*/include/asm/arch" paths assuming they are symlinks but
> > this prevents us from adding place-holder
Hi Jagan,
I've just tried this out on x530 and db-88f6820-amc (both ARCH_MVEBU).
On Fri, Jan 18, 2019 at 8:23 PM Jagan Teki wrote:
>
> Migrate CONFIG_BUILD_TARGET into Kconfig.
>
> Signed-off-by: Jagan Teki
> ---
> diff --git a/Kconfig b/Kconfig
> index aff7b2e00a..15b79259a8 100644
> ---
On Sun, Feb 10, 2019 at 12:11:21AM +0100, Marek Vasut wrote:
> Here are the four fixes which do not trigger the sunxi breakage.
>
> The following changes since commit 97276a91db8e98f081a40ddf9dc8f81d4032a756:
>
> Prepare v2019.04-rc1 (2019-02-07 21:32:19 -0500)
>
> are available in the Git
On Sun, Feb 10, 2019 at 03:27:56AM -0600, Simon Glass wrote:
> Hi Tom,
>
> I thought I had already sent these but just noticed that I had not.
>
> The following changes since commit 97276a91db8e98f081a40ddf9dc8f81d4032a756:
>
> Prepare v2019.04-rc1 (2019-02-07 21:32:19 -0500)
>
> are
SPL currently does not check uImage CRCs when loading U-Boot.
This patch adds checking the uImage CRC when SPL loads U-Boot. It does
this by reusing the existing config option SPL_CRC32_SUPPORT to allow
leaving out the CRC check on boards where the additional code size or
boot time is a problem
Hi Tim,
On 5/02/19 9:57 AM, Tim Harvey wrote:
> phy_reset should be called before autoneg is setup
>
> The only boards using MV88E61XX_SWITCH are:
> - alliedtelesis/SBx81LIFKW
> - alliedtelesis/SBx81LIFXCAT
> - gateworks/gw_ventana
>
> Cc: Chris Packham
> Signed-off-by: Tim Harvey
On Sat, 2019-02-09 at 06:33 +, Anup Patel wrote:
> This patch enables CONFIG_SYS_BOOT_RAMDISK_HIGH for RISC-V
> because bootm will update initrd location in DTB only if
> CONFIG_SYS_BOOT_RAMDISK_HIGH is enabled. If we don't enable
> this option then bootm assumes DTB already has initrd details
On Sat, 2019-02-09 at 06:33 +, Anup Patel wrote:
> From: Atish Patra
>
> The readme guide describes the procedure to build, flash and boot
> Linux
> using U-boot on HiFive Unleashed. It also explains the current state
> of
> U-boot support and future action items.
nit: U-Boot
>
>
On Sat, 2019-02-09 at 06:32 +, Anup Patel wrote:
> Add driver code for the SiFive FU540 PRCI IP block. This IP block
> handles reset and clock control for the SiFive FU540 device and
> implements SoC-level clock tree controls and dividers.
>
> Based on code written by Wesley Terpstra
>
On Sat, 2019-02-09 at 06:31 +, Anup Patel wrote:
> Some of the drivers expect asm/arch/clk.h to be provided by
> arch support code so we add place-holder asm/arch/clk.h for
> RISC-V support.
>
> Signed-off-by: Anup Patel
> ---
> arch/riscv/include/asm/arch/clk.h | 14 ++
> 1
On Sat, 2019-02-09 at 06:31 +, Anup Patel wrote:
> Currently, the mrproper make target tries to force remove all
> "arch/*/include/asm/arch" paths assuming they are symlinks but
> this prevents us from adding place-holder headers under the
> arch/riscv/include/asm/arch directory.
>
> To solve
On Sat, 2019-02-09 at 06:31 +, Anup Patel wrote:
> We will be adding place-holder headers under include/asm/arch
> for RISC-V so this patch updates .gitignore to not consider
> files under arch/riscv/include/asm/arch
>
> Signed-off-by: Anup Patel
> ---
> arch/.gitignore | 1 +
> 1 file
On Mon, 2019-01-21 at 12:39 +, Auer, Lukas wrote:
> On Sun, 2019-01-20 at 17:07 -0800, Atish Patra wrote:
> > On 1/20/19 12:22 PM, Auer, Lukas wrote:
> > > Hi Anup,
> > >
> > > On Fri, 2019-01-18 at 11:19 +, Anup Patel wrote:
> > > > From: Atish Patra
> > > >
> > > > It is possible that
On Sat, 2019-02-02 at 09:06 -0800, Paul Walmsley wrote:
> On Tue, 22 Jan 2019, Auer, Lukas wrote:
>
> > For the same reason, I agree with you that it does not make sense
> > to
> > implement the SBI in U-Boot. OpenSBI is better suited to handle
> > this.
>
> It should be possible to link the
asm/io.h is the header file containing the central MMIO accessor macros.
Judging by the header and the comments, it was apparently once copied
from the Linux kernel, but has deviated since then heavily.
Clean up the definitions by:
- removing pointless Linux history
- removing commented code
-
The timing registers in the DRAM controller can be programmed in any
order, as they will only take effect once the controller is eventually
"activated".
Switch the MMIO writes in mctl_set_timing_lpddr3() over to use
writel_relaxed(), since we don't need the stronger guarantee of the
normal
The normal MMIO accessor macros (readX/writeX) guarantee a strong ordering,
even with normal memory accesses: https://lwn.net/Articles/698014/
For some MMIO operations (framebuffers being a prominent example) this is
not needed, and the rather costly barrier inserted on weakly ordered
systems like
Hi, this is a resend of what I posted some weeks ago, just adding the
missing Signed-off-by: in patch 2/3, as pointed out by Philipp. I used
the opportunity to add his Reviewed-by: tags on the first two patches.
(Many thanks for that!) The rest is unchanged.
---
Admittedly this is
On Sun, Feb 10, 2019 at 02:48:32PM +0100, Alexander Graf wrote:
>
>
> > Am 10.02.2019 um 14:16 schrieb Tom Rini :
> >
> >> On Fri, Feb 08, 2019 at 08:58:18AM +0100, Alexander Graf wrote:
> >>
> >>
> >>> Am 08.02.2019 um 05:11 schrieb Simon Glass :
> >>>
> >>> Hi Alex,
> >>>
> On Sat, 2
On Sun, Feb 10, 2019 at 7:30 AM Adam Ford wrote:
>
> On Mon, Feb 4, 2019 at 12:17 PM Tim Harvey wrote:
> >
> > On Wed, Jan 2, 2019 at 6:37 PM Adam Ford wrote:
> > >
> > > The LogicPD board uses a Micron Flash with ECC. To boot this from
> > > SPL, the ECC needs to be correctly configured or
> Am 10.02.2019 um 14:16 schrieb Tom Rini :
>
>> On Fri, Feb 08, 2019 at 08:58:18AM +0100, Alexander Graf wrote:
>>
>>
>>> Am 08.02.2019 um 05:11 schrieb Simon Glass :
>>>
>>> Hi Alex,
>>>
On Sat, 2 Feb 2019 at 09:07, Alexander Graf wrote:
> Am 02.02.2019 um
Hi Jean-Jacques,
On Fri, 8 Feb 2019 at 12:31, Jean-Jacques Hiblot wrote:
>
> + Simon
>
> On 05/02/2019 15:48, Jean-Jacques Hiblot wrote:
> >
> > On 05/02/2019 14:45, Tom Rini wrote:
> >> On Mon, Feb 04, 2019 at 12:19:19PM +0100, Jean-Jacques Hiblot wrote:
> >>> We need to make sure that file
On Mon, Feb 4, 2019 at 12:20 PM Tim Harvey wrote:
>
> On Thu, Jan 17, 2019 at 5:17 AM Adam Ford wrote:
> >
> > The initialization of the NAND in SPL hard-coded ecc.bytes,
> > ecc.size, and ecc.strength which may work for some NAND parts,
> > but it not appropriate for others. With the pending
On Mon, Feb 4, 2019 at 12:17 PM Tim Harvey wrote:
>
> On Wed, Jan 2, 2019 at 6:37 PM Adam Ford wrote:
> >
> > The LogicPD board uses a Micron Flash with ECC. To boot this from
> > SPL, the ECC needs to be correctly configured or the BCH engine
> > times out.
> >
> > Signed-off-by: Adam Ford
>
On Tue, Jan 15, 2019 at 10:26:37PM +0800, Shawn Guo wrote:
> Some platforms choose to store device tree blob in Android image second
> area. Let's try to look for dtb from there when booting an Android
> image, and use it for booting if found.
>
> Signed-off-by: Shawn Guo
Applied to
On Thu, Jan 31, 2019 at 06:57:38PM +0100, Philippe Reynes wrote:
> This commit add watchdog and sysreset watchdog
> in the bcm63158 device tree.
>
> Signed-off-by: Philippe Reynes
Applied to u-boot/master, thanks!
--
Tom
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On Mon, Feb 04, 2019 at 03:14:17PM +0100, Philippe Reynes wrote:
> The name of the board is bcm968580xref,
> so rename the config to bcm968580xref too.
>
> Signed-off-by: Philippe Reynes
Applied to u-boot/master, thanks!
--
Tom
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